optimize uuid usage in init script

[i2c@gpio5] Support for changing sda and scl at insmod time.

.gitignore

@@ -1,6 +1,11 @@
 *~
 *.swp
+*.o
+*.ko
+*.d
 host-tools/
+host-tools
+*.sqfs
 build/tools/common/sd_tools/genimage.cfg.tmp
 fsbl/build/*
 install/*
@@ -179,3 +184,239 @@ buildroot/board/cvitek/SG200X/overlay/mnt/system/sdk-release
 buildroot/board/cvitek/SG200X/overlay/mnt/system/auto.sh
 middleware/v2/mod_tmp/*
 cscope.out
+middleware/v2/3rdparty/inih/ini.d
+middleware/v2/3rdparty/inih/ini.o
+middleware/v2/component/isp/sensor/cv182x/gcore_gc4653/gc4653_cmos.d
+middleware/v2/component/isp/sensor/cv182x/gcore_gc4653/gc4653_cmos.o
+middleware/v2/component/isp/sensor/cv182x/gcore_gc4653/gc4653_sensor_ctl.d
+middleware/v2/component/isp/sensor/cv182x/gcore_gc4653/gc4653_sensor_ctl.o
+middleware/v2/component/isp/sensor/cv182x/ov_os04a10/os04a10_cmos.d
+middleware/v2/component/isp/sensor/cv182x/ov_os04a10/os04a10_cmos.o
+middleware/v2/component/isp/sensor/cv182x/ov_os04a10/os04a10_sensor_ctl.d
+middleware/v2/component/isp/sensor/cv182x/ov_os04a10/os04a10_sensor_ctl.o
+middleware/v2/lib/libsns_os04a10.a
+middleware/v2/lib/libsns_os04a10.so
+middleware/v2/modules/bin/src/cvi_bin.d
+middleware/v2/modules/bin/src/cvi_bin.o
+middleware/v2/modules/bin/src/md5.d
+middleware/v2/modules/bin/src/md5.o
+middleware/v2/modules/bin/src/rw_json.d
+middleware/v2/modules/bin/src/rw_json.o
+middleware/v2/modules/bin/src/vo_bin.d
+middleware/v2/modules/bin/src/vo_bin.o
+middleware/v2/modules/bin/src/vo_json_struct.d
+middleware/v2/modules/bin/src/vo_json_struct.o
+middleware/v2/modules/bin/src/vpss_bin.d
+middleware/v2/modules/bin/src/vpss_bin.o
+middleware/v2/modules/bin/src/vpss_json_struct.d
+middleware/v2/modules/bin/src/vpss_json_struct.o
+middleware/v2/modules/ive/src/cvi_ive.d
+middleware/v2/modules/ive/src/cvi_ive.o
+middleware/v2/modules/mipi_tx/src/mipi_tx.d
+middleware/v2/modules/mipi_tx/src/mipi_tx.o
+middleware/v2/modules/misc/src/cvi_misc.d
+middleware/v2/modules/misc/src/cvi_misc.o
+middleware/v2/modules/osdc/src/cmpr_canvas.d
+middleware/v2/modules/osdc/src/cmpr_canvas.o
+middleware/v2/modules/osdc/src/cvi_osdc.d
+middleware/v2/modules/osdc/src/cvi_osdc.o
+middleware/v2/modules/osdc/src/osd_cmpr.d
+middleware/v2/modules/osdc/src/osd_cmpr.o
+middleware/v2/modules/sys/src/cvi_base.d
+middleware/v2/modules/sys/src/cvi_base.o
+middleware/v2/modules/sys/src/cvi_sys.d
+middleware/v2/modules/sys/src/cvi_sys.o
+middleware/v2/modules/sys/src/cvi_thermal.d
+middleware/v2/modules/sys/src/cvi_thermal.o
+middleware/v2/modules/sys/src/cvi_tracer.d
+middleware/v2/modules/sys/src/cvi_tracer.o
+middleware/v2/modules/sys/src/cvi_vb.d
+middleware/v2/modules/sys/src/cvi_vb.o
+middleware/v2/modules/sys/src/devmem.d
+middleware/v2/modules/sys/src/devmem.o
+middleware/v2/modules/sys/src/hashmap.d
+middleware/v2/modules/sys/src/hashmap.o
+middleware/v2/modules/sys/src/peri.d
+middleware/v2/modules/sys/src/peri.o
+middleware/v2/modules/sys/src/sys_ioctl.d
+middleware/v2/modules/sys/src/sys_ioctl.o
+middleware/v2/modules/sys/src/vb_ioctl.d
+middleware/v2/modules/sys/src/vb_ioctl.o
+middleware/v2/modules/vdec/src/cvi_vdec.d
+middleware/v2/modules/vdec/src/cvi_vdec.o
+middleware/v2/modules/venc/src/cvi_venc.d
+middleware/v2/modules/venc/src/cvi_venc.o
+middleware/v2/modules/vpu/src/cvi_gdc_1822.d
+middleware/v2/modules/vpu/src/cvi_gdc_1822.o
+middleware/v2/modules/vpu/src/cvi_region.d
+middleware/v2/modules/vpu/src/cvi_region.o
+middleware/v2/modules/vpu/src/cvi_vi.d
+middleware/v2/modules/vpu/src/cvi_vi.o
+middleware/v2/modules/vpu/src/cvi_vo.d
+middleware/v2/modules/vpu/src/cvi_vo.o
+middleware/v2/modules/vpu/src/cvi_vpss.d
+middleware/v2/modules/vpu/src/cvi_vpss.o
+middleware/v2/modules/vpu/src/dump_register.d
+middleware/v2/modules/vpu/src/dump_register.o
+middleware/v2/modules/vpu/src/dwa_ioctl.d
+middleware/v2/modules/vpu/src/dwa_ioctl.o
+middleware/v2/modules/vpu/src/gdc_mesh_1822.d
+middleware/v2/modules/vpu/src/gdc_mesh_1822.o
+middleware/v2/modules/vpu/src/rgn_ioctl.d
+middleware/v2/modules/vpu/src/rgn_ioctl.o
+middleware/v2/modules/vpu/src/vi_ioctl.d
+middleware/v2/modules/vpu/src/vi_ioctl.o
+middleware/v2/modules/vpu/src/vo_ioctl.d
+middleware/v2/modules/vpu/src/vo_ioctl.o
+middleware/v2/modules/vpu/src/vpss_ioctl.d
+middleware/v2/modules/vpu/src/vpss_ioctl.o
+middleware/v2/sample/audio/aac_sample/cvi_audio_aac_adp.d
+middleware/v2/sample/audio/aac_sample/cvi_audio_aac_adp.o
+middleware/v2/sample/audio/cvi_audio_dl_adp.d
+middleware/v2/sample/audio/cvi_audio_dl_adp.o
+middleware/v2/sample/audio/cvi_audio_parse_param.d
+middleware/v2/sample/audio/cvi_audio_parse_param.o
+middleware/v2/sample/audio/cvi_sample_audio.d
+middleware/v2/sample/audio/cvi_sample_audio.o
+middleware/v2/sample/audio/sample_audio
+middleware/v2/sample/common/loadbmp.d
+middleware/v2/sample/common/loadbmp.o
+middleware/v2/sample/common/md5sum.d
+middleware/v2/sample/common/md5sum.o
+middleware/v2/sample/common/sample_common_bin.d
+middleware/v2/sample/common/sample_common_bin.o
+middleware/v2/sample/common/sample_common_isp.d
+middleware/v2/sample/common/sample_common_isp.o
+middleware/v2/sample/common/sample_common_peripheral.d
+middleware/v2/sample/common/sample_common_peripheral.o
+middleware/v2/sample/common/sample_common_platform.d
+middleware/v2/sample/common/sample_common_platform.o
+middleware/v2/sample/common/sample_common_region.d
+middleware/v2/sample/common/sample_common_region.o
+middleware/v2/sample/common/sample_common_sensor.d
+middleware/v2/sample/common/sample_common_sensor.o
+middleware/v2/sample/common/sample_common_sys.d
+middleware/v2/sample/common/sample_common_sys.o
+middleware/v2/sample/common/sample_common_vdec.d
+middleware/v2/sample/common/sample_common_vdec.o
+middleware/v2/sample/common/sample_common_venc.d
+middleware/v2/sample/common/sample_common_venc.o
+middleware/v2/sample/common/sample_common_vi.d
+middleware/v2/sample/common/sample_common_vi.o
+middleware/v2/sample/common/sample_common_vo.d
+middleware/v2/sample/common/sample_common_vo.o
+middleware/v2/sample/common/sample_common_vpss.d
+middleware/v2/sample/common/sample_common_vpss.o
+middleware/v2/sample/fisheye/sample_fisheye
+middleware/v2/sample/fisheye/sample_fisheye.d
+middleware/v2/sample/fisheye/sample_fisheye.o
+middleware/v2/sample/ir_auto/ir_auto
+middleware/v2/sample/ir_auto/ir_auto.d
+middleware/v2/sample/ir_auto/ir_auto.o
+middleware/v2/sample/ive/sample_16bitto8bit
+middleware/v2/sample/ive/sample_add
+middleware/v2/sample/ive/sample_and
+middleware/v2/sample/ive/sample_bernsen
+middleware/v2/sample/ive/sample_bgmodel
+middleware/v2/sample/ive/sample_cannyedge
+middleware/v2/sample/ive/sample_cannyhysedge
+middleware/v2/sample/ive/sample_csc
+middleware/v2/sample/ive/sample_dilate
+middleware/v2/sample/ive/sample_dma
+middleware/v2/sample/ive/sample_erode
+middleware/v2/sample/ive/sample_filter
+middleware/v2/sample/ive/sample_filterandcsc
+middleware/v2/sample/ive/sample_framediffmotion
+middleware/v2/sample/ive/sample_gmm
+middleware/v2/sample/ive/sample_gmm2
+middleware/v2/sample/ive/sample_gradfg
+middleware/v2/sample/ive/sample_hist
+middleware/v2/sample/ive/sample_integ
+middleware/v2/sample/ive/sample_lbp
+middleware/v2/sample/ive/sample_magandang
+middleware/v2/sample/ive/sample_map
+middleware/v2/sample/ive/sample_ncc
+middleware/v2/sample/ive/sample_normgrad
+middleware/v2/sample/ive/sample_or
+middleware/v2/sample/ive/sample_ordstatfilter
+middleware/v2/sample/ive/sample_query
+middleware/v2/sample/ive/sample_resize
+middleware/v2/sample/ive/sample_sad
+middleware/v2/sample/ive/sample_sobel
+middleware/v2/sample/ive/sample_stcandicorner
+middleware/v2/sample/ive/sample_sub
+middleware/v2/sample/ive/sample_thresh
+middleware/v2/sample/ive/sample_thresh_S16
+middleware/v2/sample/ive/sample_thresh_U16
+middleware/v2/sample/ive/sample_xor
+middleware/v2/sample/mipi_tx/lt9611/lt9611
+middleware/v2/sample/mipi_tx/lt9611/lt9611.d
+middleware/v2/sample/mipi_tx/lt9611/lt9611.o
+middleware/v2/sample/mipi_tx/sample_dsi
+middleware/v2/sample/mipi_tx/sample_dsi.d
+middleware/v2/sample/mipi_tx/sample_dsi.o
+middleware/v2/sample/osdc/sample_osdc
+middleware/v2/sample/osdc/sample_osdc.d
+middleware/v2/sample/osdc/sample_osdc.o
+middleware/v2/sample/overlay/sample_overlay
+middleware/v2/sample/overlay/sample_overlay.d
+middleware/v2/sample/overlay/sample_overlay.o
+middleware/v2/sample/region/sample_region
+middleware/v2/sample/region/sample_region.d
+middleware/v2/sample/region/sample_region.o
+middleware/v2/sample/sample_panel/sample_panel.d
+middleware/v2/sample/sample_panel/sample_panel.o
+middleware/v2/sample/scene_auto/sample_scene_auto
+middleware/v2/sample/scene_auto/src/core/cvi_scene.d
+middleware/v2/sample/scene_auto/src/core/cvi_scene.o
+middleware/v2/sample/scene_auto/src/core/cvi_scene_setparam.d
+middleware/v2/sample/scene_auto/src/core/cvi_scene_setparam.o
+middleware/v2/sample/scene_auto/src/sample/cvi_scene_decode.d
+middleware/v2/sample/scene_auto/src/sample/cvi_scene_decode.o
+middleware/v2/sample/scene_auto/src/sample/cvi_scene_loadparam.d
+middleware/v2/sample/scene_auto/src/sample/cvi_scene_loadparam.o
+middleware/v2/sample/scene_auto/src/sample/sample_scene.d
+middleware/v2/sample/scene_auto/src/sample/sample_scene.o
+middleware/v2/sample/scene_auto/src/sample/sample_scene_main.d
+middleware/v2/sample/scene_auto/src/sample/sample_scene_main.o
+middleware/v2/sample/scene_auto/tools/iniparser/src/dictionary.d
+middleware/v2/sample/scene_auto/tools/iniparser/src/dictionary.o
+middleware/v2/sample/scene_auto/tools/iniparser/src/iniparser.d
+middleware/v2/sample/scene_auto/tools/iniparser/src/iniparser.o
+middleware/v2/sample/sensor_test/sensor_test
+middleware/v2/sample/sensor_test/sensor_test.d
+middleware/v2/sample/sensor_test/sensor_test.o
+middleware/v2/sample/sensor_test/src/ae_test.d
+middleware/v2/sample/sensor_test/src/ae_test.o
+middleware/v2/sample/vdec/sample_vdec
+middleware/v2/sample/vdec/sample_vdec.d
+middleware/v2/sample/vdec/sample_vdec.o
+middleware/v2/sample/vdec/sample_vdec_asan
+middleware/v2/sample/vdec/src/sample_vdec_lib.d
+middleware/v2/sample/vdec/src/sample_vdec_lib.o
+middleware/v2/sample/vdec/src/sample_vdec_testcase.d
+middleware/v2/sample/vdec/src/sample_vdec_testcase.o
+middleware/v2/sample/vdecvo/sample_vdecvo
+middleware/v2/sample/vdecvo/sample_vdecvo.d
+middleware/v2/sample/vdecvo/sample_vdecvo.o
+middleware/v2/sample/venc/sample_vcodec
+middleware/v2/sample/venc/sample_vcodec.d
+middleware/v2/sample/venc/sample_vcodec.o
+middleware/v2/sample/venc/sample_vcodec_asan
+middleware/v2/sample/venc/sample_venc
+middleware/v2/sample/venc/sample_venc.d
+middleware/v2/sample/venc/sample_venc.o
+middleware/v2/sample/venc/sample_venc_asan
+middleware/v2/sample/venc/src/sample_venc_lib.d
+middleware/v2/sample/venc/src/sample_venc_lib.o
+middleware/v2/sample/venc/src/sample_venc_testcase.d
+middleware/v2/sample/venc/src/sample_venc_testcase.o
+middleware/v2/sample/vio/sample_vio
+middleware/v2/sample/vio/sample_vio.d
+middleware/v2/sample/vio/sample_vio.o
+middleware/v2/sample/vio/sample_vio_main.d
+middleware/v2/sample/vio/sample_vio_main.o
+osdrv/extdrv/wireless/.tmp_4261/
+middleware/v2/lib
+host-tools/
+kvm/

README.md

@@ -1,13 +1,60 @@
 # LicheeRV-Nano-Build
 
-# how to build
+# download source
 
 ```
-git clone https://github.com/LicheeRV-Nano-Build --depth=1
+git clone https://github.com/sipeed/LicheeRV-Nano-Build --depth=1
 cd LicheeRV-Nano-Build
-wget https://sophon-file.sophon.cn/sophon-prod-s3/drive/23/03/07/16/host-tools.tar.gz
-tar xf host-tools.tar.gz
+git clone https://github.com/sophgo/host-tools --depth=1
+```
+
+## host environment
+
+you can use container:
+
+```
+cd host/ubuntu
+docker build -t licheervnano-build-ubuntu .
+docker run --name licheervnano-build-ubuntu licheervnano-build-ubuntu
+docker export licheervnano-build-ubuntu | sqfstar licheervnano-build-ubuntu.sqfs
+singularity shell -e licheervnano-build-ubuntu.sqfs
+```
+
+# build it
+
+```
 source build/cvisetup.sh
+# C906:
 defconfig sg2002_licheervnano_sd
+# A53:
+# defconfig sg2002_licheea53nano_sd
 build_all
 ```
+
+# build fail
+
+on some system, qt5svg or qt5base will build failed on first build, please retry command:
+
+```
+build_all
+```
+
+# how to modify image after build:
+
+```
+# first partition
+touch wifi.sta
+mcopy -i install/xxx/xxx.img@@1s wifi.sta ::/
+
+# second partition
+./host/mount_ext4.sh install/xxx/xxx.img mountpoint
+cd mountpoint
+touch xxx
+```
+
+# logo
+
+```
+./host/make_logo.sh input.jpeg logo.jpeg
+mcopy -i install/xxx/xxx.img@@1s logo.jpeg ::/
+```

build/Makefile

@@ -559,6 +559,7 @@ br-rootfs-pack:
 	# ${Q}rm -rf $(BR_ROOTFS_DIR)/*
 	# copy rootfs to rawimg dir
 	${Q}cp $(BR_DIR)/output/images/rootfs.ext4 $(OUTPUT_DIR)/rawimages/rootfs.$(STORAGE_TYPE)
+	${Q}tar zcvf $(OUTPUT_DIR)/licheervnano-drivers.tar.gz $(BR_DIR)/output/target/mnt
 	$(call raw2cimg ,rootfs.$(STORAGE_TYPE))
 
 ifeq ($(CONFIG_BUILDROOT_FS),y)

build/boards/chip_list.json

@@ -4,7 +4,7 @@
   },
 
   "cv181x": {
-    "cv181x": ["cv1811ha", "cv1812cp", "cv1812h", "cv1813h"]
+    "cv181x": ["cv1812cp", "cv1812h", "cv1813h"]
   },
 
   "cv180x": {

build/boards/cv181x/cv1811ha_wevb_0007a_spinor/cv1811ha_wevb_0007a_spinor_defconfig

@@ -1,30 +0,0 @@
-CONFIG_CHIP_cv1811ha=y
-CONFIG_BOARD_wevb_0007a_spinor=y
-CONFIG_DDR_CFG_ddr3_1866_x16=y
-CONFIG_ARCH="arm"
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_KERNEL_ENTRY_HACK=y
-CONFIG_KERNEL_ENTRY_HACK_ADDR="0x80108000"
-CONFIG_TOOLCHAIN_GLIBC_ARM=y
-CONFIG_FLASH_SIZE_SHRINK=y
-CONFIG_BOOT_IMAGE_SINGLE_DTB=y
-CONFIG_STORAGE_TYPE_spinor=y
-CONFIG_SENSOR_GCORE_GC2053=y
-CONFIG_SENSOR_GCORE_GC2053_1L=y
-CONFIG_SENSOR_GCORE_GC2093=y
-CONFIG_SENSOR_GCORE_GC4653=y
-CONFIG_SENSOR_PIXELPLUS_PR2020=y
-CONFIG_SENSOR_SONY_IMX307=y
-CONFIG_SENSOR_SONY_IMX327=y
-CONFIG_UBOOT_2021_10=y
-CONFIG_KERNEL_SRC_5.10=y
-CONFIG_KERNEL_SRC="linux_5.10"
-CONFIG_KERNEL_LZMA=y
-CONFIG_SKIP_RAMDISK=y
-CONFIG_USE_4K_ERASE_SIZE_FOR_JFFS2=y
-CONFIG_SENSOR_TUNING_PARAM_cv181x_src_gcore_gc4653=y
-# CONFIG_ROOTFS_OVERLAYFS is not set
-CONFIG_TARGET_PACKAGE_DROPBEAR=y
-CONFIG_TARGET_PACKAGE_MTD-UTILS=y
-# CONFIG_TARGET_PACKAGE_RSYSLOG is not set
-# CONFIG_TARGET_PACKAGE_GATORD is not set

build/boards/cv181x/cv1811ha_wevb_0007a_spinor/dts_arm/cv1811ha_wevb_0007a_spinor.dts

@@ -1,10 +0,0 @@
-/dts-v1/;
-#include "cv181x_base_arm.dtsi"
-#include "cv181x_asic_bga.dtsi"
-#include "cv181x_asic_spinor.dtsi"
-#include "cv181x_default_memmap.dtsi"
-
-/ {
-
-};
-

build/boards/cv181x/cv1811ha_wevb_0007a_spinor/linux/cv1811ha_wevb_0007a_spinor_defconfig

@@ -1,282 +0,0 @@
-CONFIG_KERNEL_XZ=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_LOG_BUF_SHIFT=15
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSFS_SYSCALL is not set
-# CONFIG_FHANDLE is not set
-# CONFIG_BASE_FULL is not set
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_ARM_LPAE=y
-CONFIG_SWP_EMULATE=y
-# CONFIG_VDSO is not set
-CONFIG_HAVE_ARM_ARCH_TIMER=y
-CONFIG_ARM_PSCI=y
-CONFIG_THUMB2_KERNEL=y
-CONFIG_FORCE_MAX_ZONEORDER=10
-# CONFIG_ATAGS is not set
-CONFIG_VFP=y
-CONFIG_NEON=y
-# CONFIG_SUSPEND is not set
-CONFIG_ARCH_CVITEK=y
-CONFIG_ARCH_CV181X=y
-CONFIG_ARCH_CVITEK_CHIP="mars"
-CONFIG_ARCH_CV181X_ASIC=y
-CONFIG_POWER_RESET=y
-# CONFIG_STACKPROTECTOR is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-# CONFIG_MQ_IOSCHED_DEADLINE is not set
-# CONFIG_MQ_IOSCHED_KYBER is not set
-# CONFIG_COREDUMP is not set
-CONFIG_CMA=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_CFG80211=m
-CONFIG_RFKILL=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_ALLOW_DEV_COREDUMP is not set
-CONFIG_DMA_CMA=n
-CONFIG_CMA_SIZE_MBYTES=0
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_OF_PARTS is not set
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_MTD_NAND_CVSNFC=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_SPI_CVI_SPIF=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_CORE is not set
-# CONFIG_NET_VENDOR_ALACRITECH is not set
-# CONFIG_NET_VENDOR_AMAZON is not set
-# CONFIG_NET_VENDOR_AQUANTIA is not set
-# CONFIG_NET_VENDOR_ARC is not set
-# CONFIG_NET_VENDOR_AURORA is not set
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CADENCE is not set
-# CONFIG_NET_VENDOR_CAVIUM is not set
-# CONFIG_NET_VENDOR_CIRRUS is not set
-# CONFIG_NET_VENDOR_CORTINA is not set
-# CONFIG_NET_VENDOR_EZCHIP is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_HISILICON is not set
-# CONFIG_NET_VENDOR_HUAWEI is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MELLANOX is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_MICROSEMI is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_NETRONOME is not set
-# CONFIG_NET_VENDOR_NI is not set
-# CONFIG_NET_VENDOR_QUALCOMM is not set
-# CONFIG_NET_VENDOR_RENESAS is not set
-# CONFIG_NET_VENDOR_ROCKER is not set
-# CONFIG_NET_VENDOR_SAMSUNG is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SOLARFLARE is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_SOCIONEXT is not set
-CONFIG_STMMAC_ETH=y
-# CONFIG_DWMAC_GENERIC is not set
-# CONFIG_NET_VENDOR_SYNOPSYS is not set
-# CONFIG_NET_VENDOR_VIA is not set
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_CVITEK_PHY=y
-# CONFIG_USB_NET_DRIVERS is not set
-# CONFIG_WLAN_VENDOR_ADMTEK is not set
-# CONFIG_WLAN_VENDOR_ATH is not set
-# CONFIG_WLAN_VENDOR_ATMEL is not set
-# CONFIG_WLAN_VENDOR_BROADCOM is not set
-# CONFIG_WLAN_VENDOR_CISCO is not set
-# CONFIG_WLAN_VENDOR_INTEL is not set
-# CONFIG_WLAN_VENDOR_INTERSIL is not set
-# CONFIG_WLAN_VENDOR_MARVELL is not set
-# CONFIG_WLAN_VENDOR_MEDIATEK is not set
-# CONFIG_WLAN_VENDOR_RALINK is not set
-CONFIG_RTL8188FU=m
-# CONFIG_WLAN_VENDOR_RSI is not set
-# CONFIG_WLAN_VENDOR_ST is not set
-# CONFIG_WLAN_VENDOR_TI is not set
-# CONFIG_WLAN_VENDOR_ZYDAS is not set
-CONFIG_INPUT=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=5
-CONFIG_SERIAL_8250_RUNTIME_UARTS=5
-CONFIG_SERIAL_8250_DW=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_SMBUS=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_DESIGNWARE_PLATFORM=y
-CONFIG_SPI=y
-# CONFIG_PTP_1588_CLOCK is not set
-CONFIG_CVITEK_PINCTRL_CV1835=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_DWAPB=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_NETLINK=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THERMAL_EMULATION=y
-CONFIG_WATCHDOG=y
-CONFIG_MEDIA_SUPPORT=n
-CONFIG_VIDEO_CVITEK=m
-CONFIG_VIDEO_CVITEK_CIF=m
-CONFIG_VIDEO_CVITEK_SNS_I2C=m
-CONFIG_VIDEO_CVITEK_MIPI_TX=m
-CONFIG_FB=y
-CONFIG_FB_CVITEK=m
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_PROC_FS is not set
-# CONFIG_SND_DRIVERS is not set
-CONFIG_SND_HDA_PREALLOC_SIZE=n
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_CV182XA_CV182XAADC=y
-CONFIG_SND_SOC_CV182XA_CV182XADAC=y
-CONFIG_SND_CV1835_I2S=y
-CONFIG_SND_SOC_CV182XAADC=y
-CONFIG_SND_SOC_CV182XADAC=y
-# CONFIG_SND_SOC_CV182X_CV182XPDM is not set
-# CONFIG_SND_SOC_CV1835PDM is not set
-# CONFIG_SND_SOC_CV1835_CONCURRENT_I2S is not set
-CONFIG_SND_SOC_CV1835_USE_AUDIO_PLL=y
-CONFIG_CV1835_I2S_SUBSYS=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_CVI=y
-CONFIG_DMADEVICES=n
-CONFIG_DW_DMAC_CVITEK=n
-# CONFIG_VIRTIO_MENU is not set
-CONFIG_STAGING=y
-CONFIG_ION=y
-CONFIG_ION_SYSTEM_HEAP=y
-CONFIG_ION_CARVEOUT_HEAP=y
-CONFIG_ION_CMA_HEAP=y
-# CONFIG_IOMMU_SUPPORT is not set
-CONFIG_CV1835_SYSDMA_REMAP=n
-CONFIG_PWM=y
-CONFIG_ANDROID=y
-# CONFIG_TEE=y
-# CONFIG_OPTEE=y
-# CONFIG_MANDATORY_FILE_LOCKING is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_CONFIGFS_FS=m
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-CONFIG_UBIFS_FS=y
-CONFIG_SQUASHFS=y
-CONFIG_SQUASHFS_FILE_DIRECT=y
-# CONFIG_SQUASHFS_ZLIB is not set
-CONFIG_SQUASHFS_XZ=y
-CONFIG_SQUASHFS_EMBEDDED=y
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=1
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V2=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=y
-CONFIG_NLS_ISO8859_3=y
-# CONFIG_CRYPTO_ECHAINIV is not set
-CONFIG_CRYPTO_SHA256=y
-# CONFIG_CRYPTO_HW is not set
-# CONFIG_XZ_DEC_X86 is not set
-# CONFIG_XZ_DEC_POWERPC is not set
-# CONFIG_XZ_DEC_IA64 is not set
-# CONFIG_XZ_DEC_ARMTHUMB is not set
-# CONFIG_XZ_DEC_SPARC is not set
-CONFIG_PRINTK_TIME=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_FTRACE is not set
-# CONFIG_RUNTIME_TESTING_MENU is not set
-# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
-
-CONFIG_RTC_CLASS=y
-
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_USB=y
-CONFIG_USB_OTG=y
-CONFIG_USB_OTG_FSM=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_LIBCOMPOSITE=y
-CONFIG_USB_F_ACM=y
-CONFIG_USB_U_SERIAL=y
-CONFIG_USB_U_ETHER=y
-CONFIG_USB_U_AUDIO=y
-CONFIG_USB_F_SERIAL=y
-CONFIG_USB_F_ECM=y
-CONFIG_USB_F_EEM=y
-CONFIG_USB_F_RNDIS=y
-CONFIG_USB_F_MASS_STORAGE=y
-CONFIG_USB_F_UAC1=y
-CONFIG_USB_F_UVC=y
-CONFIG_USB_UAS=y
-CONFIG_USB_DWC2=m
-CONFIG_USB_DWC2_DUAL_ROLE=y
-CONFIG_USB_GADGET=y
-CONFIG_U_SERIAL_CONSOLE=y
-CONFIG_USB_CONFIGFS=y
-CONFIG_USB_CONFIGFS_SERIAL=y
-CONFIG_USB_CONFIGFS_ACM=y
-CONFIG_USB_CONFIGFS_ECM=y
-CONFIG_USB_CONFIGFS_RNDIS=y
-CONFIG_USB_CONFIGFS_EEM=y
-CONFIG_USB_CONFIGFS_MASS_STORAGE=y
-CONFIG_USB_CONFIGFS_F_FS=y
-CONFIG_USB_CONFIGFS_F_UAC1=y
-CONFIG_USB_CONFIGFS_F_UVC=y
-CONFIG_USB_CONFIGFS_F_FS=y
-CONFIG_USB_CONFIGFS_UEVENT=y
-CONFIG_USB_PHY=y
-CONFIG_USB_GPIO_VBUS=y

build/boards/cv181x/cv1811ha_wevb_0007a_spinor/memmap.py

@@ -1,85 +0,0 @@
-SIZE_1M = 0x100000
-SIZE_1K = 1024
-
-
-# Only attributes in class MemoryMap are generated to .h
-class MemoryMap:
-    # No prefix "CVIMMAP_" for the items in _no_prefix[]
-    _no_prefix = [
-        "CONFIG_SYS_TEXT_BASE"  # u-boot's CONFIG_SYS_TEXT_BASE is used without CPP.
-    ]
-
-    DRAM_BASE = 0x80000000
-    DRAM_SIZE = 128 * SIZE_1M
-
-    # ==============
-    # C906L FreeRTOS
-    # ==============
-    FREERTOS_SIZE = 768 * SIZE_1K
-    # FreeRTOS is at the end of DRAM
-    FREERTOS_ADDR = DRAM_BASE + DRAM_SIZE - FREERTOS_SIZE
-    FSBL_C906L_START_ADDR = FREERTOS_ADDR
-
-    # ==============================
-    # OpenSBI | arm-trusted-firmware
-    # ==============================
-    # Monitor is at the begining of DRAM
-    MONITOR_ADDR = DRAM_BASE
-
-    ATF_SIZE = 512 * SIZE_1K
-    OPENSBI_SIZE = 512 * SIZE_1K
-    OPENSBI_FDT_ADDR = MONITOR_ADDR + OPENSBI_SIZE
-
-    # =========================
-    # memory@DRAM_BASE in .dts.
-    # =========================
-    # Ignore the area of FreeRTOS in u-boot and kernel
-    KERNEL_MEMORY_ADDR = DRAM_BASE
-    KERNEL_MEMORY_SIZE = DRAM_SIZE - FREERTOS_SIZE
-
-    # =================
-    # Multimedia buffer. Used by u-boot/kernel/FreeRTOS
-    # =================
-    ION_SIZE = 70 * SIZE_1M
-    H26X_BITSTREAM_SIZE = 2 * SIZE_1M
-    H26X_ENC_BUFF_SIZE = 0
-    ISP_MEM_BASE_SIZE = 20 * SIZE_1M
-    FREERTOS_RESERVED_ION_SIZE = H26X_BITSTREAM_SIZE + H26X_ENC_BUFF_SIZE + ISP_MEM_BASE_SIZE
-
-    # ION after FreeRTOS
-    ION_ADDR = FREERTOS_ADDR - ION_SIZE
-
-    # Buffers of the fast image are inside the ION buffer
-    H26X_BITSTREAM_ADDR = ION_ADDR
-    H26X_ENC_BUFF_ADDR = H26X_BITSTREAM_ADDR + H26X_BITSTREAM_SIZE
-    ISP_MEM_BASE_ADDR = H26X_ENC_BUFF_ADDR + H26X_ENC_BUFF_SIZE
-
-    assert ISP_MEM_BASE_ADDR + ISP_MEM_BASE_SIZE <= ION_ADDR + ION_SIZE
-
-    # Boot logo is after the ION buffer
-    # Framebuffer uses boot logo's reserved memory
-    BOOTLOGO_SIZE = 1800 * SIZE_1K
-    BOOTLOGO_ADDR = ION_ADDR - BOOTLOGO_SIZE
-    FRAMEBUFFER_SIZE = BOOTLOGO_SIZE
-    FRAMEBUFFER_ADDR = BOOTLOGO_ADDR
-
-    # ===================
-    # FSBL and u-boot-2021
-    # ===================
-    CVI_UPDATE_HEADER_SIZE = SIZE_1K
-    UIMAG_SIZE = 16 * SIZE_1M
-
-    # kernel image loading buffer
-    UIMAG_ADDR = DRAM_BASE + 24 * SIZE_1M
-    CVI_UPDATE_HEADER_ADDR = UIMAG_ADDR - CVI_UPDATE_HEADER_SIZE
-
-    # FSBL decompress buffer
-    FSBL_UNZIP_ADDR = UIMAG_ADDR
-    FSBL_UNZIP_SIZE = UIMAG_SIZE
-
-    assert UIMAG_ADDR + UIMAG_SIZE <= BOOTLOGO_ADDR
-
-    # u-boot's run address and entry point
-    CONFIG_SYS_TEXT_BASE = DRAM_BASE + 2 * SIZE_1M
-    # u-boot's init stack point is only used before board_init_f()
-    CONFIG_SYS_INIT_SP_ADDR = UIMAG_ADDR + UIMAG_SIZE

build/boards/cv181x/cv1811ha_wevb_0007a_spinor/partition/partition_spinor.xml

@@ -1,9 +0,0 @@
-<physical_partition type="spinor">
-    <partition label="fip" size_in_kb="1024" readonly="false" file="fip.bin"/>
-    <partition label="BOOT" size_in_kb="3072" readonly="false" file="boot.spinor"/>
-    <partition label="ENV" size_in_kb="64" file="" />
-    <partition label="ENV_BAK" size_in_kb="64" file="" />
-    <partition label="ROOTFS" size_in_kb="11264" readonly="false" file="rootfs.spinor" />
-    <partition label="DATA"  readonly="false" file="" mountpoint="/mnt/data" type="jffs2" />
-</physical_partition>
-

build/boards/cv181x/cv1811ha_wevb_0007a_spinor/u-boot/cv1811ha_wevb_0007a_spinor_defconfig

@@ -1,45 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="cv181x_asic"
-CONFIG_IDENT_STRING=" cvitek_cv181x"
-CONFIG_ARMV8_SET_SMPEN=y
-CONFIG_TARGET_CVITEK_CV181X=y
-CONFIG_CVITEK_SPI_FLASH=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_BOOTDELAY=1
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SYS_PROMPT="cv181x# "
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_LZMADEC is not set
-# CONFIG_CMD_UNLZ4 is not set
-# CONFIG_CMD_UNZIP is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_ITEST is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_CVI_SD_UPDATE=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_MMC_SDHCI_CVITEK=y
-CONFIG_MTD=y
-# CONFIG_PHY_SMSC is not set
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_PHY_CVITEK=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_LZ4=y
-CONFIG_LZMA=y
-# CONFIG_TOOLS_LIBCRYPTO is not set
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set

build/boards/default/dts/cv181x_arm/cv181x_base_arm.dtsi

@@ -1,320 +0,0 @@
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/reset/cv181x-resets.h>
-#include <dt-bindings/clock/cv181x-clock.h>
-#include <dt-bindings/thermal/thermal.h>
-#include <dt-bindings/dma/cv181x-dmamap.h>
-#include "cvi_board_memmap.h"
-
-/memreserve/	CVIMMAP_MONITOR_ADDR CVIMMAP_ATF_SIZE; // ATF (BL31 + BL32) 512KB
-
-#include "cv181x_base.dtsi"
-
-/ {
-	model = "SOPHGO ASIC. ARM.";
-	interrupt-parent = <&gic>;
-
-	#size-cells = <0x2>;
-	#address-cells = <0x2>;
-
-	gic: interrupt-controller {
-		compatible = "arm,cortex-a15-gic";
-		ranges;
-		#size-cells = <0x2>;
-		#address-cells = <0x2>;
-		interrupt-controller;
-		#interrupt-cells = <0x3>;
-		reg = <0x0 0x01F01000 0x0 0x1000>,
-		      <0x0 0x01F02000 0x0 0x2000>;
-	};
-
-	pmu_a53 {
-		compatible = "arm,cortex-a53-pmu";
-		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&A53_0>;
-	};
-
-	psci {
-		migrate = <0xc4000005>;
-		cpu_on = <0xc4000003>;
-		cpu_off = <0x84000002>;
-		cpu_suspend = <0xc4000001>;
-		sys_poweroff = <0x84000008>;
-		sys_reset = <0x84000009>;
-		method = "smc";
-		compatible = "arm,psci-0.2", "arm,psci";
-	};
-
-	cpus {
-		#size-cells = <0x0>;
-		#address-cells = <0x1>;
-
-		A53_0: cpu@0 {
-			reg = <0x0>;
-			enable-method = "psci";
-			compatible = "arm,cortex-a53";
-			device_type = "cpu";
-			next-level-cache = <&CA53_L2>;
-		};
-
-		CA53_L2: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-		always-on;
-		clock-frequency = <25000000>;
-		compatible = "arm,armv8-timer";
-	};
-
-	firmware {
-		optee {
-			compatible = "linaro,optee-tz";
-			method = "smc";
-		};
-	};
-
-	cooling:cooling {
-		clocks = <&clk CV181X_CLK_A53>, <&clk CV181X_CLK_TPU>;
-		clock-names = "clk_cpu", "clk_tpu_axi";
-		dev-freqs = <800000000 500000000>,
-			<400000000 375000000>,
-			<400000000 300000000>;
-		compatible = "sophgo,cooling";
-		#cooling-cells = <2>;
-	};
-
-	tpu {
-		interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
-			     <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
-	};
-
-	mon {
-		interrupts = <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
-	};
-
-	wiegand0 {
-		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	wiegand1 {
-		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	wiegand2 {
-		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	saradc {
-		interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
-	};
-
-	rtc {
-		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	sysdma_remap {
-		int_mux = <0x1FF>; /* enable bit [0..8] for CPU0(CA53) */
-	};
-
-	dmac: dma@0x4330000 {
-		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-#if 0
-	watchdog0: cv-wd@0x3010000 {
-		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
-	};
-#endif
-
-	spinand:cv-spinf@4060000 {
-		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	spif:cvi-spif@10000000 {
-		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	spi0:spi0@04180000 {
-		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	spi1:spi1@04190000 {
-		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	spi2:spi2@041A0000 {
-		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	spi3:spi3@041B0000 {
-		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	uart0: serial@04140000 {
-		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	uart1: serial@04150000 {
-		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	uart2: serial@04160000 {
-		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	uart3: serial@04170000 {
-		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	uart4: serial@041C0000 {
-		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	gpio0: gpio@03020000 {
-		porta: gpio-controller@0 {
-			interrupt-controller;
-			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
-		};
-	};
-
-	gpio1: gpio@03021000 {
-		portb: gpio-controller@1 {
-			interrupt-controller;
-			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
-		};
-	};
-
-	gpio2: gpio@03022000 {
-		portc: gpio-controller@2 {
-			interrupt-controller;
-			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-		};
-	};
-
-	gpio3: gpio@03023000 {
-		portd: gpio-controller@3 {
-			interrupt-controller;
-			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
-		};
-	};
-
-	gpio4: gpio@05021000 {
-		porte: gpio-controller@4 {
-			interrupt-controller;
-			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-		};
-	};
-
-	i2c0: i2c@04000000 {
-		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	i2c1: i2c@04010000 {
-		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	i2c2: i2c@04020000 {
-		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	i2c3: i2c@04030000 {
-		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	i2c4: i2c@04040000 {
-		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	ethernet0: ethernet@4070000 {
-		interrupt-names = "macirq";
-		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	emmc:cv-emmc@4300000 {
-		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	sd:cv-sd@4310000 {
-		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	i2s0: i2s@04100000 {
-		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	i2s1: i2s@04110000 {
-		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	i2s2: i2s@04120000 {
-		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	i2s3: i2s@04130000 {
-		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	wifisd:wifi-sd@4320000 {
-		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	mipi_rx: cif {
-		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "csi0", "csi1";
-	};
-
-	vi {
-		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "isp";
-	};
-
-	ive {
-		interrupt-names = "ive_irq";
-		interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
-	};
-
-	vpss {
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "sc";
-	};
-
-	dwa {
-		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "dwa";
-	};
-
-	vcodec {
-		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "h265","h264","sbm";
-	};
-
-	jpu {
-		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "jpeg";
-	};
-
-	rtos_cmdqu {
-		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "mailbox";
-	};
-
-	usb: usb@04340000 {
-		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	thermal:thermal@030E0000 {
-		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tempsen";
-	};
-
-};

build/boards/default/dts/sg200x/find_and_set.sh

@@ -1,12 +0,0 @@
-#!/bin/bash
-
-files=`find . -name "cv181x_*.dtsi"`
-
-for i in $files
-do
-	echo $i
-filename=${i#*cv181x_}
-echo $filename
-mv $i soph_$filename
-
-done

build/boards/default/dts/sg200x/soph_base.dtsi

@@ -156,21 +156,21 @@
 		compatible = "cvitek,cvi-pwm";
 		reg = <0x0 0x3060000 0x0 0x1000>;
 		clocks = <&clk CV181X_CLK_PWM>;
-		#pwm-cells = <1>;
+		#pwm-cells = <4>;
 	};
 
 	pwm1: pwm@3061000 {
 		compatible = "cvitek,cvi-pwm";
 		reg = <0x0 0x3061000 0x0 0x1000>;
 		clocks = <&clk CV181X_CLK_PWM>;
-		#pwm-cells = <2>;
+		#pwm-cells = <4>;
 	};
 
 	pwm2: pwm@3062000 {
 		compatible = "cvitek,cvi-pwm";
 		reg = <0x0 0x3062000 0x0 0x1000>;
 		clocks = <&clk CV181X_CLK_PWM>;
-		#pwm-cells = <3>;
+		#pwm-cells = <4>;
 	};
 
 	pwm3: pwm@3063000 {
@@ -233,6 +233,7 @@
 		clocks = <&clk CV181X_CLK_SPI>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		bias-pull-up;
 	};
 
 	spi3:spi3@041B0000 {
@@ -865,13 +866,13 @@
 
 			trips {
 				soc_thermal_trip_0: soc_thermal_trip_0 {
-					temperature = <100000>; /* millicelsius */
+					temperature = <110000>; /* millicelsius */
 					hysteresis = <5000>; /* millicelsius */
 					type = "passive";
 				};
 
 				soc_thermal_trip_1: soc_thermal_trip_1 {
-					temperature = <110000>; /* millicelsius */
+					temperature = <120000>; /* millicelsius */
 					hysteresis = <5000>; /* millicelsius */
 					type = "passive";
 				};

build/boards/sg200x/sg2000_duo_sd/dts_riscv/sg2000_duo_sd.dts

@@ -1,7 +1,7 @@
 /dts-v1/;
 #include "soph_base_riscv.dtsi"
 #include "soph_asic_bga.dtsi"
-#include "soph_asic_emmc.dtsi"
+#include "soph_asic_sd.dtsi"
 #include "soph_default_memmap.dtsi"
 
 / {

build/boards/sg200x/sg2000_duo_sd/partition/partition_emmc.xml

@@ -1,11 +0,0 @@
-<physical_partition type="emmc">
-	<partition label="BOOT" size_in_kb="8192" file="boot.emmc" />
-	<partition label="MISC" size_in_kb="512" file="logo.jpg" />
-	<!-- Beware that in emmc u-boot environment should be 0x40000 alignment -->
-	<partition label="ENV" size_in_kb="128" file="" />
-	<partition label="ROOTFS" size_in_kb="70656" file="rootfs.emmc" />
-	<partition label="SYSTEM" size_in_kb="40960" file="system.emmc" type="ext4" />
-    <partition label="CFG" size_in_kb="15240" file="cfg.emmc" mountpoint="/mnt/cfg" type="ext4" />
-	<partition label="DATA" size_in_kb="3145728" file="" mountpoint="/mnt/data" type="ext4"/>
-</physical_partition>
-

build/boards/sg200x/sg2000_duo_sd/partition/partition_sd.xml

@@ -0,0 +1,5 @@
+<physical_partition type="sd">
+    <partition label="BOOT" size_in_kb="80960" readonly="false" file="boot.sd"/>
+    <partition label="ROOTFS" size_in_kb="204800" readonly="false" file="rootfs.sd" />
+    <partition label="DATA"  size_in_kb="512000" readonly="false" file="data.sd" mountpoint="/mnt/data" type="ext4" />
+</physical_partition>

build/boards/sg200x/sg2000_duo_sd/sg2000_duo_sd_defconfig

@@ -1,5 +1,5 @@
 CONFIG_CHIP_sg2000=y
-CONFIG_BOARD_wevb_emmc=y
+CONFIG_BOARD_duo_sd=y
 CONFIG_DDR_CFG_ddr3_1866_x16=y
 CONFIG_ARCH="riscv"
 CONFIG_CROSS_COMPILE="riscv64-unknown-linux-gnu-"
@@ -9,7 +9,7 @@ CONFIG_KERNEL_ENTRY_HACK_ADDR="0x80200000"
 CONFIG_TOOLCHAIN_MUSL_RISCV64=y
 CONFIG_FLASH_SIZE_SHRINK=y
 CONFIG_BOOT_IMAGE_SINGLE_DTB=y
-CONFIG_STORAGE_TYPE_emmc=y
+CONFIG_STORAGE_TYPE_sd=y
 CONFIG_SENSOR_GCORE_GC4653=y
 CONFIG_SENSOR_SMS_SC3335=y
 CONFIG_SENSOR_SMS_SC500AI=y

build/boards/sg200x/sg2000_duo_sd/u-boot/sg2000_duo_sd_defconfig

@@ -40,4 +40,4 @@ CONFIG_SPI=y
 CONFIG_LZ4=y
 CONFIG_LZMA=y
 # CONFIG_TOOLS_LIBCRYPTO is not set
-CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_NOWHERE=y

build/boards/sg200x/sg2000_wevb_sd/dts_arm/sg2000_wevb_sd.dts

@@ -0,0 +1,13 @@
+/dts-v1/;
+#include "soph_base_arm.dtsi"
+#include "soph_asic_bga.dtsi"
+#include "soph_asic_sd.dtsi"
+#include "soph_default_memmap.dtsi"
+
+/ {
+
+	sd:cv-sd@4310000 {
+		max-frequency = <10000000>;
+	};
+};
+

build/boards/sg200x/sg2000_wevb_sd/linux/sg2000_wevb_sd_defconfig

@@ -0,0 +1,284 @@
+CONFIG_KERNEL_XZ=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_LOG_BUF_SHIFT=15
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+# CONFIG_UID16 is not set
+# CONFIG_SYSFS_SYSCALL is not set
+# CONFIG_FHANDLE is not set
+# CONFIG_BASE_FULL is not set
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+# CONFIG_SLUB_DEBUG is not set
+CONFIG_ARM_LPAE=y
+CONFIG_SWP_EMULATE=y
+# CONFIG_VDSO is not set
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_ARM_PSCI=y
+CONFIG_THUMB2_KERNEL=y
+CONFIG_FORCE_MAX_ZONEORDER=10
+# CONFIG_ATAGS is not set
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_SUSPEND is not set
+CONFIG_ARCH_CVITEK=y
+CONFIG_ARCH_CV181X=y
+CONFIG_ARCH_CVITEK_CHIP="mars"
+CONFIG_ARCH_CV181X_ASIC=y
+CONFIG_POWER_RESET=y
+# CONFIG_STACKPROTECTOR is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_MQ_IOSCHED_DEADLINE is not set
+# CONFIG_MQ_IOSCHED_KYBER is not set
+# CONFIG_COREDUMP is not set
+CONFIG_CMA=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_CFG80211=m
+CONFIG_RFKILL=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+CONFIG_DMA_CMA=n
+CONFIG_CMA_SIZE_MBYTES=0
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_OF_PARTS is not set
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_MTD_NAND_CVSNFC=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_SPI_CVI_SPIF=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CORE is not set
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_AURORA is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CADENCE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_DWMAC_GENERIC is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_CVITEK_PHY=y
+# CONFIG_USB_NET_DRIVERS is not set
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATH is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+# CONFIG_WLAN_VENDOR_BROADCOM is not set
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_MARVELL is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+CONFIG_RTL8188FU=m
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+CONFIG_INPUT=y
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=5
+CONFIG_SERIAL_8250_RUNTIME_UARTS=5
+CONFIG_SERIAL_8250_DW=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_SMBUS=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+# CONFIG_PTP_1588_CLOCK is not set
+CONFIG_CVITEK_PINCTRL_CV1835=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_NETLINK=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_WATCHDOG=y
+CONFIG_MEDIA_SUPPORT=n
+CONFIG_VIDEO_CVITEK=m
+CONFIG_VIDEO_CVITEK_CIF=m
+CONFIG_VIDEO_CVITEK_SNS_I2C=m
+CONFIG_VIDEO_CVITEK_MIPI_TX=m
+CONFIG_FB=y
+CONFIG_FB_CVITEK=m
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_PROC_FS is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_HDA_PREALLOC_SIZE=n
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_CV182XA_CV182XAADC=y
+CONFIG_SND_SOC_CV182XA_CV182XADAC=y
+CONFIG_SND_CV1835_I2S=y
+CONFIG_SND_SOC_CV182XAADC=y
+CONFIG_SND_SOC_CV182XADAC=y
+# CONFIG_SND_SOC_CV182X_CV182XPDM is not set
+# CONFIG_SND_SOC_CV1835PDM is not set
+# CONFIG_SND_SOC_CV1835_CONCURRENT_I2S is not set
+CONFIG_SND_SOC_CV1835_USE_AUDIO_PLL=y
+CONFIG_CV1835_I2S_SUBSYS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_CVI=y
+CONFIG_DMADEVICES=n
+CONFIG_DW_DMAC_CVITEK=n
+# CONFIG_VIRTIO_MENU is not set
+CONFIG_STAGING=y
+CONFIG_ION=y
+CONFIG_ION_SYSTEM_HEAP=y
+CONFIG_ION_CARVEOUT_HEAP=y
+CONFIG_ION_CMA_HEAP=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_CV1835_SYSDMA_REMAP=n
+CONFIG_PWM=y
+CONFIG_ANDROID=y
+# CONFIG_TEE=y
+# CONFIG_OPTEE=y
+# CONFIG_MANDATORY_FILE_LOCKING is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_CONFIGFS_FS=m
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_FILE_DIRECT=y
+# CONFIG_SQUASHFS_ZLIB is not set
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_EMBEDDED=y
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=1
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V2=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+# CONFIG_CRYPTO_ECHAINIV is not set
+CONFIG_CRYPTO_SHA256=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_FTRACE is not set
+# CONFIG_RUNTIME_TESTING_MENU is not set
+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
+
+CONFIG_RTC_CLASS=y
+
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_USB=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_LIBCOMPOSITE=y
+CONFIG_USB_F_ACM=y
+CONFIG_USB_U_SERIAL=y
+CONFIG_USB_U_ETHER=y
+CONFIG_USB_U_AUDIO=y
+CONFIG_USB_F_SERIAL=y
+CONFIG_USB_F_ECM=y
+CONFIG_USB_F_EEM=y
+CONFIG_USB_F_RNDIS=y
+CONFIG_USB_F_MASS_STORAGE=y
+CONFIG_USB_F_UAC1=y
+CONFIG_USB_F_UVC=y
+CONFIG_USB_UAS=y
+CONFIG_USB_DWC2=m
+CONFIG_USB_DWC2_DUAL_ROLE=y
+CONFIG_USB_GADGET=y
+CONFIG_U_SERIAL_CONSOLE=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_UAC1=y
+CONFIG_USB_CONFIGFS_F_UVC=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_UEVENT=y
+CONFIG_USB_PHY=y
+CONFIG_USB_GPIO_VBUS=y

build/boards/sg200x/sg2000_wevb_sd/memmap.py

@@ -0,0 +1,85 @@
+SIZE_1M = 0x100000
+SIZE_1K = 1024
+
+
+# Only attributes in class MemoryMap are generated to .h
+class MemoryMap:
+    # No prefix "CVIMMAP_" for the items in _no_prefix[]
+    _no_prefix = [
+        "CONFIG_SYS_TEXT_BASE"  # u-boot's CONFIG_SYS_TEXT_BASE is used without CPP.
+    ]
+
+    DRAM_BASE = 0x80000000
+    DRAM_SIZE = 512 * SIZE_1M
+
+    # ==============
+    # C906L FreeRTOS
+    # ==============
+    FREERTOS_SIZE = 768 * SIZE_1K
+    # FreeRTOS is at the end of DRAM
+    FREERTOS_ADDR = DRAM_BASE + DRAM_SIZE - FREERTOS_SIZE
+    FSBL_C906L_START_ADDR = FREERTOS_ADDR
+
+    # ==============================
+    # OpenSBI | arm-trusted-firmware
+    # ==============================
+    # Monitor is at the begining of DRAM
+    MONITOR_ADDR = DRAM_BASE
+
+    ATF_SIZE = 512 * SIZE_1K
+    OPENSBI_SIZE = 512 * SIZE_1K
+    OPENSBI_FDT_ADDR = MONITOR_ADDR + OPENSBI_SIZE
+
+    # =========================
+    # memory@DRAM_BASE in .dts.
+    # =========================
+    # Ignore the area of FreeRTOS in u-boot and kernel
+    KERNEL_MEMORY_ADDR = DRAM_BASE
+    KERNEL_MEMORY_SIZE = DRAM_SIZE - FREERTOS_SIZE
+
+    # =================
+    # Multimedia buffer. Used by u-boot/kernel/FreeRTOS
+    # =================
+    ION_SIZE = 70 * SIZE_1M
+    H26X_BITSTREAM_SIZE = 2 * SIZE_1M
+    H26X_ENC_BUFF_SIZE = 0
+    ISP_MEM_BASE_SIZE = 20 * SIZE_1M
+    FREERTOS_RESERVED_ION_SIZE = H26X_BITSTREAM_SIZE + H26X_ENC_BUFF_SIZE + ISP_MEM_BASE_SIZE
+
+    # ION after FreeRTOS
+    ION_ADDR = FREERTOS_ADDR - ION_SIZE
+
+    # Buffers of the fast image are inside the ION buffer
+    H26X_BITSTREAM_ADDR = ION_ADDR
+    H26X_ENC_BUFF_ADDR = H26X_BITSTREAM_ADDR + H26X_BITSTREAM_SIZE
+    ISP_MEM_BASE_ADDR = H26X_ENC_BUFF_ADDR + H26X_ENC_BUFF_SIZE
+
+    assert ISP_MEM_BASE_ADDR + ISP_MEM_BASE_SIZE <= ION_ADDR + ION_SIZE
+
+    # Boot logo is after the ION buffer
+    # Framebuffer uses boot logo's reserved memory
+    BOOTLOGO_SIZE = 1800 * SIZE_1K
+    BOOTLOGO_ADDR = ION_ADDR - BOOTLOGO_SIZE
+    FRAMEBUFFER_SIZE = BOOTLOGO_SIZE
+    FRAMEBUFFER_ADDR = BOOTLOGO_ADDR
+
+    # ===================
+    # FSBL and u-boot-2021
+    # ===================
+    CVI_UPDATE_HEADER_SIZE = SIZE_1K
+    UIMAG_SIZE = 16 * SIZE_1M
+
+    # kernel image loading buffer
+    UIMAG_ADDR = DRAM_BASE + 24 * SIZE_1M
+    CVI_UPDATE_HEADER_ADDR = UIMAG_ADDR - CVI_UPDATE_HEADER_SIZE
+
+    # FSBL decompress buffer
+    FSBL_UNZIP_ADDR = UIMAG_ADDR
+    FSBL_UNZIP_SIZE = UIMAG_SIZE
+
+    assert UIMAG_ADDR + UIMAG_SIZE <= BOOTLOGO_ADDR
+
+    # u-boot's run address and entry point
+    CONFIG_SYS_TEXT_BASE = DRAM_BASE + 2 * SIZE_1M
+    # u-boot's init stack point is only used before board_init_f()
+    CONFIG_SYS_INIT_SP_ADDR = UIMAG_ADDR + UIMAG_SIZE

build/boards/sg200x/sg2000_wevb_sd/partition/partition_sd.xml

@@ -0,0 +1,5 @@
+<physical_partition type="sd">
+    <partition label="BOOT" size_in_kb="80960" readonly="false" file="boot.sd"/>
+    <partition label="ROOTFS" size_in_kb="204800" readonly="false" file="rootfs.sd" />
+    <partition label="DATA"  size_in_kb="512000" readonly="false" file="data.sd" mountpoint="/mnt/data" type="ext4" />
+</physical_partition>

build/boards/sg200x/sg2000_wevb_sd/sg2000_wevb_sd_defconfig

@@ -0,0 +1,30 @@
+CONFIG_CHIP_sg2000=y
+CONFIG_BOARD_wevb_sd=y
+CONFIG_DDR_CFG_ddr3_1866_x16=y
+CONFIG_ARCH="arm"
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_KERNEL_ENTRY_HACK=y
+CONFIG_KERNEL_ENTRY_HACK_ADDR="0x80108000"
+CONFIG_TOOLCHAIN_GLIBC_ARM=y
+CONFIG_FLASH_SIZE_SHRINK=y
+CONFIG_BOOT_IMAGE_SINGLE_DTB=y
+CONFIG_STORAGE_TYPE_sd=y
+CONFIG_SENSOR_GCORE_GC2053=y
+CONFIG_SENSOR_GCORE_GC2053_1L=y
+CONFIG_SENSOR_GCORE_GC2093=y
+CONFIG_SENSOR_GCORE_GC4653=y
+CONFIG_SENSOR_PIXELPLUS_PR2020=y
+CONFIG_SENSOR_SONY_IMX307=y
+CONFIG_SENSOR_SONY_IMX327=y
+CONFIG_UBOOT_2021_10=y
+CONFIG_KERNEL_SRC_5.10=y
+CONFIG_KERNEL_SRC="linux_5.10"
+CONFIG_KERNEL_LZMA=y
+CONFIG_SKIP_RAMDISK=y
+CONFIG_USE_4K_ERASE_SIZE_FOR_JFFS2=y
+CONFIG_SENSOR_TUNING_PARAM_cv181x_src_gcore_gc4653=y
+# CONFIG_ROOTFS_OVERLAYFS is not set
+CONFIG_TARGET_PACKAGE_DROPBEAR=y
+CONFIG_TARGET_PACKAGE_MTD-UTILS=y
+# CONFIG_TARGET_PACKAGE_RSYSLOG is not set
+# CONFIG_TARGET_PACKAGE_GATORD is not set

build/boards/sg200x/sg2000_wevb_sd/u-boot/sg2000_wevb_sd_defconfig

@@ -0,0 +1,49 @@
+CONFIG_ARM=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="cv181x_asic"
+CONFIG_IDENT_STRING=" cvitek_cv181x"
+CONFIG_ARMV8_SET_SMPEN=y
+CONFIG_TARGET_CVITEK_CV181X=y
+#CONFIG_CVITEK_SPI_FLASH=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_BOOTDELAY=1
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="soph# "
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNLZ4 is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_ITEST is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CVI_SD_UPDATE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_CVITEK=y
+CONFIG_MTD=y
+# CONFIG_PHY_SMSC is not set
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_CVITEK=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_LZ4=y
+CONFIG_LZMA=y
+# CONFIG_TOOLS_LIBCRYPTO is not set
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_ENV_IS_NOWHERE=y

build/boards/sg200x/sg2002_licheea53nano_sd/config.json

@@ -0,0 +1,8 @@
+{
+    "ddr_cfg_list": [
+        "ddr3_1866_x16",
+        "ddr3_2133_x16",
+        "ddr_auto_x16"
+    ],
+    "board_information": "CA53"
+}

build/boards/sg200x/sg2002_licheea53nano_sd/dts_arm/sg2002_licheea53nano_sd.dts

@@ -0,0 +1,185 @@
+/dts-v1/;
+#include "soph_base_arm.dtsi"
+#include "soph_asic_qfn.dtsi"
+#include "soph_asic_sd.dtsi"
+#include "soph_default_memmap.dtsi"
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/gpio.h>
+
+&i2c0 {
+        status = "disabled";
+        /delete-property/ scl-pinmux;
+        /delete-property/ sda-pinmux;
+        /delete-property/ scl-gpios;
+        /delete-property/ sda-gpios;
+};
+
+&i2c1 {
+        status = "disabled";
+        /delete-property/ scl-pinmux;
+        /delete-property/ sda-pinmux;
+        /delete-property/ scl-gpios;
+        /delete-property/ sda-gpios;
+};
+
+&sd {
+        min-frequency = <400000>; // 400Khz
+        //max-frequency = <50000000>; // 50Mhz
+        max-frequency = <25000000>; // 25Mhz
+        //max-frequency = <10000000>; // 10Mhz
+        //max-frequency = <5000000>; // 5Mhz
+};
+
+&cvi_vo {
+#ifndef __UBOOT__
+	/delete-property/ reset-gpio;
+	/delete-property/ pwm-gpio;
+#else
+	// for uboot
+        reset-gpio = <&porte 0 1>;
+        pwm-gpio = <&porte 2 1>;
+#endif
+        /delete-property/ power-ct-gpio;
+
+};
+
+&mipi_tx {
+#ifndef __UBOOT__
+	// for linux kernel
+        reset-gpio = <&porte 0 1>;
+        pwm-gpio = <&porte 2 1>;
+#else
+        /delete-property/ reset-gpio;
+        /delete-property/ pwm-gpio;
+#endif
+        /delete-property/ power-ct-gpio;
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&pwm0 {
+        status = "okay";
+};
+
+&pwm1 {
+      status = "okay";
+};
+
+&pwm2 {
+      status = "okay";
+};
+
+&i2c2 {
+        status = "disabled";
+        /delete-property/ scl-pinmux;
+        /delete-property/ sda-pinmux;
+        /delete-property/ scl-gpios;
+        /delete-property/ sda-gpios;
+};
+
+&i2c3 {
+        status = "disabled";
+        /delete-property/ scl-pinmux;
+        /delete-property/ sda-pinmux;
+        /delete-property/ scl-gpios;
+        /delete-property/ sda-gpios;
+};
+
+&i2c4 {
+        statuc = "okay";
+        gt9xx: gt9xx@14 {
+                compatible = "goodix,gt9xx";
+                reg = <0x14>;
+                goodix,irq-gpio = <&porte 3 0>;
+                goodix,rst-gpio = <&porte 4 0>;
+                status = "okay";
+        };
+	hytr: hynitron@5a {
+		compatible = "hynitron,hyn_ts";
+		reg = <0x5a>;
+		hynitron,irq-gpio = <&porte 3 0>;
+		hynitron,reset-gpio = <&porte 4 0>;
+		hynitron,max-touch-number = <5>;
+		hynitron,display-coords = <368 552>;
+                status = "okay";
+	};
+};
+
+&dac {
+        status = "okay";
+        /delete-property/ mute-gpio-r;
+};
+
+&fb_reserved {
+        status = "okay";
+};
+
+&cvi_fb {
+        status = "okay";
+};
+
+&mipi_rx {
+        snsr-reset = <&porte 1 GPIO_ACTIVE_LOW>;
+};
+
+/ {
+        model = "LicheeRv Nano";
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                key-user {
+                        label = "User Key";
+                        linux,code = <KEY_DISPLAYTOGGLE>;
+                        debounce-interval = <1>;
+                        gpios = <&porta 30 1>;
+                };
+        };
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-user {
+			gpios = <&porta 14 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "activity";
+		};
+	};
+
+	lcd0_backlight: pwm-backlight@0 {
+		compatible = "pwm-backlight";
+		pwms = <&pwm2 2 50000000>; // 20Khz
+		brightness-levels = <0 2 4 8 16 32 64 128 255>;
+		default-brightness-level = <4>;
+	};
+
+        wifisd:wifi-sd@4320000 {                                                    
+                compatible = "cvitek,cv181x-sdio";                                  
+                bus-width = <4>;                                                    
+                reg = <0x0 0x4320000 0x0 0x1000>;                                   
+                reg_names = "core_mem";                                             
+                src-frequency = <375000000>;                                        
+                min-frequency = <400000>; // 400Khz                                 
+                //max-frequency = <50000000>; // 50Mhz                              
+                //max-frequency = <45000000>; // 45Mhz                              
+                //max-frequency = <40000000>; // 40Mhz                              
+                //max-frequency = <35000000>; // 35Mhz                              
+                //max-frequency = <30000000>; // 30Mhz                              
+                max-frequency = <25000000>; // 25Mhz                                
+                //max-frequency = <20000000>; // 20Mhz                              
+                //max-frequency = <15000000>; // 15Mhz                              
+                //max-frequency = <10000000>; // 10Mhz                              
+                //max-frequency = <5000000>; // 5Mhz                                
+                64_addressing;                                                      
+                reset_tx_rx_phy;                                                    
+                non-removable;                                                      
+                pll_index = <0x7>;                                                  
+                pll_reg = <0x300207C>;                                              
+                no-mmc;                                                             
+                no-sd;                                                              
+                status = "okay";                                                    
+		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+        };
+};

build/boards/sg200x/sg2002_licheea53nano_sd/linux/sg2002_licheea53nano_sd_defconfig

@@ -0,0 +1,370 @@
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_LOG_BUF_SHIFT=15
+CONFIG_BLK_DEV_INITRD=n
+# CONFIG_UID16 is not set
+# CONFIG_SYSFS_SYSCALL is not set
+# CONFIG_FHANDLE is not set
+# CONFIG_BASE_FULL is not set
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+# CONFIG_SLUB_DEBUG is not set
+CONFIG_ARM_LPAE=y
+CONFIG_SWP_EMULATE=y
+# CONFIG_VDSO is not set
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_ARM_PSCI=y
+CONFIG_THUMB2_KERNEL=y
+CONFIG_FORCE_MAX_ZONEORDER=10
+# CONFIG_ATAGS is not set
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_SUSPEND is not set
+CONFIG_ARCH_CVITEK=y
+CONFIG_ARCH_CV181X=y
+CONFIG_ARCH_CVITEK_CHIP="mars"
+CONFIG_ARCH_CV181X_ASIC=y
+CONFIG_POWER_RESET=y
+# CONFIG_STACKPROTECTOR is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_MQ_IOSCHED_DEADLINE is not set
+# CONFIG_MQ_IOSCHED_KYBER is not set
+# CONFIG_COREDUMP is not set
+CONFIG_CMA=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_CFG80211=m
+CONFIG_RFKILL=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+CONFIG_DMA_CMA=n
+CONFIG_CMA_SIZE_MBYTES=0
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_OF_PARTS is not set
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_MTD_NAND_CVSNFC=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_SPI_CVI_SPIF=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CORE is not set
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_AURORA is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CADENCE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_DWMAC_GENERIC is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_CVITEK_PHY=y
+# CONFIG_USB_NET_DRIVERS is not set
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATH is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+# CONFIG_WLAN_VENDOR_BROADCOM is not set
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_MARVELL is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+# CONFIG_RTL8188FU is not set
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=5
+CONFIG_SERIAL_8250_RUNTIME_UARTS=5
+CONFIG_SERIAL_8250_DW=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_SMBUS=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+# CONFIG_PTP_1588_CLOCK is not set
+CONFIG_CVITEK_PINCTRL_CV1835=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_NETLINK=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_WATCHDOG=y
+CONFIG_MEDIA_SUPPORT=n
+CONFIG_VIDEO_CVITEK=m
+CONFIG_VIDEO_CVITEK_CIF=m
+CONFIG_VIDEO_CVITEK_SNS_I2C=m
+CONFIG_VIDEO_CVITEK_MIPI_TX=m
+CONFIG_FB=y
+CONFIG_FB_CVITEK=m
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_PROC_FS is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_HDA_PREALLOC_SIZE=n
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_CV182XA_CV182XAADC=y
+CONFIG_SND_SOC_CV182XA_CV182XADAC=y
+CONFIG_SND_CV1835_I2S=y
+CONFIG_SND_SOC_CV182XAADC=y
+CONFIG_SND_SOC_CV182XADAC=y
+# CONFIG_SND_SOC_CV182X_CV182XPDM is not set
+# CONFIG_SND_SOC_CV1835PDM is not set
+# CONFIG_SND_SOC_CV1835_CONCURRENT_I2S is not set
+CONFIG_SND_SOC_CV1835_USE_AUDIO_PLL=y
+CONFIG_CV1835_I2S_SUBSYS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_CVI=y
+CONFIG_DMADEVICES=n
+CONFIG_DW_DMAC_CVITEK=n
+# CONFIG_VIRTIO_MENU is not set
+CONFIG_STAGING=y
+CONFIG_ION=y
+CONFIG_ION_SYSTEM_HEAP=y
+CONFIG_ION_CARVEOUT_HEAP=y
+CONFIG_ION_CMA_HEAP=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_CV1835_SYSDMA_REMAP=n
+CONFIG_PWM=y
+CONFIG_ANDROID=y
+# CONFIG_TEE=y
+# CONFIG_OPTEE=y
+# CONFIG_MANDATORY_FILE_LOCKING is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_CONFIGFS_FS=m
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_FILE_DIRECT=y
+# CONFIG_SQUASHFS_ZLIB is not set
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_EMBEDDED=y
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=1
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V2=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+# CONFIG_CRYPTO_ECHAINIV is not set
+CONFIG_CRYPTO_SHA256=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_FTRACE is not set
+# CONFIG_RUNTIME_TESTING_MENU is not set
+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
+
+CONFIG_RTC_CLASS=y
+
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_USB=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_LIBCOMPOSITE=y
+CONFIG_USB_F_ACM=y
+CONFIG_USB_U_SERIAL=y
+CONFIG_USB_U_ETHER=y
+CONFIG_USB_U_AUDIO=y
+CONFIG_USB_F_SERIAL=y
+CONFIG_USB_F_ECM=y
+CONFIG_USB_F_EEM=y
+CONFIG_USB_F_RNDIS=y
+CONFIG_USB_F_MASS_STORAGE=y
+CONFIG_USB_F_UAC1=y
+CONFIG_USB_F_UVC=y
+CONFIG_USB_UAS=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC2_DUAL_ROLE=y
+CONFIG_USB_GADGET=y
+CONFIG_U_SERIAL_CONSOLE=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_UAC1=y
+CONFIG_USB_CONFIGFS_F_UVC=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_UEVENT=y
+CONFIG_USB_PHY=y
+CONFIG_USB_GPIO_VBUS=y
+
+# for licheervnano
+CONFIG_FB_SIMPLE=y
+CONFIG_IP_MULTICAST=y
+CONFIG_SND_PROC_FS=y
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BREDR=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HS=y
+CONFIG_BT_LE=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SWAP=y
+CONFIG_USB_LIBCOMPOSITE=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_F_ACM=y
+CONFIG_USB_F_EEM=y
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_IPV6=y
+# CONFIG_IPV6_SIT is not set
+CONFIG_PACKET_DIAG=y
+CONFIG_UNIX_DIAG=y
+CONFIG_NETLINK_DIAG=y
+CONFIG_AIC_WLAN_SUPPORT=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_HYNITRON_TS=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_MAGIC_SYSRQ_SERIAL is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CLASS_FLASH=y
+CONFIG_LEDS_USER=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_LEDS_TRIGGER_ACTIVITY=y
+CONFIG_LEDS_TRIGGER_NETDEV=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_V4L2_FLASH_LED_CLASS=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_AIC_WLAN_SUPPORT=y     
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y           
+CONFIG_INPUT_TOUCHSCREEN=y 
+CONFIG_TOUCHSCREEN_HYNITRON_TS=y
+CONFIG_USB_DWC2=y
+CONFIG_VT=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=m
+CONFIG_BACKLIGHT_PWM=m
+
+
+
+# these driver may broken codec driver
+# CONFIG_FUSE_FS is not set
+# CONFIG_CUSE is not set
+# CONFIG_OVERLAY_FS is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_MEMCG is not set
+# CONFIG_BLK_CGROUP is not set
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_FAIR_GROUP_SCHED is not set
+# CONFIG_CFS_BANDWIDTH is not set
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_CGROUP_PIDS is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CHECKPOINT_RESTORE is not set
+CONFIG_EPOLL=y
+CONFIG_IO_URING=y
+CONFIG_SIGNALFD=y

build/boards/sg200x/sg2002_licheea53nano_sd/memmap.py

@@ -0,0 +1,85 @@
+SIZE_1M = 0x100000
+SIZE_1K = 1024
+
+
+# Only attributes in class MemoryMap are generated to .h
+class MemoryMap:
+    # No prefix "CVIMMAP_" for the items in _no_prefix[]
+    _no_prefix = [
+        "CONFIG_SYS_TEXT_BASE"  # u-boot's CONFIG_SYS_TEXT_BASE is used without CPP.
+    ]
+
+    DRAM_BASE = 0x80000000
+    DRAM_SIZE = 256 * SIZE_1M
+
+    # ==============
+    # C906L FreeRTOS
+    # ==============
+    FREERTOS_SIZE = 768 * SIZE_1K
+    # FreeRTOS is at the end of DRAM
+    FREERTOS_ADDR = DRAM_BASE + DRAM_SIZE - FREERTOS_SIZE
+    FSBL_C906L_START_ADDR = FREERTOS_ADDR
+
+    # ==============================
+    # OpenSBI | arm-trusted-firmware
+    # ==============================
+    # Monitor is at the begining of DRAM
+    MONITOR_ADDR = DRAM_BASE
+
+    ATF_SIZE = 512 * SIZE_1K
+    OPENSBI_SIZE = 512 * SIZE_1K
+    OPENSBI_FDT_ADDR = MONITOR_ADDR + OPENSBI_SIZE
+
+    # =========================
+    # memory@DRAM_BASE in .dts.
+    # =========================
+    # Ignore the area of FreeRTOS in u-boot and kernel
+    KERNEL_MEMORY_ADDR = DRAM_BASE
+    KERNEL_MEMORY_SIZE = DRAM_SIZE - FREERTOS_SIZE
+
+    # =================
+    # Multimedia buffer. Used by u-boot/kernel/FreeRTOS
+    # =================
+    ION_SIZE = 70 * SIZE_1M
+    H26X_BITSTREAM_SIZE = 2 * SIZE_1M
+    H26X_ENC_BUFF_SIZE = 0
+    ISP_MEM_BASE_SIZE = 20 * SIZE_1M
+    FREERTOS_RESERVED_ION_SIZE = H26X_BITSTREAM_SIZE + H26X_ENC_BUFF_SIZE + ISP_MEM_BASE_SIZE
+
+    # ION after FreeRTOS
+    ION_ADDR = FREERTOS_ADDR - ION_SIZE
+
+    # Buffers of the fast image are inside the ION buffer
+    H26X_BITSTREAM_ADDR = ION_ADDR
+    H26X_ENC_BUFF_ADDR = H26X_BITSTREAM_ADDR + H26X_BITSTREAM_SIZE
+    ISP_MEM_BASE_ADDR = H26X_ENC_BUFF_ADDR + H26X_ENC_BUFF_SIZE
+
+    assert ISP_MEM_BASE_ADDR + ISP_MEM_BASE_SIZE <= ION_ADDR + ION_SIZE
+
+    # Boot logo is after the ION buffer
+    # Framebuffer uses boot logo's reserved memory
+    BOOTLOGO_SIZE = 8000 * SIZE_1K
+    BOOTLOGO_ADDR = ION_ADDR - BOOTLOGO_SIZE
+    FRAMEBUFFER_SIZE = BOOTLOGO_SIZE
+    FRAMEBUFFER_ADDR = BOOTLOGO_ADDR
+
+    # ===================
+    # FSBL and u-boot-2021
+    # ===================
+    CVI_UPDATE_HEADER_SIZE = SIZE_1K
+    UIMAG_SIZE = 16 * SIZE_1M
+
+    # kernel image loading buffer
+    UIMAG_ADDR = DRAM_BASE + 24 * SIZE_1M
+    CVI_UPDATE_HEADER_ADDR = UIMAG_ADDR - CVI_UPDATE_HEADER_SIZE
+
+    # FSBL decompress buffer
+    FSBL_UNZIP_ADDR = UIMAG_ADDR
+    FSBL_UNZIP_SIZE = UIMAG_SIZE
+
+    assert UIMAG_ADDR + UIMAG_SIZE <= BOOTLOGO_ADDR
+
+    # u-boot's run address and entry point
+    CONFIG_SYS_TEXT_BASE = DRAM_BASE + 2 * SIZE_1M
+    # u-boot's init stack point is only used before board_init_f()
+    CONFIG_SYS_INIT_SP_ADDR = UIMAG_ADDR + UIMAG_SIZE

build/boards/sg200x/sg2002_licheea53nano_sd/partition/partition_sd.xml

@@ -0,0 +1,4 @@
+<physical_partition type="sd">
+    <partition label="BOOT" size_in_kb="80960" readonly="false" file="boot.sd"/>
+    <partition label="ROOTFS" size_in_kb="1048576" readonly="false" file="rootfs.sd" />
+</physical_partition>

build/boards/sg200x/sg2002_licheea53nano_sd/sg2002_licheea53nano_sd_defconfig

@@ -0,0 +1,23 @@
+CONFIG_CHIP_sg2002=y
+CONFIG_BOARD_licheea53nano_sd=y
+CONFIG_DDR_CFG_ddr3_1866_x16=y
+CONFIG_ARCH="arm"
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_KERNEL_ENTRY_HACK=y
+CONFIG_KERNEL_ENTRY_HACK_ADDR="0x80108000"
+CONFIG_TOOLCHAIN_GLIBC_ARM=y
+# CONFIG_FLASH_SIZE_SHRINK is not set
+CONFIG_CP_EXT_WIRELESS=y
+CONFIG_BOOT_IMAGE_SINGLE_DTB=y
+CONFIG_STORAGE_TYPE_sd=y
+CONFIG_SENSOR_GCORE_GC4653=y
+CONFIG_UBOOT_2021_10=y
+CONFIG_KERNEL_SRC_5.10=y
+CONFIG_KERNEL_SRC="linux_5.10"
+CONFIG_KERNEL_LZMA=y
+CONFIG_SKIP_RAMDISK=y
+CONFIG_SENSOR_TUNING_PARAM_cv181x_src_gcore_gc4653=y
+# CONFIG_ROOTFS_OVERLAYFS is not set
+# CONFIG_TARGET_PACKAGE_RSYSLOG is not set
+# CONFIG_TARGET_PACKAGE_GATORD is not set
+CONFIG_ENABLE_FREERTOS=y

build/boards/sg200x/sg2002_licheea53nano_sd/u-boot/cvi_board_init.c

@@ -0,0 +1,137 @@
+__attribute__((optimize("O0")))
+// 1.26ms
+void suck_loop(uint64_t loop) {
+        loop = loop * 50 * 100;
+        uint64_t a;
+        while (loop > 0) {
+                a = loop / (uint64_t)99;
+                a = loop / (uint64_t)77;
+                a = loop / (uint64_t)55;
+                a = loop / (uint64_t)33;
+                a = loop / (uint64_t)11;
+                a = loop / (uint64_t)999;
+                a = loop / (uint64_t)777;
+                a = loop / (uint64_t)555;
+                a = loop / (uint64_t)333;
+                a = loop / (uint64_t)111;
+                a = loop / (uint64_t)9999;
+                a = loop / (uint64_t)7777;
+                a = loop / (uint64_t)5555;
+                a = loop / (uint64_t)3333;
+                a = loop / (uint64_t)1111;
+                a = loop / (uint64_t)99999;
+                a = loop / (uint64_t)77777;
+                a = loop / (uint64_t)55555;
+                a = loop / (uint64_t)33333;
+                a = loop / (uint64_t)11111;
+                loop--;
+        }
+}
+
+static inline void user_led_on(void) {
+	uint32_t val;
+
+        val = mmio_read_32(0x03020000);
+        val |= (1 << 14);
+        mmio_write_32(0x03020000, val);
+}
+
+static inline void user_led_off(void) {
+	uint32_t val;
+
+        val = mmio_read_32(0x03020000);
+        val &= ~(1 << 14);
+        mmio_write_32(0x03020000, val);
+}
+
+static inline void user_led_toggle(void) {
+	uint32_t val;
+
+        val = mmio_read_32(0x03020000);
+        val ^= (1 << 14);
+        mmio_write_32(0x03020000, val);
+}
+
+int cvi_board_init(void)
+{
+        uint32_t val;
+
+	// user led
+	mmio_write_32(0x03001038, 0x3); // GPIOA 14 GPIO_MODE
+	val = mmio_read_32(0x03020004); // GPIOA DIR
+        val |= (1 << 14); // output
+        mmio_write_32(0x03020004, val);
+	user_led_toggle();
+
+        // wifi power reset
+        mmio_write_32(0x0300104C, 0x3); // GPIOA 26
+        val = mmio_read_32(0x03020004); // GPIOA DIR
+        val |= (1 << 26); // output
+        mmio_write_32(0x03020004, val);
+
+        val = mmio_read_32(0x03020000); // signal level
+        val &= ~(1 << 26); // set level to low
+        mmio_write_32(0x03020000, val);
+
+        suck_loop(50);
+	user_led_toggle();
+
+        val = mmio_read_32(0x03020000); // signal level
+        val |= (1 << 26); // set level to high
+        mmio_write_32(0x03020000, val);
+
+        // wifi sdio pinmux
+        mmio_write_32(0x030010D0, 0x0); // D3
+        mmio_write_32(0x030010D4, 0x0); // D2
+        mmio_write_32(0x030010D8, 0x0); // D1
+        mmio_write_32(0x030010DC, 0x0); // D0
+        mmio_write_32(0x030010E0, 0x0); // CMD
+        mmio_write_32(0x030010E4, 0x0); // CLK
+
+        // uart bluetooth
+        mmio_write_32(0x03001070, 0x1); // GPIOA 28 UART1 TX
+        mmio_write_32(0x03001074, 0x1); // GPIOA 29 UART1 RX
+        mmio_write_32(0x03001068, 0x4); // GPIOA 18 UART1 CTS
+        mmio_write_32(0x03001064, 0x4); // GPIOA 19 UART1 RTS
+
+        // PWM
+        //mmio_write_32(0x03001068, 0x2); // GPIOA 18 PWM 6
+
+        // lcd reset
+        mmio_write_32(0x030010A4, 0x0); // PWRGPIO 0 GPIO_MODE
+
+	user_led_toggle();
+        // lcd backlight
+        //mmio_write_32(0x030010EC, 0x0); // GPIOB 0 PWM0_BUCK
+	// for licheervnano alpha
+	val = mmio_read_32(0x03021000); // signal level
+        val |= (1 << 0); // set level to high
+        mmio_write_32(0x03021000, val);
+        val = mmio_read_32(0x03021004); // GPIOB DIR
+        val |= (1 << 0); // output
+        mmio_write_32(0x03021004, val);
+        mmio_write_32(0x030010EC, 0x3); // GPIOB 0 GPIO_MODE
+
+	// for licheervnano beta
+	//mmio_write_32(0x030010ac, 0x4); // PWRGPIO 2 PWM 10
+	mmio_write_32(0x030010ac, 0x0); // PWRGPIO 2 GPIO_MODE
+
+        // camera function
+        //mmio_write_32(0x0300116C, 0x5); // RX4N CAM_MCLK0 for alpha
+        mmio_write_32(0x0300118C, 0x5); // RX0N CAM_MCLK1 for beta
+
+        // camera/tp i2c
+        mmio_write_32(0x03001090, 0x5); // PWR_GPIO6 IIC4_SCL
+        mmio_write_32(0x03001098, 0x5); // PWR_GPIO8 IIC4_SDA
+
+        // tp function
+        mmio_write_32(0x03001084, 0x3); // PWR_SEQ1 PWR_GPIO[3]
+        mmio_write_32(0x03001088, 0x3); // PWR_SEQ2 PWR_GPIO[4]
+        mmio_write_32(0x05027078, 0x11);// Unlock PWR_GPIO[3]
+        mmio_write_32(0x0502707c, 0x11);// Unlock PWR_GPIO[4]
+
+        // wait hardware bootup
+        suck_loop(50);
+	user_led_off();
+        return 0;
+}

build/boards/sg200x/sg2002_licheea53nano_sd/u-boot/cvitek.h

@@ -0,0 +1,13 @@
+/*
+ *VO control GPIOs
+ */
+#define VO_GPIO_RESET_PORT		portb
+#define VO_GPIO_RESET_INDEX		5
+#define VO_GPIO_RESET_ACTIVE	GPIO_ACTIVE_LOW
+#define VO_GPIO_PWM_PORT		portb
+#define VO_GPIO_PWM_INDEX		4
+#define VO_GPIO_PWM_ACTIVE		GPIO_ACTIVE_HIGH
+#define VO_GPIO_POWER_CT_PORT	portb
+#define VO_GPIO_POWER_CT_INDEX	3
+#define VO_GPIO_POWER_CT_ACTIVE	GPIO_ACTIVE_HIGH
+

build/boards/sg200x/sg2002_licheea53nano_sd/u-boot/sg2002_licheea53nano_sd_defconfig

@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="soph_asic"
+CONFIG_IDENT_STRING=" soph"
+CONFIG_ARMV8_SET_SMPEN=y
+CONFIG_TARGET_CVITEK_CV181X=y
+#CONFIG_CVITEK_SPI_FLASH=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_BOOTDELAY=0
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="soph# "
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNLZ4 is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_ITEST is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CVI_SD_UPDATE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_CVITEK=y
+CONFIG_MTD=y
+# CONFIG_PHY_SMSC is not set
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_CVITEK=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_LZ4=y
+CONFIG_LZMA=y
+# CONFIG_TOOLS_LIBCRYPTO is not set
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_ENV_IS_NOWHERE=y
+
+# for licheervnano
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_BUF_ADDR=0x81800000
+CONFIG_FASTBOOT_BUF_SIZE=0x1000000
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_DISPLAY=y
+CONFIG_DM_VIDEO=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_CMD_VIDCONSOLE=y
+CONFIG_VIDEO_BPP16=y
+CONFIG_VIDEO_BPP32=y
+CONFIG_VIDEO_CVITEK=y
+CONFIG_DISPLAY_CVITEK_MIPI=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_BOOTLOGO=y
+CONFIG_CMD_CVI_VO=y
+CONFIG_CMD_GPIO=y

build/boards/sg200x/sg2002_licheervnano_sd/dts_riscv/sg2002_licheervnano_sd.dts

@@ -8,7 +8,7 @@
 #include <dt-bindings/gpio/gpio.h>
 
 &i2c0 {
-        status = "disabled";
+        status = "okay";
         /delete-property/ scl-pinmux;
         /delete-property/ sda-pinmux;
         /delete-property/ scl-gpios;
@@ -16,7 +16,7 @@
 };
 
 &i2c1 {
-        status = "disabled";
+        status = "okay";
         /delete-property/ scl-pinmux;
         /delete-property/ sda-pinmux;
         /delete-property/ scl-gpios;
@@ -34,31 +34,52 @@
 &cvi_vo {
 #ifndef __UBOOT__
 	/delete-property/ reset-gpio;
+	/delete-property/ pwm-gpio;
 #else
 	// for uboot
         reset-gpio = <&porte 0 1>;
+        pwm-gpio = <&porte 2 1>;
 #endif
-        /delete-property/ pwm-gpio;
         /delete-property/ power-ct-gpio;
 
 };
 
 &mipi_tx {
-        /delete-property/ pwm-gpio;
 #ifndef __UBOOT__
 	// for linux kernel
         reset-gpio = <&porte 0 1>;
+        pwm-gpio = <&porte 2 1>;
 #else
         /delete-property/ reset-gpio;
+        /delete-property/ pwm-gpio;
 #endif
         /delete-property/ power-ct-gpio;
         status = "okay";
 };
 
+&uart0 {
+	clocks = <&clk CV181X_CLK_UART0>;
+	/delete-property/ clock-frequency;
+};
+
 &uart1 {
+        clocks = <&clk CV181X_CLK_UART1>;
+        /delete-property/ clock-frequency;
         status = "okay";
 };
 
+&uart2 {
+        clocks = <&clk CV181X_CLK_UART2>;
+        /delete-property/ clock-frequency;
+        status = "okay";
+};
+
+&uart3 {
+        clocks = <&clk CV181X_CLK_UART3>;
+        /delete-property/ clock-frequency;
+	status = "okay";
+};
+
 &pwm0 {
         status = "okay";
 };
@@ -80,7 +101,7 @@
 };
 
 &i2c3 {
-        status = "disabled";
+        status = "okay";
         /delete-property/ scl-pinmux;
         /delete-property/ sda-pinmux;
         /delete-property/ scl-gpios;
@@ -88,7 +109,7 @@
 };
 
 &i2c4 {
-        statuc = "okay";
+        status = "okay";
         gt9xx: gt9xx@14 {
                 compatible = "goodix,gt9xx";
                 reg = <0x14>;
@@ -96,17 +117,57 @@
                 goodix,rst-gpio = <&porte 4 0>;
                 status = "okay";
         };
-	hytr: hynitron@5a {
-		compatible = "hynitron,hyn_ts";
-		reg = <0x5a>;
-		hynitron,irq-gpio = <&porte 3 0>;
-		hynitron,reset-gpio = <&porte 4 0>;
-		hynitron,max-touch-number = <5>;
-		hynitron,display-coords = <368 552>;
+        hynitron: hynitron@5a {
+                compatible = "hynitron,hyn_ts", "hyn,7xx";
+                reg = <0x5a>;
+                irq-gpio = <&porte 3 0>;
+                hynitron,irq-gpio = <&porte 3 0>;
+                reset-gpio = <&porte 4 0>;
+                hynitron,reset-gpio = <&porte 4 0>;
+                max-touch-number = <5>;
+                hynitron,max-touch-number = <5>;
+                display-coords = <0 0 480 640>;
+                hynitron,display-coords = <368 552>;
+                pos-swap = <0>;
+                posx-reverse = <1>;
+                posy-reverse = <1>;
                 status = "okay";
+        };
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+
+        // /delete-node/ spidev@0;
+        st7789: st7789@0{
+		compatible = "sitronix,st7789";
+		reg = <0>;
+		status = "disabled";
+		spi-max-frequency = <80000000>;
+		spi-cpol;
+		spi-cpha;
+		rotate = <0>;
+		fps = <60>;
+		rgb;
+		buswidth = <8>;
+		dc = <&porte 20 GPIO_ACTIVE_HIGH>;
+		reset = <&porta 14 GPIO_ACTIVE_LOW>;
+		debug = <0>;
 	};
 };
 
+&spi3 {
+	status = "okay";
+};
+
 &dac {
         status = "okay";
         /delete-property/ mute-gpio-r;
@@ -127,6 +188,29 @@
 / {
         model = "LicheeRv Nano";
 
+	spi4: spi4@gpio {
+		compatible = "spi-gpio";
+		sck-gpio = <&porta 22 0>;
+		miso-gpio = <&porta 23 0>;
+		mosi-gpio = <&porta 25 0>;
+		cs-gpio = <&porta 24 GPIO_ACTIVE_LOW>;
+		num-chipselects = <1>;
+		status = "okay";
+
+		spidev@0 {
+			compatible = "spidev";
+			reg = <0>;
+		};
+	};
+
+	i2c5: i2c5@gpio {
+		compatible = "i2c-gpio";
+                scl-gpios = <&porta 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                sda-gpios = <&porta 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                i2c-gpio,delay-us = <5>;
+                status = "okay";
+	};
+
         gpio-keys {
                 compatible = "gpio-keys";
                 key-user {
@@ -146,6 +230,17 @@
 		};
 	};
 
+	// buggy pwm driver, not working, please use userspace pwm api
+	/*
+	lcd0_backlight: pwm-backlight@0 {
+		compatible = "pwm-backlight";
+		pwm-names = "backlight";
+		pwms = <&pwm2 2 50000000>; // 20Khz
+		brightness-levels = <0 2 4 8 16 32 64 128 255>;
+		default-brightness-level = <4>;
+	};
+	*/
+
         wifisd:wifi-sd@4320000 {
                 compatible = "cvitek,cv181x-sdio";
                 bus-width = <4>;

build/boards/sg200x/sg2002_licheervnano_sd/linux/sg2002_licheervnano_sd_defconfig

@@ -8,7 +8,7 @@ CONFIG_PREEMPT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=15
-CONFIG_BLK_DEV_INITRD=n
+CONFIG_BLK_DEV_INITRD=y
 # CONFIG_SYSFS_SYSCALL is not set
 # CONFIG_FHANDLE is not set
 # CONFIG_BASE_FULL is not set
@@ -107,14 +107,8 @@ CONFIG_CVITEK_PHY=y
 # CONFIG_WLAN_VENDOR_TI is not set
 # CONFIG_WLAN_VENDOR_ZYDAS is not set
 CONFIG_INPUT=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 CONFIG_INPUT_EVDEV=y
 # CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=5
@@ -123,9 +117,13 @@ CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
 CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
+CONFIG_I2C_SLAVE=y
+CONFIG_I2C_SLAVE_EEPROM=y
+CONFIG_I2C_DESIGNWARE_SLAVE=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MUX=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_GPIO=m
 # CONFIG_PTP_1588_CLOCK is not set
 CONFIG_PINCTRL=y
 CONFIG_CVITEK_PINCTRL_CV1835=y
@@ -359,6 +357,8 @@ CONFIG_VIDEO_CVITEK_MIPI_TX=m
 # end of Digital TV options
 
 CONFIG_FB=y
+# CONFIG_FB_TFT is not set
+# CONFIG_FB_TFT_ST7789 is not set
 CONFIG_FB_CVITEK=m
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -450,7 +450,17 @@ CONFIG_RCU_TRACE=n
 # CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_FTRACE is not set
 # CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_USB_ROLE_SWITCH=y
+
+CONFIG_RTC_CLASS=y
+
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_USB=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=y
+CONFIG_USB_STORAGE=y
 CONFIG_USB_LIBCOMPOSITE=y
 CONFIG_USB_F_ACM=y
 CONFIG_USB_U_SERIAL=y
@@ -463,13 +473,14 @@ CONFIG_USB_F_RNDIS=y
 CONFIG_USB_F_MASS_STORAGE=y
 CONFIG_USB_F_FS=y
 CONFIG_USB_F_UAC1=y
+CONFIG_USB_ROLE_SWITCH=y
 # buggy driver, need fix
 # CONFIG_USB_F_UVC is not set
 CONFIG_USB_CONFIGFS=y
 CONFIG_USB_CONFIGFS_SERIAL=y
 CONFIG_USB_CONFIGFS_ACM=y
 # CONFIG_USB_CONFIGFS_OBEX is not set
-# CONFIG_USB_CONFIGFS_NCM is not set
+CONFIG_USB_CONFIGFS_NCM=y
 CONFIG_USB_CONFIGFS_ECM=y
 # CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
 CONFIG_USB_CONFIGFS_RNDIS=y
@@ -482,11 +493,11 @@ CONFIG_USB_CONFIGFS_F_UAC1=y
 # CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
 # CONFIG_USB_CONFIGFS_F_UAC2 is not set
 # CONFIG_USB_CONFIGFS_F_MIDI is not set
-# CONFIG_USB_CONFIGFS_F_HID is not set
+CONFIG_USB_CONFIGFS_F_HID=y
 CONFIG_USB_CONFIGFS_F_UVC=y
 CONFIG_BUG=n
 CONFIG_ADVISE_SYSCALLS=n
-CONFIG_TIMERFD=n
+CONFIG_TIMERFD=y
 
 # for licheervnano
 CONFIG_FB_SIMPLE=y
@@ -502,6 +513,9 @@ CONFIG_BT_HS=y
 CONFIG_BT_LE=y
 CONFIG_BT_HCIUART=y
 CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIUART_RTL=y
 CONFIG_SERIAL_DEV_BUS=y
 CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
 CONFIG_SWAP=y
@@ -522,6 +536,8 @@ CONFIG_KEYBOARD_GPIO=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_HYNITRON_TS=y
 CONFIG_MAGIC_SYSRQ=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
 # CONFIG_MAGIC_SYSRQ_SERIAL is not set
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
@@ -539,17 +555,27 @@ CONFIG_V4L2_FLASH_LED_CLASS=y
 CONFIG_MEDIA_USB_SUPPORT=y
 CONFIG_USB_VIDEO_CLASS=y
 CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_VT=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=m
+CONFIG_BACKLIGHT_PWM=m
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_DESIGNWARE=y
+CONFIG_SPI_DW_MMIO=y
+CONFIG_SPI_GPIO=m
+CONFIG_SPI_SPIDEV=y
 
 # these driver may broken codec driver
 # CONFIG_FUSE_FS is not set
 # CONFIG_CUSE is not set
 # CONFIG_OVERLAY_FS is not set
-# CONFIG_NAMESPACES is not set
+CONFIG_NAMESPACES=y
 # CONFIG_UTS_NS is not set
 # CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
+CONFIG_USER_NS=y
 # CONFIG_PID_NS is not set
-# CONFIG_NET_NS is not set
+CONFIG_NET_NS=y
 # CONFIG_CGROUPS is not set
 # CONFIG_MEMCG is not set
 # CONFIG_BLK_CGROUP is not set
@@ -563,3 +589,422 @@ CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
 CONFIG_EPOLL=y
 CONFIG_IO_URING=y
 CONFIG_SIGNALFD=y
+CONFIG_EXFAT_FS=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=y
+CONFIG_UNIX=y
+CONFIG_UNIX_SCM=y
+CONFIG_UNIX_DIAG=y
+# CONFIG_TLS is not set
+# CONFIG_XFRM_USER is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_ROUTE_CLASSID=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+CONFIG_NET_IPGRE=y
+# CONFIG_NET_IPGRE_DEMUX is not set
+CONFIG_IP_MULTIPLE_TABLES=y
+# CONFIG_IP_MROUTE is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_NET_IPVTI is not set
+# CONFIG_NET_FOU is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_BBR=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_IPV6_ILA is not set
+# CONFIG_IPV6_VTI is not set
+# CONFIG_IPV6_SIT is not set
+CONFIG_IPV6_TUNNEL=y
+CONFIG_IPV6_GRE=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_IPV6_SEG6_LWTUNNEL is not set
+# CONFIG_IPV6_SEG6_HMAC is not set
+# CONFIG_IPV6_RPL_LWTUNNEL is not set
+# CONFIG_MPTCP is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_INGRESS=y
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_FAMILY_ARP=y
+CONFIG_NETFILTER_NETLINK_ACCT=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NETFILTER_NETLINK_OSF=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_LOG_COMMON=y
+CONFIG_NF_LOG_NETDEV=y
+CONFIG_NETFILTER_CONNCOUNT=y
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_ZONES=y
+CONFIG_NF_CONNTRACK_PROCFS=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+CONFIG_NF_CONNTRACK_TIMESTAMP=y
+CONFIG_NF_CONNTRACK_LABELS=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_BROADCAST=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_SNMP=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NF_CT_NETLINK_TIMEOUT=y
+CONFIG_NF_CT_NETLINK_HELPER=y
+CONFIG_NETFILTER_NETLINK_GLUE_CT=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_REDIRECT=y
+CONFIG_NF_NAT_MASQUERADE=y
+CONFIG_NETFILTER_SYNPROXY=y
+CONFIG_NF_TABLES=y
+CONFIG_NF_TABLES_INET=y
+CONFIG_NF_TABLES_NETDEV=y
+CONFIG_NFT_NUMGEN=y
+CONFIG_NFT_CT=y
+# CONFIG_NFT_FLOW_OFFLOAD is not set
+CONFIG_NFT_COUNTER=y
+CONFIG_NFT_CONNLIMIT=y
+CONFIG_NFT_LOG=y
+CONFIG_NFT_LIMIT=y
+CONFIG_NFT_MASQ=y
+CONFIG_NFT_REDIR=y
+CONFIG_NFT_NAT=y
+CONFIG_NFT_TUNNEL=y
+CONFIG_NFT_OBJREF=y
+CONFIG_NFT_QUEUE=y
+CONFIG_NFT_QUOTA=y
+CONFIG_NFT_REJECT=y
+CONFIG_NFT_REJECT_INET=y
+CONFIG_NFT_COMPAT=y
+CONFIG_NFT_HASH=y
+CONFIG_NFT_FIB=y
+# CONFIG_NFT_FIB_INET is not set
+CONFIG_NFT_SOCKET=y
+CONFIG_NFT_OSF=y
+CONFIG_NFT_TPROXY=y
+CONFIG_NFT_SYNPROXY=y
+CONFIG_NF_DUP_NETDEV=y
+CONFIG_NFT_DUP_NETDEV=y
+CONFIG_NFT_FWD_NETDEV=y
+# CONFIG_NFT_FIB_NETDEV is not set
+CONFIG_NF_FLOW_TABLE_INET=y
+CONFIG_NF_FLOW_TABLE=y
+CONFIG_NETFILTER_XTABLES=y
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=y
+CONFIG_NETFILTER_XT_CONNMARK=y
+CONFIG_NETFILTER_XT_SET=y
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+# CONFIG_NETFILTER_XT_TARGET_CT is not set
+# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
+CONFIG_NETFILTER_XT_TARGET_HL=y
+CONFIG_NETFILTER_XT_TARGET_HMARK=y
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_LED=y
+CONFIG_NETFILTER_XT_TARGET_LOG=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_NAT=y
+CONFIG_NETFILTER_XT_TARGET_NETMAP=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_REDIRECT=y
+CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y
+CONFIG_NETFILTER_XT_TARGET_TEE=y
+# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set
+# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
+CONFIG_NETFILTER_XT_MATCH_BPF=y
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_CPU=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ECN=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_HL=y
+CONFIG_NETFILTER_XT_MATCH_IPCOMP=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_IPVS=y
+CONFIG_NETFILTER_XT_MATCH_L2TP=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_NFACCT=y
+CONFIG_NETFILTER_XT_MATCH_OSF=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_RECENT=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_SOCKET=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+# end of Core Netfilter Configuration
+
+CONFIG_IP_SET=y
+CONFIG_IP_SET_MAX=256
+# CONFIG_IP_SET_BITMAP_IP is not set
+# CONFIG_IP_SET_BITMAP_IPMAC is not set
+# CONFIG_IP_SET_BITMAP_PORT is not set
+# CONFIG_IP_SET_HASH_IP is not set
+# CONFIG_IP_SET_HASH_IPMARK is not set
+# CONFIG_IP_SET_HASH_IPPORT is not set
+# CONFIG_IP_SET_HASH_IPPORTIP is not set
+# CONFIG_IP_SET_HASH_IPPORTNET is not set
+# CONFIG_IP_SET_HASH_IPMAC is not set
+# CONFIG_IP_SET_HASH_MAC is not set
+# CONFIG_IP_SET_HASH_NETPORTNET is not set
+# CONFIG_IP_SET_HASH_NET is not set
+# CONFIG_IP_SET_HASH_NETNET is not set
+# CONFIG_IP_SET_HASH_NETPORT is not set
+# CONFIG_IP_SET_HASH_NETIFACE is not set
+# CONFIG_IP_SET_LIST_SET is not set
+CONFIG_IP_VS=y
+# CONFIG_IP_VS_IPV6 is not set
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+# CONFIG_IP_VS_PROTO_TCP is not set
+# CONFIG_IP_VS_PROTO_UDP is not set
+# CONFIG_IP_VS_PROTO_ESP is not set
+# CONFIG_IP_VS_PROTO_AH is not set
+# CONFIG_IP_VS_PROTO_SCTP is not set
+
+#
+# IPVS scheduler
+#
+# CONFIG_IP_VS_RR is not set
+# CONFIG_IP_VS_WRR is not set
+# CONFIG_IP_VS_LC is not set
+# CONFIG_IP_VS_WLC is not set
+# CONFIG_IP_VS_FO is not set
+# CONFIG_IP_VS_OVF is not set
+# CONFIG_IP_VS_LBLC is not set
+# CONFIG_IP_VS_LBLCR is not set
+# CONFIG_IP_VS_DH is not set
+# CONFIG_IP_VS_SH is not set
+# CONFIG_IP_VS_MH is not set
+# CONFIG_IP_VS_SED is not set
+# CONFIG_IP_VS_NQ is not set
+
+#
+# IPVS SH scheduler
+#
+CONFIG_IP_VS_SH_TAB_BITS=8
+
+#
+# IPVS MH scheduler
+#
+CONFIG_IP_VS_MH_TAB_INDEX=12
+
+#
+# IPVS application helper
+#
+# CONFIG_IP_VS_NFCT is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=y
+CONFIG_NF_SOCKET_IPV4=y
+CONFIG_NF_TPROXY_IPV4=y
+CONFIG_NF_TABLES_IPV4=y
+CONFIG_NFT_REJECT_IPV4=y
+CONFIG_NFT_DUP_IPV4=y
+CONFIG_NFT_FIB_IPV4=y
+CONFIG_NF_TABLES_ARP=y
+CONFIG_NF_FLOW_TABLE_IPV4=y
+CONFIG_NF_DUP_IPV4=y
+CONFIG_NF_LOG_ARP=y
+CONFIG_NF_LOG_IPV4=y
+CONFIG_NF_REJECT_IPV4=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+# CONFIG_IP_NF_MATCH_RPFILTER is not set
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_SYNPROXY=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+# end of IP: Netfilter Configuration
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_SOCKET_IPV6=y
+CONFIG_NF_TPROXY_IPV6=y
+CONFIG_NF_TABLES_IPV6=y
+CONFIG_NFT_REJECT_IPV6=y
+CONFIG_NFT_DUP_IPV6=y
+CONFIG_NFT_FIB_IPV6=y
+CONFIG_NF_FLOW_TABLE_IPV6=y
+CONFIG_NF_DUP_IPV6=y
+CONFIG_NF_REJECT_IPV6=y
+CONFIG_NF_LOG_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_AH=y
+CONFIG_IP6_NF_MATCH_EUI64=y
+CONFIG_IP6_NF_MATCH_FRAG=y
+CONFIG_IP6_NF_MATCH_OPTS=y
+CONFIG_IP6_NF_MATCH_HL=y
+CONFIG_IP6_NF_MATCH_IPV6HEADER=y
+CONFIG_IP6_NF_MATCH_MH=y
+# CONFIG_IP6_NF_MATCH_RPFILTER is not set
+CONFIG_IP6_NF_MATCH_RT=y
+CONFIG_IP6_NF_MATCH_SRH=y
+# CONFIG_IP6_NF_TARGET_HL is not set
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_TARGET_SYNPROXY=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_IP6_NF_NAT=y
+CONFIG_IP6_NF_TARGET_MASQUERADE=y
+CONFIG_IP6_NF_TARGET_NPT=y
+# end of IPv6: Netfilter Configuration
+
+CONFIG_NF_DEFRAG_IPV6=y
+CONFIG_NF_CONNTRACK_BRIDGE=y
+# CONFIG_BPFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+CONFIG_HAVE_NET_DSA=y
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+# CONFIG_6LOWPAN is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+# CONFIG_DNS_RESOLVER is not set
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_VSOCKETS is not set
+CONFIG_NETLINK_DIAG=y
+# CONFIG_MPLS is not set
+# CONFIG_NET_NSH is not set
+# CONFIG_HSR is not set
+# CONFIG_NET_SWITCHDEV is not set
+# CONFIG_NET_L3_MASTER_DEV is not set
+# CONFIG_QRTR is not set
+# CONFIG_NET_NCSI is not set
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+# CONFIG_BPF_JIT is not set
+
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_NET_CORE=y
+CONFIG_WIREGUARD=y
+CONFIG_TUN=y
+
+CONFIG_NET_IP_TUNNEL=y
+CONFIG_NET_UDP_TUNNEL=y
+CONFIG_VXLAN=y
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_OPTION=y
+CONFIG_USB_ACM=y
+
+CONFIG_VETH=y

build/boards/sg200x/sg2002_licheervnano_sd/memmap.py

@@ -40,7 +40,7 @@ class MemoryMap:
     # =================
     # Multimedia buffer. Used by u-boot/kernel/FreeRTOS
     # =================
-    ION_SIZE = 75 * SIZE_1M
+    ION_SIZE = 105 * SIZE_1M
     H26X_BITSTREAM_SIZE = 2 * SIZE_1M
     H26X_ENC_BUFF_SIZE = 0
     ISP_MEM_BASE_SIZE = 20 * SIZE_1M

build/boards/sg200x/sg2002_licheervnano_sd/partition/partition_sd.xml

@@ -1,4 +1,4 @@
 <physical_partition type="sd">
     <partition label="BOOT" size_in_kb="80960" readonly="false" file="boot.sd"/>
-    <partition label="ROOTFS" size_in_kb="1048576" readonly="false" file="rootfs.sd" />
+    <partition label="ROOTFS" size_in_kb="1572864" readonly="false" file="rootfs.sd" />
 </physical_partition>

build/boards/sg200x/sg2002_licheervnano_sd/sg2002_licheervnano_sd_defconfig

@@ -14,11 +14,16 @@ CONFIG_CP_EXT_WIRELESS=y
 CONFIG_STORAGE_TYPE_sd=y
 CONFIG_MIPI_PANEL_ZCT2133V1=y
 CONFIG_SENSOR_GCORE_GC4653=y
+CONFIG_SENSOR_OV_OV2685=y
+CONFIG_SENSOR_OV_OS04A10=y
+CONFIG_SENSOR_LONTIUM_LT6911=y
+CONFIG_SENSOR_SMS_SC035GS=y
 CONFIG_UBOOT_2021_10=y
 CONFIG_KERNEL_SRC_5.10=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SKIP_RAMDISK=y
+CONFIG_KERNEL_UNCOMPRESSED=y
+# CONFIG_SKIP_RAMDISK is not set
 CONFIG_SENSOR_TUNING_PARAM_cv181x_src_gcore_gc4653=y
+# CONFIG_SENSOR_TUNING_PARAM_sg200x_src_ov_os04a10=y
 # CONFIG_ROOTFS_OVERLAYFS is not set
-# CONFIG_ENABLE_FREERTOS is not set
+# CONFIG_ENABLE_FREERTOS=y
 # CONFIG_TARGET_PACKAGE_GATORD is not set

build/boards/sg200x/sg2002_licheervnano_sd/u-boot/cvi_board_init.c

@@ -73,7 +73,7 @@ int cvi_board_init(void)
         val &= ~(1 << 26); // set level to low
         mmio_write_32(0x03020000, val);
 
-        suck_loop(200);
+        suck_loop(50);
 	user_led_toggle();
 
         val = mmio_read_32(0x03020000); // signal level
@@ -88,6 +88,14 @@ int cvi_board_init(void)
         mmio_write_32(0x030010E0, 0x0); // CMD
         mmio_write_32(0x030010E4, 0x0); // CLK
 
+        // spi2 pinmux
+        // mmio_write_32(0x030010D0, 0x1); // CS
+        // mmio_write_32(0x030010DC, 0x1); // MISO
+        // mmio_write_32(0x030010E0, 0x1); // MOSI
+        // mmio_write_32(0x030010E4, 0x1); // SCK
+        // mmio_write_32(0x030010D8, 0x3); // DC
+        // mmio_write_32(0x03001038, 0x3); // RESET
+
         // uart bluetooth
         mmio_write_32(0x03001070, 0x1); // GPIOA 28 UART1 TX
         mmio_write_32(0x03001074, 0x1); // GPIOA 29 UART1 RX
@@ -113,10 +121,21 @@ int cvi_board_init(void)
         mmio_write_32(0x030010EC, 0x3); // GPIOB 0 GPIO_MODE
 
 	// for licheervnano beta
-	mmio_write_32(0x030010ac, 0x4); // PWRGPIO 2 PWM 10
+	//mmio_write_32(0x030010ac, 0x4); // PWRGPIO 2 PWM 10
+	mmio_write_32(0x030010ac, 0x0); // PWRGPIO 2 GPIO_MODE
 
         // camera function
-        mmio_write_32(0x0300116C, 0x5); // RX4N CAM_MCLK0
+        //mmio_write_32(0x0300116C, 0x5); // RX4N CAM_MCLK0 for alpha
+        mmio_write_32(0x0300118C, 0x5); // RX0N CAM_MCLK1 for beta
+
+	// spi1 on mipi csi 
+	/*
+	mmio_write_32(0x0300116C, 0x7); // spi1 clk   GPIOC2 MIPI_RX4N
+	mmio_write_32(0x03001170, 0x7); // spi1 cs    GPIOC3 MIPI_RX4P
+	mmio_write_32(0x03001174, 0x7); // spi1 miso  GPIOC4 MIPI_RX3N
+	mmio_write_32(0x03001178, 0x7); // spi1 mosi  GPIOC5 MIPI_RX3P
+	*/
+	
 
         // camera/tp i2c
         mmio_write_32(0x03001090, 0x5); // PWR_GPIO6 IIC4_SCL
@@ -128,8 +147,18 @@ int cvi_board_init(void)
         mmio_write_32(0x05027078, 0x11);// Unlock PWR_GPIO[3]
         mmio_write_32(0x0502707c, 0x11);// Unlock PWR_GPIO[4]
 
+	// bitbang i2c
+        mmio_write_32(0x0300103C, 0x03); // GPIOA 15 GPIO_MODE
+	mmio_write_32(0x03001058, 0x03); // GPIOA 27 GPIO_MODE
+
+	// bitbang spi
+	mmio_write_32(0x03001060, 0x03); // GPIOA 24 GPIO_MODE
+	mmio_write_32(0x0300105C, 0x03); // GPIOA 23 GPIO_MODE
+	mmio_write_32(0x03001054, 0x03); // GPIOA 25 GPIO_MODE
+	mmio_write_32(0x03001050, 0x03); // GPIOA 22 GPIO_MODE
+
         // wait hardware bootup
-        suck_loop(100);
+        suck_loop(50);
 	user_led_off();
         return 0;
 }

build/boards/sg200x/sg2002_licheervnano_sd/u-boot/sg2002_licheervnano_sd_defconfig

@@ -9,7 +9,7 @@ CONFIG_TARGET_CVITEK_CV181X=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_BOOTDELAY=1
+CONFIG_BOOTDELAY=0
 CONFIG_SYS_PROMPT="soph# "
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_XIMG is not set
@@ -63,3 +63,4 @@ CONFIG_BMP_32BPP=y
 CONFIG_BOOTLOGO=y
 CONFIG_CMD_CVI_VO=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_MBR=y

build/common_functions.sh

@@ -242,6 +242,28 @@ function pack_burn_image
   popd
 )}
 
+function pack_usbdl_image
+{(
+  pushd "$OUTPUT_DIR"
+  [ -d tmp ] && rm -rf tmp
+  set -eux
+  cp -rf $TOOLS_PATH/cv181x/usb_dl $OUTPUT_DIR
+  cd usb_dl
+  unzip -o $OUTPUT_DIR/upgrade.zip
+  cp $OUTPUT_DIR/fip.bin ./
+  set +eux
+  echo "========================================="
+  echo ""
+  echo "usb flash command:"
+  echo ""
+  echo "cd $OUTPUT_DIR/usb_dl && python3 cv181x_dl.py"
+  echo ""
+  echo ""
+  echo "========================================="
+
+  popd
+)}
+
 function pack_prog_img
 {(
   local tmp_dir

build/envsetup_soc.sh

@@ -621,6 +621,7 @@ function build_all()
   pack_data || return $?
   pack_system || return $?
   pack_upgrade || return $?
+  pack_usbdl_image || return $?
   pack_burn_image || return $?
 )}
 

build/scripts/fip_v2.mk

@@ -25,6 +25,7 @@ fsbl%: export FSBL_SECURE_BOOT_SUPPORT=${CONFIG_FSBL_SECURE_BOOT_SUPPORT}
 fsbl%: export ARCH=$(call qstrip,${CONFIG_ARCH})
 fsbl%: export OD_CLK_SEL=${CONFIG_OD_CLK_SEL}
 fsbl%: export VC_CLK_OVERDRIVE=${CONFIG_VC_CLK_OVERDRIVE}
+fsbl%: export TPU_PERF_MODE=$(shell if [ "${CONFIG_CHIP_cv1812cp}" = "y" ] || [ "${CONFIG_CHIP_sg2002}" = "y" ]; then echo "y";else echo "n";fi)
 fsbl-build: u-boot-build memory-map
 	$(call print_target)
 	${Q}mkdir -p ${FSBL_PATH}/build

build/sensors/sensor_list.json

@@ -31,6 +31,7 @@
 		"OV_OS04C10_SLAVE",
 		"OV_OS08A20",
 		"OV_OS08A20_SLAVE",
+		"OV_OV2685",
 		"OV_OV4689",
 		"OV_OV5647",
 		"OV_OV6211",

build/tools/common/sd_tools/genimage_rootless.cfg

@@ -5,9 +5,12 @@ image boot.vfat {
                         "fip.bin",
                         "rawimages/boot.sd",
 			"usb.dev",
-			"usb.rndis0",
-			"fb",
+			"usb.ncm",
+                        "usb.rndis",
 			"wifi.sta",
+			"gt9xx",
+			"logo.jpeg",
+			"ver",
                 }
         }
         size = 16M 

build/tools/common/sd_tools/sd_gen_burn_image_rootless.sh

@@ -16,7 +16,8 @@ fi
 output_dir=$1
 echo ${output_dir}
 set -eu
-image=`LC_ALL=C date | tr -d '( ):'`.img
+git_id=$(git rev-parse HEAD | head -c 6)
+image=$(LC_ALL=C date +%F-%R | sed -e 's/:/-/g' | tr -d '( ):')-${git_id}.img
 THISDIR=$(dirname $(realpath $0))
 mkdir -pv ${output_dir}/tmp/
 mkdir -pv ${output_dir}/root/
@@ -26,11 +27,14 @@ cp -fv ${output_dir}/fip.bin ${output_dir}/input/
 cp -fv ${output_dir}/rawimages/boot.sd ${output_dir}/input/rawimages/
 cp -fv ${output_dir}/rawimages/rootfs.sd ${output_dir}/input/
 touch ${output_dir}/input/usb.dev
-touch ${output_dir}/input/usb.rndis0
-touch ${output_dir}/input/fb
+touch ${output_dir}/input/usb.ncm
+touch ${output_dir}/input/usb.rndis
 touch ${output_dir}/input/wifi.sta
 touch ${output_dir}/input/gt9xx
+touch ${output_dir}/input/fb
+echo ${image} > ${output_dir}/input/ver
 cp -fv ${THISDIR}/genimage_rootless.cfg ${output_dir}/genimage.cfg
+cp -fv ${THISDIR}/logo.jpeg ${output_dir}/input/logo.jpeg
 sed -i -e "s/duo.img/${image}/g" ${output_dir}/genimage.cfg
 cd ${output_dir}/
 ${THISDIR}/genimage

build/tools/cv181x/usb_dl/rom_usb_dl/XmlParser.py

@@ -83,6 +83,8 @@ class XmlParser:
 
         if self.storage == "emmc":
             self.__calEmmcOffset(parts)
+        if self.storage == "sd":
+            self.__calEmmcOffset(parts)
         elif self.storage == "spinor":
             self.__calNorOffset(parts)
         elif self.storage == "spinand":

build/tools/cv181x/usb_dl/rom_usb_dl/cv181x_uboot_usb_download.py

@@ -41,8 +41,8 @@ def parse_Args():
         type=str)
     parser.add_argument(
         '--pid',
-        metavar='1001',
-        default='1001',
+        metavar='1000',
+        default='1000',
         type=str)
     parser.add_argument(
         "-v",

buildroot/board/cvitek/SG200X/overlay/etc/avahi/avahi-daemon.conf

@@ -30,7 +30,7 @@ use-ipv6=yes
 #use-iff-running=no
 #enable-dbus=yes
 #disallow-other-stacks=no
-allow-point-to-point=yes
+#allow-point-to-point=no
 #cache-entries-max=4096
 #clients-max=4096
 #objects-per-client-max=1024
@@ -45,7 +45,7 @@ enable-wide-area=yes
 #disable-publishing=no
 #disable-user-service-publishing=no
 #add-service-cookie=no
-#publish-addresses=yes
+publish-addresses=yes
 publish-hinfo=yes
 publish-workstation=yes
 #publish-domain=yes

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S00kmod

@@ -15,7 +15,7 @@ then
 	insmod soph_vpss.ko
 	insmod soph_dwa.ko
 	insmod soph_vo.ko
-	insmod soph_mipi_tx.ko
+#	insmod soph_mipi_tx.ko
 	insmod soph_rgn.ko
 	insmod soph_wdt.ko
 	insmod soph_clock_cooling.ko
@@ -29,9 +29,6 @@ then
 	insmod soph_pwm.ko
 	insmod soph_saradc.ko
 	insmod soph_wiegand.ko
-	insmod cfg80211.ko
-	insmod 3rd/aic8800_bsp.ko
-	insmod 3rd/aic8800_fdrv.ko
 	echo "OK"
 	exit 0
 fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S00pmu

@@ -0,0 +1,31 @@
+#!/bin/sh
+
+if ! command -v i2cget &> /dev/null
+then
+    echo "i2cdetect not find, please install i2c-tools"
+    exit 1
+fi
+
+pmu_version=$(i2cget -y 4 0x34 0x03)
+pmu_version=$((pmu_version & 0xCF))
+
+chip_id_1=$(printf "%d" 0x47)
+chip_id_2=$(printf "%d" 0x4a)
+
+if [ "$pmu_version" -eq "$chip_id_1" ] || [ "$pmu_version" -eq "$chip_id_2" ]; then
+    case "$1" in
+    start)
+        exec /usr/bin/axp2101
+        echo "Starting PMU: OK\n"
+    ;;
+    stop)
+        runlevel=$(cat /run/runlevel | awk '{ print $1 }')
+        if [ "$runlevel" = "0" ]; then
+            printf "Stopping PMU\n"
+            value=$(i2cget -y 4 0x34 0x10)
+            value=$((value | 0x01))
+            i2cset -y 4 0x34 0x10 $value
+        fi
+    ;;
+    esac
+fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S02config

@@ -8,11 +8,23 @@ then
 	then
 		cp -vf /boot/sshd_config /etc/ssh/sshd_config
 	fi
+	if [ -e /boot/resolv.conf ]
+	then
+		rm -rf /etc/resolv.conf
+		cp -vf /boot/resolv.conf /etc/resolv.conf
+	fi
 	if [ -e /boot/input-event-daemon ]
 	then
-		chmod 0644 /etc/input-event-daemon.conf
+		if [ ! -e /etc/input-event-daemon.conf ]
+		then
+			cp /etc/input-event-daemon.conf.bak /etc/input-event-daemon.conf
+		fi
 	else
-		chmod 0000 /etc/input-event-daemon.conf
+		if [ -e /etc/input-event-daemon.conf ]
+		then
+			cp /etc/input-event-daemon.conf /etc/input-event-daemon.conf.bak
+			rm /etc/input-event-daemon.conf
+		fi
 	fi
 	if [ -e /boot/rc.local ]
 	then
@@ -24,7 +36,41 @@ then
 	fi
 	if [ -e /boot/console_handler.sh ]
 	then
-		cp /boot/ttyGS0_handler.sh /etc/ttyGS0_handler.sh
+		cp /boot/console_handler.sh /etc/console_handler.sh
+	fi
+	if [ -e /boot/alpha ]
+	then
+		if [ ! -e /mnt/data/sensor_cfg.ini ]
+		then
+			cp /mnt/data/sensor_cfg.ini.alpha /mnt/data/sensor_cfg.ini
+		fi
+		if [ $(cat /mnt/data/sensor_cfg.ini | wc -l) -eq 0 ]
+		then
+			cp /mnt/data/sensor_cfg.ini.beta /mnt/data/sensor_cfg.ini
+		fi
+		# MIPI RX 4N PINMUX MCLK0
+		devmem 0x0300116C 32 0x5
+		# MIPI RX 0N PINMUX MIPIP RX 0N
+		devmem 0x0300118C 32 0x3
+		echo " alpha "
+	else
+		if [ ! -e /mnt/data/sensor_cfg.ini ]
+		then
+			cp /mnt/data/sensor_cfg.ini.beta /mnt/data/sensor_cfg.ini
+		fi
+		if [ $(cat /mnt/data/sensor_cfg.ini | wc -l) -eq 0 ]
+		then
+			cp /mnt/data/sensor_cfg.ini.beta /mnt/data/sensor_cfg.ini
+		fi
+		# MIPI RX 4N PINMUX MIPI RX 4N
+		devmem 0x0300116C 32 0x3
+		# MIPI RX 0N PINMUX MCLK1
+		devmem 0x0300118C 32 0x5
+		echo -n " beta "
+	fi
+	if [ -e /boot/kvmtest ]
+	then
+		cp /mnt/data/sensor_cfg.ini.LT /mnt/data/sensor_cfg.ini
 	fi
 	echo "OK"
 fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S02devicekey

@@ -0,0 +1,11 @@
+#!/bin/sh
+
+if [ "$1" = "start" ]
+then
+	str_value=$(cat /sys/class/cvi-base/base_uid | awk '{print $2}')
+	first_uint=$(echo $str_value | cut -d'_' -f1)
+	second_uint=$(echo $str_value | cut -d'_' -f2)
+	result="$first_uint$second_uint"
+	echo $result > /device_key
+fi
+

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S03usbdev

@@ -1,5 +1,6 @@
 #!/bin/sh
 
+
 if [ "$1" = "start" ]
 then
 	. /etc/profile
@@ -11,26 +12,56 @@ then
 	then
 		echo "usb mode: device"
 		cd /sys/kernel/config/usb_gadget
-		mkdir g0
+		mkdir -p g0
 		cd g0
 		if [ -e /boot/usb.idVendor ]
 		then
 			cat /boot/usb.idVendor > idVendor
 		else
-			echo 0x3346 > idVendor
+			echo 0x359F > idVendor
 		fi
 		if [ -e /boot/usb.idProduct ]
 		then
 			cat /boot/usb.idProduct > idProduct
 		else
-			echo 0x1009 > idProduct
+			echo 0x2120 > idProduct
 		fi
-		mkdir strings/0x409
+		if [ -e /boot/usb.bcdDevice ]
+		then
+			cat /boot/usb.bcdDevice > bcdDevice
+		else
+			echo 0x0300 > bcdDevice
+		fi
+		if [ -e /boot/usb.bcdUSB ]
+		then
+			cat /boot/usb.bcdUSB > bcdUSB
+		else
+			echo 0x0200 > bcdUSB
+		fi
+		if [ -e /boot/usb.bDeviceClass ]
+		then
+			cat /boot/usb.bDeviceClass > bDeviceClass
+		else
+			echo 0xef > bDeviceClass
+		fi
+		if [ -e /boot/usb.bDeviceSubClass ]
+		then
+			cat /boot/usb.bDeviceSubClass > bDeviceSubClass
+		else
+			echo 0x02 > bDeviceSubClass
+		fi
+		if [ -e /boot/usb.bDeviceProtocol ]
+		then
+			cat /boot/usb.bDeviceProtocol > bDeviceProtocol
+		else
+			echo 0x01 > bDeviceProtocol
+		fi
+		mkdir -p strings/0x409
 		if [ -e /boot/usb.serialnumber ]
 		then
 			cat /boot/usb.serialnumber > strings/0x409/serialnumber
 		else
-			echo '0123456789ABCDEF' > strings/0x409/serialnumber
+			cat /device_key > strings/0x409/serialnumber
 		fi
 		if [ -e /boot/usb.manufacturer ]
 		then
@@ -44,20 +75,25 @@ then
 		else
 			echo 'licheervnano' > strings/0x409/product
 		fi
-		mkdir configs/c.1
+		mkdir -p configs/c.1
+		# uvc
+		if [ -e /boot/usb.uvc ]
+		then
+			/etc/init.d/uvc_tool.sh mount /boot/usb.uvc
+			/etc/init.d/uvc_tool.sh server
+		fi
+
 		if [ -e /boot/usb.GS0 ]
 		then
-			mkdir functions/acm.GS0
+			mkdir -p functions/acm.GS0
+			rm -rf configs/c.1/acm.GS0
 			ln -s functions/acm.GS0 configs/c.1/
 		fi
-		if [ -e /boot/usb.rndis0 ]
-		then
-			mkdir functions/rndis.usb0
-			ln -s functions/rndis.usb0 configs/c.1/
-		fi
+
 		if [ -e /boot/usb.disk0 ]
 		then
-			mkdir functions/mass_storage.disk0
+			mkdir -p functions/mass_storage.disk0
+			rm -rf configs/c.1/mass_storage.disk0
 			ln -s functions/mass_storage.disk0 configs/c.1/
 			echo 1 > functions/mass_storage.disk0/lun.0/removable
 			if [ -e /boot/usb.disk0.ro ]
@@ -78,6 +114,60 @@ then
 				cat /boot/usb.disk0 > functions/mass_storage.disk0/lun.0/file
 			fi
 		fi
+
+		# rndis
+		if [ -e /boot/usb.rndis ]
+		then
+			mkdir -p functions/rndis.usb0
+			ln -s functions/rndis.usb0 configs/c.1/
+			echo e0 > functions/rndis.usb0/class
+			echo 01 > functions/rndis.usb0/subclass
+			echo 03 > functions/rndis.usb0/protocol
+		fi
+
+		# ncm
+		if [ -e /boot/usb.ncm ]
+		then
+			mkdir -p functions/ncm.usb0
+			ln -s functions/ncm.usb0 configs/c.1/
+		fi
+
+		# keyboard
+		if [ -e /boot/usb.keyboard ]
+		then
+			mkdir functions/hid.GS0
+			# echo 1 > functions/hid.GS0/subclass
+			echo 1 > functions/hid.GS0/wakeup_on_write
+			echo 1 > functions/hid.GS0/protocol
+			echo 6 > functions/hid.GS0/report_length
+			echo -ne \\x05\\x01\\x09\\x06\\xa1\\x01\\x05\\x07\\x19\\xe0\\x29\\xe7\\x15\\x00\\x25\\x01\\x75\\x01\\x95\\x08\\x81\\x02\\x95\\x01\\x75\\x08\\x81\\x03\\x95\\x05\\x75\\x01\\x05\\x08\\x19\\x01\\x29\\x05\\x91\\x02\\x95\\x01\\x75\\x03\\x91\\x03\\x95\\x06\\x75\\x08\\x15\\x00\\x25\\x65\\x05\\x07\\x19\\x00\\x29\\x65\\x81\\x00\\xc0 > functions/hid.GS0/report_desc
+			ln -s functions/hid.GS0 configs/c.1
+		fi
+
+		# mouse
+		if [ -e /boot/usb.mouse ]
+		then
+			mkdir functions/hid.GS1
+			# echo 1 > functions/hid.GS1/subclass
+			echo 1 > functions/hid.GS1/wakeup_on_write
+			echo 2 > functions/hid.GS1/protocol
+			echo -ne \\x34 > functions/hid.GS1/report_length
+			echo -ne \\x5\\x1\\x9\\x2\\xa1\\x1\\x9\\x1\\xa1\\x0\\x5\\x9\\x19\\x1\\x29\\x3\\x15\\x0\\x25\\x1\\x95\\x3\\x75\\x1\\x81\\x2\\x95\\x1\\x75\\x5\\x81\\x3\\x5\\x1\\x9\\x30\\x9\\x31\\x9\\x38\\x15\\x81\\x25\\x7f\\x75\\x8\\x95\\x3\\x81\\x6\\xc0\\xc0 > functions/hid.GS1/report_desc        
+			ln -s functions/hid.GS1 configs/c.1
+		fi
+
+		# touchpad
+		if [ -e /boot/usb.touchpad ]
+		then
+			mkdir functions/hid.GS2
+			# echo 1 > functions/hid.GS2/subclass
+			echo 1 > functions/hid.GS2/wakeup_on_write
+			echo 2 > functions/hid.GS2/protocol
+			echo 6 > functions/hid.GS2/report_length
+			echo -ne \\x05\\x01\\x09\\x02\\xa1\\x01\\x09\\x01\\xa1\\x00\\x05\\x09\\x19\\x01\\x29\\x03\\x15\\x00\\x25\\x01\\x95\\x03\\x75\\x01\\x81\\x02\\x95\\x01\\x75\\x05\\x81\\x01\\x05\\x01\\x09\\x30\\x09\\x31\\x15\\x00\\x26\\xff\\x7f\\x35\\x00\\x46\\xff\\x7f\\x75\\x10\\x95\\x02\\x81\\x02\\x05\\x01\\x09\\x38\\x15\\x81\\x25\\x7f\\x35\\x00\\x45\\x00\\x75\\x08\\x95\\x01\\x81\\x06\\xc0\\xc0 > functions/hid.GS2/report_desc
+			ln -s functions/hid.GS2 configs/c.1
+		fi
+
 		ls /sys/class/udc/ | cat > UDC
 		echo device > /proc/cviusb/otg_role
 	fi
@@ -87,4 +177,24 @@ if [ "$1" = "stop" ]
 then
 	echo '' > /sys/kernel/config/usb_gadget/g0/UDC
 	echo host > /proc/cviusb/otg_role
+	# uvc
+	if [ -e /sys/kernel/config/usb_gadget/g0/configs/c.1/uvc.usb0 ]
+	then
+		/etc/init.d/uvc_tool.sh unmount
+	fi
+
+	# rndis
+	if [ -e /sys/kernel/config/usb_gadget/g0/configs/c.1/rndis.usb0 ]
+	then
+		unlink /sys/kernel/config/usb_gadget/g0/configs/c.1/rndis.usb0
+		rmdir /sys/kernel/config/usb_gadget/g0/functions/rndis.usb0
+	fi
+
+	# ncm
+	if [ -e /sys/kernel/config/usb_gadget/g0/configs/c.1/ncm.usb0 ]
+	then
+		unlink /sys/kernel/config/usb_gadget/g0/configs/c.1/ncm.usb0
+		rmdir /sys/kernel/config/usb_gadget/g0/functions/ncm.usb0
+	fi
 fi
+

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S04backlight

@@ -0,0 +1,33 @@
+#!/bin/sh
+
+if [ "$1" = "start" ]
+then
+	. /etc/profile
+	if [ ! -e /boot/alpha ]
+	then
+		devmem 0x030010AC 32 0x04 # PINMUX PWM10
+		blpwm="/sys/class/pwm/pwmchip8/pwm2/"
+		if [ ! -e "${blpwm}" ]
+		then
+			echo 2 > /sys/class/pwm/pwmchip8/export
+		fi
+		echo 0 > $blpwm/enable
+		echo "10000" > ${blpwm}/period # 100KHZ
+		panel_value=""
+		if [ -e /boot/board ]
+		then
+			panel_value=$(grep '^panel=' /boot/board | cut -d '=' -f 2)
+		elif [ -e /boot/uEnv.txt ]
+		then
+			panel_value=$(grep '^panel=' /boot/uEnv.txt | cut -d '=' -f 2)
+		fi
+		if [ "$panel_value" = "st7701_hd228001c31" ]
+		then
+			echo "2000" > ${blpwm}/duty_cycle # 20%
+		else
+			echo "9000" > ${blpwm}/duty_cycle
+		fi
+		echo 1 > $blpwm/enable
+	fi
+	exit 0
+fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S05tp

@@ -3,6 +3,23 @@
 if [ "$1" = "start" ]
 then
 	. /etc/profile
+	panel_value=""
+	if [ -e /boot/board ]
+	then
+		panel_value=$(grep '^panel=' /boot/board | cut -d '=' -f 2)
+	elif [ -e /boot/uEnv.txt ]
+	then
+		panel_value=$(grep '^panel=' /boot/uEnv.txt | cut -d '=' -f 2)
+	fi
+	if [ "$panel_value" = "st7701_lct024bsi20" ]
+	then
+		echo "load cst7xx touchscreen driver"
+		insmod /mnt/system/ko/hynitron_touch_new.ko
+	elif [ "$panel_value" = "st7701_hd228001c31" ]
+	then
+		echo "load cst3xx touchscreen driver"
+		insmod /mnt/system/ko/hynitron_touch.ko
+	fi
 	if [ -e /boot/gt9xx ]
 	then
 		echo "load gt9xx touchscreen driver"

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S10uuid

@@ -19,7 +19,7 @@ then
 		prefix=$(cat /boot/hostname.prefix)
 	fi
 	old_hostname=$(cat /etc/hostname)
-	new_hostname=${prefix}-$(sha512sum /sys/class/cvi-base/base_uid | head -c 4)
+	new_hostname=${prefix}-$(sha512sum /device_key | head -c 4)
 
 	if [ -e /boot/hostname ]
 	then
@@ -38,25 +38,11 @@ then
 	then
 		new_ethmac=$(cat /boot/ethmac)
 	else
-		new_ethmac=$(hex2mac 48da356f$(sha512sum /sys/class/cvi-base/base_uid | head -c 4))
+		new_ethmac=$(hex2mac 48da356f$(sha512sum /device_key  | head -c 4))
 	fi
 
 	ifconfig eth0 down
 	ip link set eth0 address ${new_ethmac}
 	ifconfig eth0 up
 	echo "ethernet mac address: ${new_ethmac}"
-
-	if [ -e /boot/usb.rndis0 ]
-	then
-		if [ -e /boot/usb.rndis0.mac ]
-		then
-			new_rndismac=$(cat /boot/usb.rndis0.mac)
-		else
-			new_rndismac=$(hex2mac 48da356e$(sha512sum /sys/class/cvi-base/base_uid | head -c 4))
-		fi
-		ifconfig usb0 down
-		ip link set usb0 address ${new_rndismac}
-		ifconfig usb0 up
-		echo "rndis mac address: ${new_rndismac}"
-	fi
 fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S25wifimod

@@ -0,0 +1,14 @@
+#!/bin/sh
+
+if [ "$1" = "start" ]
+then
+	. /etc/profile
+	printf "load wifi kernel module: "
+	cd /mnt/system/ko/
+	insmod cfg80211.ko
+	insmod 3rd/aic8800_bsp.ko
+	insmod 3rd/aic8800_fdrv.ko
+	insmod 3rd/8733bs.ko
+	echo "OK"
+	exit 0
+fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S30gadget_nic

@@ -0,0 +1,176 @@
+#!/bin/sh
+
+. /etc/profile
+
+gen_udhcpd_conf() {
+	interface=${1}
+	ipv4_prefix=${2}
+	echo "start ${ipv4_prefix}.100"
+	echo "end ${ipv4_prefix}.200"
+	echo "interface ${interface}"
+	echo "pidfile /var/run/udhcpd.${interface}.pid"
+	echo "lease_file /var/lib/misc/udhcpd.${interface}.leases"
+	echo "option subnet 255.255.255.0"
+	echo "option lease 864000"
+}
+
+hex2mac() {
+	MAC=""
+	seq 2 2 12 | while read i
+	do
+		echo -n ${1} | head -c $i | tail -c 2
+		if [ $i != 12 ]
+		then
+			echo -n ':'
+		fi
+	done | tr '[:upper:]' '[:lower:]'
+}
+
+start() {
+	# S03usbdev start first
+	if [ -e /boot/usb.dev ]
+	then
+		rndis_ifname=usb0
+		# RNDIS
+		if [ -e /boot/usb.rndis ]
+		then
+			# mac
+			if [ -e /boot/usb.rndis.mac ]
+			then
+				new_rndismac=$(cat /boot/usb.rndis.mac)
+			else
+				new_rndismac=$(hex2mac 48da356f$(sha512sum /device_key | head -c 4))
+			fi
+			ip link set $rndis_ifname address ${new_rndismac}
+			ifconfig $rndis_ifname up
+			echo "rndis mac address: ${new_rndismac}"
+
+			# dhcp
+			if [ ! -e /boot/rndis.nodhcpd ]
+			then
+				if [ -e /boot/rndis.ipv4_prefix ]
+				then
+					ipv4_prefix=`cat /boot/rndis.ipv4_prefix`
+				else
+					id2=$(printf "%d" 0x$(sha512sum /device_key | head -c 2))
+					id3=$(printf "%d" 0x$(sha512sum /device_key | head -c 4 | tail -c 2))
+					id3=$((id3 + 1))
+					if [ "$id2" = "$id3" ]
+					then
+						id2=$((id2 + 2))
+					fi
+					if [ "$id2" -ge 255 ]
+					then
+						id2=252
+					fi
+					if [ "$id3" -ge 255 ]
+					then
+						id3=251
+					fi
+					ipv4_prefix=10.$id2.$id3
+				fi
+				gen_udhcpd_conf $rndis_ifname "${ipv4_prefix}"  > /etc/udhcpd.${rndis_ifname}.conf
+				ip addr add $ipv4_prefix.1/24 dev $rndis_ifname
+				udhcpd -S /etc/udhcpd.${rndis_ifname}.conf
+			fi
+			echo "RNDIS DHCP OK"
+			rndis_ifname=usb1
+		fi
+
+		# CDC NCM
+		if [ -e /boot/usb.ncm ]
+		then
+			# mac
+			if [ -e /boot/usb.ncm.mac ]
+			then
+				new_mac=$(cat /boot/usb.ncm.mac)
+			else
+				new_mac=$(hex2mac 48da356e$(sha512sum /device_key | head -c 4))
+			fi
+			ip link set $rndis_ifname address ${new_mac}
+			ifconfig $rndis_ifname up
+			echo "ncm mac address: ${new_mac}"
+
+			# dhcp
+			if [ ! -e /boot/ncm.nodhcpd ]
+			then
+				if [ -e /boot/ncm.ipv4_prefix ]
+				then
+					ipv4_prefix=`cat /boot/ncm.ipv4_prefix`
+				else
+					id2=$(printf "%d" 0x$(sha512sum /device_key | head -c 2))
+					id3=$(printf "%d" 0x$(sha512sum /device_key | head -c 4 | tail -c 2))
+					if [ "$id2" = "$id3" ]
+					then
+						id2=$((id2 + 1))
+					fi
+					if [ "$id2" -ge 255 ]
+					then
+						id2=253
+					fi
+					if [ "$id3" -ge 255 ]
+					then
+						id3=254
+					fi
+					ipv4_prefix=10.$id2.$id3
+				fi
+				gen_udhcpd_conf $rndis_ifname "${ipv4_prefix}"  > /etc/udhcpd.${rndis_ifname}.conf
+				ip addr add $ipv4_prefix.1/24 dev $rndis_ifname
+				udhcpd -S /etc/udhcpd.${rndis_ifname}.conf
+			fi
+			echo "CDC NCM DHCP OK"
+		fi
+	fi
+}
+
+stop() {
+	# first card
+	if [ -e /var/run/udhcpd.usb0.pid ]
+	then
+		kill $(cat "/var/run/udhcpd.usb0.pid")
+		rm /var/run/udhcpd.usb0.pid || true
+	fi
+	pnum=$(ps -ef|grep udhcpd|grep -v grep| grep udhcpd.usb0.conf | awk '{print $1}' | wc -l)
+	if [ x$pnum != x0 ]
+	then
+		ps -ef|grep udhcpd|grep -v grep| grep udhcpd.usb0.conf | awk '{print $1}'|xargs kill -2 || true
+	fi
+	usb0_info=$(ip link |grep usb0)
+	if [ -n "$usb0_info" ]
+	then
+		ifconfig usb0 down
+	fi
+
+	# second card
+	if [ -e /var/run/udhcpd.usb1.pid ]
+	then
+		kill $(cat /var/run/udhcpd.usb1.pid)
+		rm /var/run/udhcpd.usb1.pid || true
+	fi
+	pnum=$(ps -ef|grep udhcpd|grep -v grep| grep udhcpd.usb1.conf | awk '{print $1}' | wc -l)
+	if [ x$pnum != x0 ]
+	then
+		ps -ef|grep udhcpd|grep -v grep| grep udhcpd.usb1.conf | awk '{print $1}'|xargs kill -2 || true
+	fi
+	usb0_info=$(ip link |grep usb1)
+	if [ -n "$usb0_info" ]
+	then
+		ifconfig usb1 down
+	fi
+}
+
+restart() {
+	stop
+	start
+}
+
+if [ "${1}" = "start" ]
+then
+	start
+elif [ "${1}" = "stop" ]
+then
+	stop
+elif [ "${1}" = "restart" ]
+then
+	restart
+fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S30rndis

@@ -1,70 +0,0 @@
-#!/bin/sh
-
-. /etc/profile
-
-gen_udhcpd_conf() {
-	interface=${1}
-	ipv4_prefix=${2}
-	echo "start ${ipv4_prefix}.100"
-	echo "end ${ipv4_prefix}.200"
-	echo "interface ${interface}"
-	echo "pidfile /var/run/udhcpd.${interface}.pid"
-	echo "lease_file /var/lib/misc/udhcpd.${interface}.leases"
-	echo "option subnet 255.255.255.0"
-	echo "option lease 864000"
-}
-
-start() {
-	if [ -e /boot/usb.rndis0 ]
-	then
-		printf "start usb rndis: "
-		if [ ! -e /boot/rndis.nodhcpd ]
-		then
-			if [ -e /boot/rndis.ipv4_prefix ]
-			then
-				ipv4_prefix=`cat /boot/rndis.ipv4_prefix`
-			else
-				id2=$(printf "%d" 0x$(sha512sum /sys/class/cvi-base/base_uid | head -c 2))
-				id3=$(printf "%d" 0x$(sha512sum /sys/class/cvi-base/base_uid | head -c 4 | tail -c 2))
-				if [ "$id2" = "$id3" ]
-				then
-					id2=$((id2 + 1))
-				fi
-				if [ "$id2" -ge 255 ]
-				then
-					id2=253
-				fi
-				if [ "$id3" -ge 255 ]
-				then
-					id3=254
-				fi
-				ipv4_prefix=10.$id2.$id3
-			fi
-			gen_udhcpd_conf usb0 "${ipv4_prefix}"  > /etc/udhcpd.usb0.conf
-			ip addr add $ipv4_prefix.1/24 dev usb0
-			udhcpd -S /etc/udhcpd.usb0.conf
-		fi
-		echo "ok"
-	fi
-}
-
-stop() {
-	kill `cat /var/run/udhcpd.usb0.pid`
-        rm /var/run/udhcpd.usb0.pid
-}
-
-restart() {
-	start
-	stop
-}
-
-if [ "${1}" = "start" ]
-then
-	start
-elif [ "${1}" = "stop" ]
-then
-	stop
-elif [ "${1}" = "restart" ]
-then
-	restart
-fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S30wifi

@@ -39,13 +39,13 @@ gen_udhcpd_conf() {
 start() {
 	if [ -e /boot/wifi.sta ]
 	then
+		echo "wifi mode: sta"
 		if [ -e /boot/wpa_supplicant.conf ]
 		then
 			cp /boot/wpa_supplicant.conf /etc/wpa_supplicant.conf
 		else
-			echo "wifi mode: sta"
-			ssid="licheervnano"
-			pass="licheervnano"
+			ssid=""
+			pass=""
 			if [ -e /boot/wifi.ssid ]
 			then
 				echo -n "ssid: "
@@ -58,23 +58,26 @@ start() {
 				cat /boot/wifi.pass
 				pass=`cat /boot/wifi.pass`
 			fi
-			echo "ctrl_interface=/var/run/wpa_supplicant" > /etc/wpa_supplicant.conf
-			wpa_passphrase "$ssid" "$pass" >> /etc/wpa_supplicant.conf
+			if [ ! -z "${ssid}${pass}" ]
+			then
+				echo "ctrl_interface=/var/run/wpa_supplicant" > /etc/wpa_supplicant.conf
+				wpa_passphrase "$ssid" "$pass" >> /etc/wpa_supplicant.conf
+			fi
 		fi
 		wpa_supplicant -B -i wlan0 -c /etc/wpa_supplicant.conf
-		if [ -e /boot/wifi.dhcp ]
+		if [ ! -e /boot/wifi.nodhcp ]
 		then
 			(udhcpc -i wlan0 -t 10 -T 1 -A 5 -b -p /run/udhcpc.wlan0.pid) &
 		fi
 	elif [ -e /boot/wifi.ap ]
 	then
+		echo "wifi mode: ap"
 		if [ -e /boot/hostapd.conf ]
 		then
 			cp /boot/hostapd.conf /etc/hostapd.conf
 		else
-			echo "wifi mode: ap"
-			id2=$(printf "%d" 0x$(sha512sum /sys/class/cvi-base/base_uid | head -c 2))
-			id3=$(printf "%d" 0x$(sha512sum /sys/class/cvi-base/base_uid | head -c 4 | tail -c 2))
+			id2=$(printf "%d" 0x$(sha512sum /device_key | head -c 2))
+			id3=$(printf "%d" 0x$(sha512sum /device_key | head -c 4 | tail -c 2))
 			if [ "$id2" = "$id3" ]
 			then
 				id2=$((id2 + 1))
@@ -88,30 +91,40 @@ start() {
 				id3=254
 			fi
 			ssid="licheervnano-${id2}${id3}"
-                        pass="licheervnano"
-                        if [ -e /boot/wifi.ssid ]
-                        then
-                                echo -n "ssid: "
-                                cat /boot/wifi.ssid
-                                ssid=`cat /boot/wifi.ssid`
-                        fi
-                        if [ -e /boot/wifi.pass ]
-                        then
-                                echo -n "wifi.pass: "
-                                cat /boot/wifi.pass
-                                pass=`cat /boot/wifi.pass`
-                        fi
-			gen_hostapd_conf "$ssid" "$pass" > /etc/hostapd.conf
-			if [ -e /boot/wifi.ipv4_prefix ]
+			pass="licheervnano"
+			if [ -e /boot/wifi.ssid ]
 			then
-				ipv4_prefix=`cat /boot/rndis.ipv4_prefix`
-			else
-				ipv4_prefix=10.$id3.$id2
+				echo -n "ssid: "
+				cat /boot/wifi.ssid
+				ssid=`cat /boot/wifi.ssid`
 			fi
-			gen_udhcpd_conf wlan0 "${ipv4_prefix}"  > /etc/udhcpd.wlan0.conf
-			ifconfig wlan0 up
-			ip addr add $ipv4_prefix.1/24 dev wlan0
+			if [ -e /boot/wifi.pass ]
+			then
+				echo -n "wifi.pass: "
+				cat /boot/wifi.pass
+				pass=`cat /boot/wifi.pass`
+			fi
+			gen_hostapd_conf "$ssid" "$pass" > /etc/hostapd.conf
 		fi
+		if [ -e /boot/wifi.ipv4_prefix ]
+		then
+			ipv4_prefix=`cat /boot/wifi.ipv4_prefix`
+		else
+			ipv4_prefix=10.$id3.$id2
+		fi
+		if [ ! -e /etc/udhcpd.wlan0.conf ]
+		then
+			gen_udhcpd_conf wlan0 "${ipv4_prefix}"  > /etc/udhcpd.wlan0.conf
+		fi
+		ifconfig wlan0 up
+		ip route del default || true
+		# routes=$(ip route show | grep 'dev wlan0' | awk '{print $1}')
+		# for route in $routes; do
+		# 	ip route del $route dev wlan0
+		# 	echo "Deleted route $route dev wlan0"
+		# done
+		ip add flush dev wlan0
+		ip addr add $ipv4_prefix.1/24 dev wlan0
 		hostapd -B -i wlan0 /etc/hostapd.conf
 		udhcpd -S /etc/udhcpd.wlan0.conf
 	elif [ -e /boot/wifi.mon ]
@@ -122,17 +135,25 @@ start() {
 }
 
 stop() {
-	killall wpa_supplicant
-	kill `cat /run/udhcpc.wlan0.pid`
-	rm /run/udhcpc.wlan0.pid
-	kill `cat /var/run/udhcpd.wlan0.pid`
-	rm /var/run/udhcpd.wlan0.pid
-	airmon-ng stop wlan0mon
+	ps -ef|grep hostapd|grep -v grep|awk '{print $1}'|xargs kill -2 || true
+	ps -ef|grep "udhcpd -S /etc/udhcpd.wlan0.conf" |grep -v grep|awk '{print $1}'|xargs kill -2 || true
+	killall wpa_supplicant || true
+	if [ -e /run/udhcpc.wlan0.pid ]
+	then
+		kill `cat /run/udhcpc.wlan0.pid` || true
+		rm -f /run/udhcpc.wlan0.pid
+	fi
+	if [ -e /var/run/udhcpd.wlan0.pid ]
+	then
+		kill `cat /var/run/udhcpd.wlan0.pid`  || true
+		rm -f /var/run/udhcpd.wlan0.pid
+	fi
+	airmon-ng stop wlan0mon || true
 }
 
 restart() {
-	start
 	stop
+	start
 }
 
 if [ "${1}" = "start" ]

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S99ednctest

@@ -0,0 +1,39 @@
+#!/bin/sh
+
+case "$1" in
+  start)
+    printf "Starting ednctest: "
+    if [ -e /boot/ednctest ]
+    then
+	    touch /tmp/ednctest
+    fi
+    . /etc/profile
+    (
+    while true
+    do
+	    if [ ! -e /tmp/ednctest ]
+	    then
+		break
+	    fi
+	    if [ ! -e /tmp/rand.h264 ]
+	    then
+	    	dd if=/dev/urandom of=/tmp/rand.yuv bs=1M count=2
+		/mnt/system/usr/bin/sample_venc -h 1080 -w 1080 -c 264 -i rand.yuv -o /tmp/rand
+	    fi
+	    /mnt/system/usr/bin/sample_vcodec sample_vdec -c 264 -i rand.h264 -o rand
+    done
+    ) &
+    [ $? = 0 ] && echo "OK" || echo "FAIL"
+  ;;
+  stop)
+    printf "Stopping ednctest: "
+    rm /tmp/ednctest
+    echo "OK"
+  ;;
+  restart)
+    printf "Restart ednctest: "
+    $(realpath ${0}) stop
+    $(realpath ${0}) start
+    echo "OK"
+  ;;
+esac

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S99modeltest

@@ -0,0 +1,35 @@
+#!/bin/sh
+
+case "$1" in
+  start)
+    printf "Starting modeltest: "
+    if [ -e /boot/modeltest ]
+    then
+	    touch /tmp/modeltest
+    fi
+    (
+    while true
+    do
+	    if [ ! -e /tmp/modeltest ]
+	    then
+		break
+	    fi
+	    cd /usr/bin/
+	nice -n 19 model_runner_test 10000
+    done
+    ) &
+    [ $? = 0 ] && echo "OK" || echo "FAIL"
+  ;;
+  stop)
+    printf "Stopping modeltest: "
+    rm /tmp/modeltest
+    killall model_runner
+    echo "OK"
+  ;;
+  restart)
+    printf "Restart modeltest: "
+    $(realpath ${0}) stop
+    $(realpath ${0}) start
+    echo "OK"
+  ;;
+esac

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S99resizefs

@@ -10,5 +10,5 @@ then
 	100%
 	" | parted ---pretend-input-tty /dev/mmcblk0 "resizepart 2 100%"
 	# resize data filesystem
-	(resize2fs /dev/mmcblk0p2 &> /dev/console) &
+	(resize2fs /dev/mmcblk0p2) &
 fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S99temptest

@@ -27,8 +27,8 @@ case "$1" in
 	    fi
 	    echo "soc temp: $soc_temp" | fbbar 32 $colorfg $colorbg
 	    colorfg=0xFFFFFFFF
-            echo "soc id: $(cat /sys/class/cvi-base/base_uid)" | fbbar 48 $colorfg $colorbg
-            sleep 1
+      echo "soc id: $(cat /device_key)" | fbbar 48 $colorfg $colorbg
+      sleep 1
     done
     ) &
     [ $? = 0 ] && echo "OK" || echo "FAIL"

buildroot/board/cvitek/SG200X/overlay/etc/init.d/uvc_tool.sh

@@ -0,0 +1,274 @@
+#! /bin/sh
+
+# 支持的格式，可以通过修改这个变量自定义支持的格式
+# Supported formats, you can customize the list by modifying this variable
+supported_formats="yuyv mjpg"
+
+# 支持的分辨率，可以通过修改这个变量自定义支持的分辨率
+# Supported resolutions, you can customize the list by modifying this variable
+supported_resolutions="480x320 640x360 640x480 1280x720 1920x1080 2560x1440"
+
+
+parse_uvc_config() {
+	input_file="$1"  # 传入的文件路径 / Path to the input file
+	parsed_data=""  # 初始化 parsed_data 为空 / Initialize parsed_data as empty
+
+	# 检查文件是否存在并可读取 / Check if the file exists and is readable
+	if [ -z "$input_file" ]; then
+		# 没有提供文件路径 / No input file provided
+		echo "Warn: No input file provided for config." 1>&2  # 输出到标准错误 / Output to stderr
+	elif [ ! -f "$input_file" ]; then
+		# 文件不存在 / File does not exist
+		echo "Warn: File '$input_file' does not exist." 1>&2  # 输出到标准错误 / Output to stderr
+	elif [ ! -r "$input_file" ]; then
+		# 文件不可读取 / File is not readable
+		echo "Warn: File '$input_file' is not readable." 1>&2  # 输出到标准错误 / Output to stderr
+	else
+		# 使用 awk 处理文件内容 / Using awk to process the file content
+		parsed_data=$(awk -v resolutions="$supported_resolutions" -v formats="$supported_formats" '
+		BEGIN {
+			OFS = " ";
+			split(resolutions, supported_res, " ");  # 将支持的分辨率放入数组 / Split the supported resolutions into an array
+			split(formats, supported_fmt, " ");  # 将支持的格式放入数组 / Split the supported formats into an array
+		}
+		/^[^#]/ {  # 只处理非 # 开头的行 / Process lines that do not start with #
+			fmt = $1;
+			res = $2;
+
+			# 检查格式是否在支持的格式列表中 / Check if the format is in the supported formats list
+			is_supported_fmt = 0;
+			for (i in supported_fmt) {
+				if (fmt == supported_fmt[i]) {
+					is_supported_fmt = 1;
+					break;
+				}
+			}
+			if (!is_supported_fmt) {
+				print "Unsupported format:", fmt > "/dev/stderr";  # 输出不支持的格式到标准错误 / Output unsupported format to stderr
+				next;
+			}
+
+			if (res ~ /^[0-9]+x[0-9]+$/) {  # 匹配 640x360/1280x720 这种格式 / Match the format like 640x360 or 1280x720
+				is_supported_res = 0;
+				for (i in supported_res) {
+					if (res == supported_res[i]) {
+						is_supported_res = 1;
+						break;
+					}
+				}
+				if (!is_supported_res) {
+					print "Unsupported resolution:", res > "/dev/stderr";  # 输出不支持的分辨率到标准错误 / Output unsupported resolution to stderr
+					next;
+				}
+				split(res, dims, "x");  # 将 1280x720 按 "x" 分割成宽高 / Split 1280x720 into width and height
+				w = dims[1];
+				h = dims[2];
+			} else {
+				print "Invalid resolution format:", res > "/dev/stderr";  # 输出无效的分辨率格式到标准错误 / Output invalid resolution format to stderr
+				next;
+			}
+			print fmt, w, h;  # 输出格式 fmt, w, h / Output fmt, w, h
+		}
+		' "$input_file")
+	fi
+
+	# 确保至少包含 'mjpg' 和 'yuyv' 格式 / Ensure at least one 'mjpg' and 'yuyv' format exists
+	has_mjpg=$(echo "$parsed_data" | grep -w "mjpg")
+	has_yuyv=$(echo "$parsed_data" | grep -w "yuyv")
+
+	if [ -z "$has_mjpg" ]; then
+		default_mjpg=$'\nmjpg 480x320\nmjpg 640x360\nmjpg 640x480\nmjpg 1280x720\nmjpg 1920x1080\nmjpg 2560x1440\n'
+        echo "Warn: No 'mjpg' config found, adding default: $default_mjpg" 1>&2
+		parsed_data="$parsed_data""$(echo "$default_mjpg" | sed 's/x/ /g')"
+	fi
+
+	if [ -z "$has_yuyv" ]; then
+		default_yuyv=$'\nyuyv 480x320\nyuyv 640x360\nyuyv 640x480\nyuyv 1280x720\nyuyv 1920x1080\nyuyv 2560x1440\n'
+        echo "Warn: No 'yuyv' config found, adding default: $default_yuyv" 1>&2
+		parsed_data="$parsed_data""$(echo "$default_yuyv" | sed 's/x/ /g')"
+	fi
+
+	parsed_data=$(echo "$parsed_data" | sed '/^$/d')  # 删除空行
+
+	echo "$parsed_data"  # 返回解析的数据 / Return the parsed data
+}
+
+
+
+
+##########################################################################
+# UVC
+
+CONFIGFS_PATH="/sys/kernel/config/usb_gadget/g0"
+ORIGINAL_DIR=$(pwd)  # 记录脚本启动时的目录 / Record the original working directory
+
+create_frame() {
+	# Example usage:
+	# create_frame <width> <height> <format name>
+
+	WIDTH=$1
+	HEIGHT=$2
+	FORMAT=$3
+
+	if [ "$FORMAT" == "yuyv" ]; then
+		wdir=streaming/uncompressed/u/${HEIGHT}p
+	elif [ "$FORMAT" == "mjpg" ]; then
+		wdir=streaming/mjpeg/m/${HEIGHT}p
+	else
+		echo "only support format yuyv/mjpeg!"
+		exit 1
+	fi
+
+	mkdir -p $wdir
+	echo $WIDTH > $wdir/wWidth
+	echo $HEIGHT > $wdir/wHeight
+	echo $(( $WIDTH * $HEIGHT * 2 )) > $wdir/dwMaxVideoFrameBufferSize
+	echo $(( $WIDTH * $HEIGHT * 2 * 8 * 5  )) > $wdir/dwMinBitRate
+	echo $(( $WIDTH * $HEIGHT * 2 * 8 * 60 )) > $wdir/dwMaxBitRate
+
+	cat > $wdir/dwFrameInterval <<EOF
+166666
+333333
+400000
+500000
+666666
+1000000
+2000000
+EOF
+	echo "333333" > $wdir/dwDefaultFrameInterval
+
+<< EOF
+    configure FrameRate
+    dwFrameInterfal is in 100-ns units (fps = 1/(dwFrameInterval * 10000000))
+      166666 -> 60 fps
+      333333 -> 30 fps
+      400000 -> 25 fps
+      500000 -> 20 fps
+      666666 -> 15 fps
+     1000000 -> 10 fps
+     2000000 ->  5 fps
+     5000000 ->  2 fps
+    10000000 ->  1 fps
+EOF
+}
+
+
+# 挂载 UVC ConfigFS / Mount the UVC ConfigFS
+mount_uvc_configfs() {
+	echo "Mounting UVC ConfigFS in $(pwd)"
+
+	# 创建 functions/uvc.usb0 目录 / Create the directory for uvc.usb0
+	mkdir -p functions/uvc.usb0
+	cd functions/uvc.usb0
+
+	# 在 functions/uvc.usb0 目录中创建控制头和符号链接 / Create control header and symlink it in uvc.usb0
+	mkdir -p control/header/h
+		ln -s control/header/h/ control/class/fs/
+		ln -s control/header/h/ control/class/ss/
+
+	# streaming_maxpacket sets wMaxPacketSize. Valid values are 1024/2048/3072
+	echo 1024 > streaming_maxpacket
+	# streaming_interval sets bInterval. Values range from 1..255
+	echo 1 > streaming_interval
+	# streaming_maxburst sets bMaxBurst. Valid values are 1..15
+	echo 1 > streaming_maxburst
+
+	# 在 functions/uvc.usb0 目录中创建流媒体路径 / Create streaming paths in uvc.usb0
+	mkdir -p streaming/uncompressed/u  # YUV 目录 / YUV directory
+	mkdir -p streaming/mjpeg/m         # MJPEG 目录 / MJPEG directory
+		# 执行解析并直接传递给 while 循环进行处理 / Execute parsing and directly pass to while loop for processing
+		parse_uvc_config "$1" | while read fmt w h; do
+			echo "Adding: Format: $fmt, Width: $w, Height: $h"  # 输出格式、宽和高 / Output fmt, width, and height
+			create_frame $w $h $fmt
+		done
+	mkdir -p streaming/header/h
+		# 将 YUV 和 MJPEG 目录链接到流媒体头中 / Link YUV and MJPEG to streaming header
+		ln -s streaming/uncompressed/u/ streaming/header/h/
+		ln -s streaming/mjpeg/m/ streaming/header/h/
+		# 将 header 链接到 class 中 / Link header to classes
+		ln -s streaming/header/h/ streaming/class/fs
+		ln -s streaming/header/h/ streaming/class/hs
+		ln -s streaming/header/h/ streaming/class/ss
+
+	cd ../..
+	ln -s functions/uvc.usb0 configs/c.1
+
+    echo "UVC ConfigFS mounted successfully in $(pwd)"
+}
+
+# 卸载 UVC ConfigFS / Unmount the UVC ConfigFS
+unmount_uvc_configfs() {
+	echo "Unmounting UVC ConfigFS in $(pwd)"
+
+	unlink configs/c.1/uvc.usb0
+
+	cd functions/uvc.usb0
+
+	# 删除流媒体目录 / Remove streaming directories
+	unlink streaming/class/fs/h
+	unlink streaming/class/hs/h
+	unlink streaming/class/ss/h
+
+	unlink streaming/header/h/u
+	unlink streaming/header/h/m
+	rmdir streaming/header/h
+
+	rmdir streaming/uncompressed/u/*p
+	rmdir streaming/mjpeg/m/*p
+	rmdir streaming/uncompressed/u
+	rmdir streaming/mjpeg/m
+
+	unlink control/class/fs/h
+	unlink control/class/ss/h
+	rmdir control/header/h
+
+	cd ../..
+	# 删除 functions/uvc.usb0 目录 / Remove the uvc.usb0 directory
+	rmdir functions/uvc.usb0
+
+	echo UVC ConfigFS unmounted successfully in $(pwd)
+}
+
+# 进入工作目录 / Enter the working directory
+cd "$CONFIGFS_PATH" || return 1
+
+# 处理传入的参数
+# Process the input arguments
+case "$1" in
+	"mount")
+		mount_uvc_configfs "$2"
+        ;;
+	"unmount")
+		unmount_uvc_configfs
+        ;;
+	"server")
+		if [ -z "$(fuser /etc/init.d/uvc-gadget-server.elf)" ]; then
+			(	
+				echo "Waiting for UDC start..."
+				while [ -z "$(cat /sys/kernel/config/usb_gadget/g0/UDC)" ]; do
+					echo -n "."
+					sleep 1
+				done
+				sleep 3	# necessary delay time
+				if [ -z "$(fuser /etc/init.d/uvc-gadget-server.elf)" ]; then
+					echo -e "\nServer is starting..."  # 输出选择了 server 模式 / Output that the server mode is selected
+					echo -e "===============================\n\n\n"
+					# 在这里添加你希望在 server 模式下执行的其他操作 / Add other operations you want to perform in server mode here
+					/etc/init.d/uvc-gadget-server.elf  -u /dev/$(basename /sys/class/udc/*/device/gadget/video4linux/video*)  -d -i /bin/cat_224.jpg 
+				else
+					echo -e "\nServer has started..."
+					echo -e "===============================\n\n\n"
+				fi
+			) >/tmp/uvc-gadget.log 2>&1 &
+		fi
+	;;
+	"stop_server")
+		fuser -k /etc/init.d/uvc-gadget-server.elf
+	;;
+	*)
+		echo "Usage: $0 {mount <file>|unmount|server|stop_server}"  # 提示正确的使用方式 / Prompt the correct usage
+	;;
+esac
+
+# 返回原始目录 / Return to the original directory
+cd "$ORIGINAL_DIR" || return 1

buildroot/board/cvitek/SG200X/overlay/etc/rc.local

@@ -2,7 +2,7 @@
 
 echo "HELLO WORLD"
 
-if [ -e /boot/maxicam ]
+if [ -e /boot/maixcam ]
 then
 	/maixapp/apps/launcher/launcher &
 fi

buildroot/board/cvitek/SG200X/overlay/etc/ssh/sshd_config

@@ -15,9 +15,10 @@
 #ListenAddress 0.0.0.0
 #ListenAddress ::
 
-#HostKey /etc/ssh/ssh_host_rsa_key
-#HostKey /etc/ssh/ssh_host_ecdsa_key
-#HostKey /etc/ssh/ssh_host_ed25519_key
+# some old ssh utils need rsa & ecdsa
+HostKey /etc/ssh/ssh_host_rsa_key
+HostKey /etc/ssh/ssh_host_ecdsa_key
+HostKey /etc/ssh/ssh_host_ed25519_key
 
 # Ciphers and keying
 #RekeyLimit default none

buildroot/board/cvitek/SG200X/overlay/mnt/data/sensor_cfg.ini.alpha

@@ -0,0 +1,34 @@
+[source]
+
+;type = SOURCE_USER_FE
+
+dev_num = 1
+
+; section for sensor
+
+[sensor]
+
+; sensor name
+name = GCORE_GC4653_MIPI_4M_30FPS_10BIT 
+
+bus_id = 4
+
+sns_i2c_addr = 29
+
+mipi_dev = 0
+
+lane_id = 2, 1, 0, -1, -1
+
+pn_swap = 0, 0, 0, 0, 0
+
+mclk_en = 1
+
+mclk = 0
+
+;port = 0
+
+;pin = 2
+
+;pol = 1
+
+;fps = 30

buildroot/board/cvitek/SG200X/overlay/mnt/data/sensor_cfg.ini.beta

@@ -0,0 +1,34 @@
+[source]
+
+;type = SOURCE_USER_FE
+
+dev_num = 1
+
+; section for sensor
+
+[sensor]
+
+; sensor name
+name = GCORE_GC4653_MIPI_4M_30FPS_10BIT
+
+bus_id = 4
+
+sns_i2c_addr = 29
+
+mipi_dev = 0
+
+lane_id = 4, 3, 2, -1, -1
+
+pn_swap = 0, 0, 0, 0, 0
+
+mclk_en = 1
+
+mclk = 1
+
+;port = 0
+
+;pin = 2
+
+;pol = 1
+
+;fps = 30

buildroot/board/cvitek/SG200X/overlay/usr/share/udhcpc/default.script

@@ -4,7 +4,13 @@
 
 [ -z "$1" ] && echo "Error: should be called from udhcpc" && exit 1
 
+ACTION="$1"
+
 RESOLV_CONF="/etc/resolv.conf"
+if [ -e /boot/resolv.conf ]
+then
+	RESOLV_CONF="/etc/resolv.conf.dhcp"
+fi
 [ -e $RESOLV_CONF ] || touch $RESOLV_CONF
 [ -n "$broadcast" ] && BROADCAST="broadcast $broadcast"
 [ -n "$subnet" ] && NETMASK="netmask $subnet"
@@ -18,7 +24,7 @@ fi
 wait_for_ipv6_default_route() {
 	printf "Waiting for IPv6 default route to appear"
 	while [ $IF_WAIT_DELAY -gt 0 ]; do
-		if [ -z "$(ip -6 route list | grep default)" ]; then
+		if ip -6 route list | grep -q default; then
 			printf "\n"
 			return
 		fi
@@ -29,7 +35,7 @@ wait_for_ipv6_default_route() {
 	printf " timeout!\n"
 }
 
-case "$1" in
+case "$ACTION" in
 	deconfig)
 		/sbin/ifconfig $interface up
 		/sbin/ifconfig $interface 0.0.0.0
@@ -115,7 +121,7 @@ esac
 HOOK_DIR="$0.d"
 for hook in "${HOOK_DIR}/"*; do
     [ -f "${hook}" -a -x "${hook}" ] || continue
-    "${hook}" "${@}"
+    "${hook}" "$ACTION"
 done
 
 exit 0

buildroot/configs/cvitek_SG200X_32bit_defconfig

@@ -0,0 +1,403 @@
+BR2_arm=y
+BR2_cortex_a53=y
+BR2_ARM_EABIHF=y
+BR2_ARM_FPU_FP_ARMV8=y
+
+BR2_TOOLCHAIN_EXTERNAL=y
+BR2_TOOLCHAIN_EXTERNAL_ARM_ARM=y
+BR2_TOOLCHAIN_EXTERNAL_DOWNLOAD=y
+BR2_TOOLCHAIN_EXTERNAL_GDB_SERVER_COPY=y
+BR2_OPTIMIZE_2=y
+
+BR2_CCACHE=y
+BR2_REPRODUCIBLE=y
+BR2_PER_PACKAGE_DIRECTORIES=y
+
+BR2_TARGET_GENERIC_HOSTNAME="licheea53nano"
+BR2_TARGET_GENERIC_ISSUE="Welcome to Linux"
+BR2_TARGET_GENERIC_ROOT_PASSWD="root"
+
+BR2_PACKAGE_AIC8800_SDIO_FIRMWARE=y
+
+BR2_INIT_SYSV=y
+BR2_ROOTFS_MERGED_USR=y
+BR2_ENABLE_LOCALE_WHITELIST="C en_US en_US.utf8"
+BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_EUDEV=y
+BR2_PACKAGE_BUSYBOX_SHOW_OTHERS=y
+BR2_PACKAGE_KMOD=y
+# dont rename network card,
+# BR2_PACKAGE_EUDEV_RULES_GEN is not set
+BR2_PACKAGE_EUDEV_ENABLE_HWDB=y
+BR2_PACKAGE_BLUEZ5_UTILS=y
+BR2_PACKAGE_BLUEZ5_UTILS_CLIENT=y
+BR2_PACKAGE_BLUEZ5_UTILS_TOOLS=y
+BR2_PACKAGE_BLUEZ5_UTILS_DEPRECATED=y
+BR2_PACKAGE_BLUEZ5_UTILS_PLUGINS_HID=y
+BR2_PACKAGE_BLUEZ5_UTILS_PLUGINS_NETWORK=y
+BR2_PACKAGE_BLUEZ5_UTILS_TOOLS_HID2HCI=y
+BR2_PACKAGE_BLUEZ5_UTILS_MONITOR=y
+BR2_PACKAGE_BLUEZ_ALSA=y
+BR2_PACKAGE_BLUEZ_ALSA_RFCOMM=y
+BR2_PACKAGE_BLUEZ_ALSA_HCITOP=y
+BR2_PACKAGE_NTP=y
+BR2_PACKAGE_NTP_NTPD=y
+BR2_PACKAGE_NTP_NTPDATE=y
+BR2_PACKAGE_MACCHANGER=y
+BR2_PACKAGE_AVAHI=y
+BR2_PACKAGE_AVAHI_AUTOIPD=y
+# avahi mdns is buggy
+# BR2_PACKAGE_AVAHI_DAEMON is not set
+# BR2_PACKAGE_AVAHI_LIBDNSSD_COMPATIBILITY is not set
+# BR2_PACKAGE_AVAHI_DEFAULT_SERVICES is not set
+BR2_PACKAGE_MDNSD=y
+BR2_PACKAGE_MDNSD_MQUERY=y
+BR2_PACKAGE_MDNSD_HTTP_SERVICE=y
+BR2_PACKAGE_MDNSD_SSH_SERVICE=y
+BR2_PACKAGE_WIRELESS_TOOLS=y
+BR2_PACKAGE_WIRELESS_TOOLS_IFRENAME=y
+BR2_PACKAGE_WIRELESS_TOOLS_IWCONFIG=y
+BR2_PACKAGE_WIRELESS_TOOLS_LIB=y
+BR2_PACKAGE_AIRCRACK_NG=y
+BR2_PACKAGE_UTIL_LINUX_RFKILL=y
+BR2_PACKAGE_IPERF3=y
+BR2_PACKAGE_IPMITOOL=y
+BR2_PACKAGE_IPMITOOL_PEN_REG_URI=y
+BR2_PACKAGE_IPMITOOL_LANPLUS=y
+BR2_PACKAGE_IPMITOOL_USB=y
+BR2_PACKAGE_IPMITOOL_IPMIEVD=y
+BR2_PACKAGE_IPMITOOL_IPMISHELL=y
+BR2_PACKAGE_ETHTOOL=y
+BR2_PACKAGE_DNSMASQ=y
+BR2_PACKAGE_DNSMASQ_DHCP=y
+BR2_PACKAGE_RSYNC=y
+BR2_PACKAGE_SOCAT=y
+BR2_PACKAGE_TINC=y
+BR2_PACKAGE_WIRELESS_REGDB=y
+BR2_PACKAGE_MOSH=y
+BR2_PACKAGE_LRZSZ=y
+BR2_PACKAGE_IW=y
+# BR2_PACKAGE_WIREGUARD=y
+BR2_PACKAGE_WIREGUARD_TOOLS=y
+# BR2_PACKAGE_WIREGUARD_LINUX_COMPAT=y
+BR2_PACKAGE_WPA_SUPPLICANT=y
+BR2_PACKAGE_WPA_SUPPLICANT_NL80211=y
+BR2_PACKAGE_WPA_SUPPLICANT_WPA3=y
+BR2_PACKAGE_WPA_SUPPLICANT_AUTOSCAN=y
+BR2_PACKAGE_WPA_SUPPLICANT_AP_SUPPORT=y
+BR2_PACKAGE_WPA_SUPPLICANT_OVERRIDES=y
+BR2_PACKAGE_WPA_SUPPLICANT_WIFI_DISPLAY=y
+BR2_PACKAGE_WPA_SUPPLICANT_MESH_NETWORKING=y
+BR2_PACKAGE_WPA_SUPPLICANT_IBSS_RSN=y
+BR2_PACKAGE_WPA_SUPPLICANT_WEXT=y
+BR2_PACKAGE_WPA_SUPPLICANT_EAP=y
+BR2_PACKAGE_WPA_SUPPLICANT_HOTSPOT=y
+BR2_PACKAGE_WPA_SUPPLICANT_DEBUG_SYSLOG=y
+BR2_PACKAGE_WPA_SUPPLICANT_WPS=y
+BR2_PACKAGE_WPA_SUPPLICANT_CLI=y
+BR2_PACKAGE_WPA_SUPPLICANT_WPA_CLIENT_SO=y
+BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y
+BR2_PACKAGE_WPA_SUPPLICANT_CTRL_IFACE=y
+BR2_PACKAGE_WPA_SUPPLICANT_DBUS=y
+BR2_PACKAGE_HOSTAPD=y
+BR2_PACKAGE_HOSTAPD_DRIVER_HOSTAP=y
+BR2_PACKAGE_HOSTAPD_DRIVER_NL80211=y
+BR2_PACKAGE_HOSTAPD_ACS=y
+BR2_PACKAGE_HOSTAPD_EAP=y
+BR2_PACKAGE_HOSTAPD_WPS=y
+BR2_PACKAGE_HOSTAPD_WPA3=y
+# BR2_PACKAGE_HOSTAPD_VLAN is not set
+BR2_PACKAGE_OPENSSH=y
+BR2_PACKAGE_OPENSSH_CLIENT=y
+BR2_PACKAGE_OPENSSH_SERVER=y
+BR2_PACKAGE_OPENSSH_KEY_UTILS=y
+BR2_PACKAGE_HAVEGED=y
+BR2_PACKAGE_LIBOPENSSL_BIN=y
+BR2_PACKAGE_LIBOPENSSL_ENGINES=y
+BR2_PACKAGE_PARTED=y
+BR2_PACKAGE_MEMTESTER=y
+BR2_PACKAGE_CACHE_CALIBRATOR=y
+BR2_PACKAGE_DHRYSTONE=y
+BR2_PACKAGE_RAMSPEED=y
+BR2_PACKAGE_SPIDEV_TEST=y
+BR2_PACKAGE_STRESS_NG=y
+BR2_PACKAGE_STRACE=y
+BR2_PACKAGE_VMTOUCH=y
+BR2_PACKAGE_ALSA_UTILS=y
+BR2_PACKAGE_ALSA_UTILS_ALSACTL=y
+BR2_PACKAGE_ALSA_UTILS_ALSAMIXER=y
+BR2_PACKAGE_ALSA_UTILS_APLAY=y
+BR2_PACKAGE_MPG123=y
+BR2_PACKAGE_BZIP2=y
+BR2_PACKAGE_LRZIP=y
+BR2_PACKAGE_LZIP=y
+BR2_PACKAGE_P7ZIP=y
+BR2_PACKAGE_PIGZ=y
+BR2_PACKAGE_PIXZ=y
+BR2_PACKAGE_UNRAR=y
+BR2_PACKAGE_UNZIP=y
+BR2_PACKAGE_ZIP=y
+BR2_PACKAGE_ZSTD=y
+BR2_PACKAGE_LZOP=y
+BR2_PACKAGE_BROTLI=y
+BR2_PACKAGE_LIBZIP=y
+BR2_PACKAGE_LZ4_PROGS=y
+BR2_PACKAGE_SZIP=y
+BR2_PACKAGE_CA_CERTIFICATES=y
+BR2_PACKAGE_EVTEST=y
+BR2_PACKAGE_FILE=y
+BR2_PACKAGE_EMPTY=y
+BR2_PACKAGE_EXFATPROGS=y
+BR2_PACKAGE_E2FSPROGS=y
+BR2_PACKAGE_E2FSPROGS_RESIZE2FS=y
+BR2_PACKAGE_TMUX=y
+BR2_PACKAGE_HTOP=y
+BR2_PACKAGE_LIBCURL=y
+BR2_PACKAGE_LIBCURL_CURL=y
+BR2_PACKAGE_LIBCURL_VERBOSE=y
+BR2_PACKAGE_LIBCURL_PROXY_SUPPORT=y
+BR2_PACKAGE_LIBCURL_COOKIES_SUPPORT=y
+BR2_PACKAGE_LIBCURL_WEBSOCKETS_SUPPORT=y
+BR2_PACKAGE_LIBCURL_EXTRA_PROTOCOLS_FEATURES=y
+BR2_PACKAGE_LIBCURL_OPENSSL=y
+BR2_PACKAGE_LIBWEBSOCKETS=y
+BR2_PACKAGE_WATCHDOG=y
+BR2_PACKAGE_SQUASHFS=y
+BR2_PACKAGE_SQUASHFS_GZIP=y
+BR2_PACKAGE_SQUASHFS_LZ4=y
+BR2_PACKAGE_SQUASHFS_LZMA=y
+BR2_PACKAGE_SQUASHFS_LZO=y
+BR2_PACKAGE_SQUASHFS_XZ=y
+BR2_PACKAGE_SQUASHFS_ZSTD=y
+BR2_PACKAGE_LCDTEST=y
+BR2_PACKAGE_ASCII_INVADERS=y
+BR2_PACKAGE_GNUCHESS=y
+BR2_PACKAGE_SL=y
+BR2_PACKAGE_XORCURSES=y
+BR2_PACKAGE_INPUT_EVENT_DAEMON=y
+BR2_PACKAGE_BLUEZ_TOOLS=y
+BR2_PACKAGE_TPUDEMO_SG200X=y
+BR2_PACKAGE_SG2002_CODEC_FIRMWARE=y
+BR2_PACKAGE_TCPDUMP=y
+BR2_PACKAGE_SSDP_RESPONDER=y
+BR2_PACKAGE_PPPD=y
+BR2_PACKAGE_NFTABLES=y
+BR2_PACKAGE_BIND=y
+BR2_PACKAGE_SYSSTAT=y
+BR2_PACKAGE_TRACEROUTE=y
+BR2_PACKAGE_IPUTILS=y
+BR2_PACKAGE_IPROUTE2=y
+BR2_PACKAGE_IPTABLES=y
+BR2_PACKAGE_IPTABLES_NFTABLES=y
+BR2_PACKAGE_NCURSES_WCHAR=y
+BR2_PACKAGE_LIBEDIT=y
+# BR2_PACKAGE_NGINX=y
+# BR2_PACKAGE_NGINX_HTTP=y
+# BR2_PACKAGE_NGINX_HTTP_DAV_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_MP4_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_FLV_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_GUNZIP_MODULE=y
+# BR2_PACKAGE_NGINX_STREAM=y
+# BR2_PACKAGE_NGINX_SELECT_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_FASTCGI_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_UWSGI_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_SCGI_MODULE=y
+BR2_PACKAGE_RTC_TOOLS=y
+BR2_PACKAGE_PICOCOM=y
+BR2_PACKAGE_FBGRAB=y
+BR2_PACKAGE_MHZ=y
+BR2_PACKAGE_SETSERIAL=y
+BR2_PACKAGE_UBOOT_TOOLS=y
+BR2_PACKAGE_UBOOT_TOOLS_FIT_SUPPORT=y
+BR2_PACKAGE_UBOOT_TOOLS_MKIMAGE=y
+BR2_PACKAGE_UBOOT_TOOLS_DUMPIMAGE=y
+
+# if your sdnand is small, you can delete some package
+
+BR2_PACKAGE_IMAGEMAGICK=y
+BR2_PACKAGE_OCRAD=y
+BR2_PACKAGE_SDL=y
+BR2_PACKAGE_SDL_FBCON=y
+BR2_PACKAGE_SDL_GFX=y
+BR2_PACKAGE_SDL_IMAGE=y
+BR2_PACKAGE_SDL_IMAGE_BMP=y
+BR2_PACKAGE_SDL_IMAGE_GIF=y
+BR2_PACKAGE_SDL_IMAGE_JPEG=y
+BR2_PACKAGE_SDL_IMAGE_PNG=y
+BR2_PACKAGE_SDL_IMAGE_WEBP=y
+BR2_PACKAGE_SDL_MIXER=y
+BR2_PACKAGE_SDL_NET=y
+BR2_PACKAGE_SDL_SOUND=y
+BR2_PACKAGE_SDL_SOUND_PLAYSOUND=y
+BR2_PACKAGE_LBREAKOUT2=y
+BR2_PACKAGE_LBREAKOUT2_AUDIO=y
+BR2_PACKAGE_LBREAKOUT2_NET=y
+BR2_PACKAGE_LTRIS=y
+BR2_PACKAGE_LTRIS_AUDIO=y
+BR2_PACKAGE_PRBOOM=y
+BR2_PACKAGE_DOOM_WAD=y
+BR2_PACKAGE_TCL=y
+# BR2_PACKAGE_TCL_SHLIB_ONLY is not set
+# BR2_PACKAGE_TCL_DEL_ENCODINGS is not set
+BR2_PACKAGE_EXPECT=y
+BR2_PACKAGE_TCLLIB=y
+BR2_PACKAGE_OPENCV4=y
+BR2_PACKAGE_OPENCV4_LIB_CALIB3D=y
+BR2_PACKAGE_OPENCV4_LIB_DNN=y
+BR2_PACKAGE_OPENCV4_LIB_HIGHGUI=y
+BR2_PACKAGE_OPENCV4_LIB_OBJDETECT=y
+BR2_PACKAGE_OPENCV4_LIB_PHOTO=y
+BR2_PACKAGE_OPENCV4_LIB_SHAPE=y
+BR2_PACKAGE_OPENCV4_LIB_STITCHING=y
+BR2_PACKAGE_OPENCV4_LIB_SUPERRES=y
+BR2_PACKAGE_OPENCV4_LIB_TS=y
+BR2_PACKAGE_OPENCV4_LIB_VIDEOSTAB=y
+BR2_PACKAGE_OPENCV4_BUILD_TESTS=y
+BR2_PACKAGE_OPENCV4_BUILD_PERF_TESTS=y
+BR2_PACKAGE_OPENCV4_WITH_FFMPEG=y
+BR2_PACKAGE_OPENCV4_WITH_JPEG=y
+BR2_PACKAGE_OPENCV4_WITH_PNG=y
+BR2_PACKAGE_OPENCV4_WITH_TBB=y
+BR2_PACKAGE_OPENCV4_WITH_TIFF=y
+BR2_PACKAGE_OPENCV4_WITH_V4L=y
+BR2_PACKAGE_OPENCV4_WITH_WEBP=y
+BR2_PACKAGE_OPENCV4_INSTALL_DATA=y
+BR2_PACKAGE_LIBQRENCODE=y
+BR2_PACKAGE_LIBQRENCODE_TOOLS=y
+BR2_PACKAGE_FFMPEG=y
+BR2_PACKAGE_FFMPEG_FFMPEG=y
+BR2_PACKAGE_FFMPEG_FFPROBE=y
+BR2_PACKAGE_FFMPEG_GPL=y
+BR2_PACKAGE_FFMPEG_NONFREE=y
+BR2_PACKAGE_FFMPEG_POSTPROC=y
+BR2_PACKAGE_MULTICAT=y
+BR2_PACKAGE_WQY_ZENHEI=y
+BR2_PACKAGE_DEJAVU=y
+BR2_PACKAGE_GNUPLOT=y
+BR2_PACKAGE_TESSERACT_OCR=y
+BR2_PACKAGE_TESSERACT_OCR_LANG_ENG=y
+BR2_PACKAGE_TESSERACT_OCR_LANG_CHI_SIM=y
+BR2_PACKAGE_TESSERACT_OCR_LANG_CHI_TRA=y
+BR2_PACKAGE_QT5=y
+BR2_PACKAGE_QT5BASE_SQLITE_SYSTEM=y
+BR2_PACKAGE_QT5BASE_GUI=y
+BR2_PACKAGE_QT5BASE_LINUXFB=y
+BR2_PACKAGE_QT5BASE_WIDGETS=y
+BR2_PACKAGE_QT5BASE_DEFAULT_QPA="linuxfb"
+BR2_PACKAGE_QT5BASE_FONTCONFIG=y
+BR2_PACKAGE_QT5BASE_GIF=y
+BR2_PACKAGE_QT5BASE_PNG=y
+BR2_PACKAGE_QT5BASE_JPEG=y
+BR2_PACKAGE_QT5BASE_SYSLOG=y
+BR2_PACKAGE_QT5BASE_DBUS=y
+BR2_PACKAGE_QT5BASE_TSLIB=y
+BR2_PACKAGE_QT5BASE_EXAMPLES=y
+BR2_PACKAGE_QT5BASE_CONCURRENT=y
+BR2_PACKAGE_QT5CONNECTIVITY=y
+BR2_PACKAGE_QT5IMAGEFORMATS=y
+BR2_PACKAGE_QT5MULTIMEDIA=y
+BR2_PACKAGE_QT5SENSORS=y
+BR2_PACKAGE_QT5SERIALBUS=y
+BR2_PACKAGE_QT5CHARTS=y
+BR2_PACKAGE_QT5COAP=y
+BR2_PACKAGE_QT5ENGINIO=y
+BR2_PACKAGE_QT5KNX=y
+BR2_PACKAGE_QT5LOCATION=y
+BR2_PACKAGE_QT5MQTT=y
+BR2_PACKAGE_QT5OPCUA=y
+BR2_PACKAGE_QT5REMOTEOBJECTS=y
+BR2_PACKAGE_QT5SPEECH=y
+BR2_PACKAGE_QT5SVG=y
+BR2_PACKAGE_QT5WEBSOCKETS=y
+BR2_PACKAGE_QT5WEBCHANNEL=y
+BR2_PACKAGE_QEXTSERIALPORT=y
+BR2_PACKAGE_QT5X11EXTRAS=y
+BR2_PACKAGE_QT5XMLPATTERNS=y
+BR2_PACKAGE_QT5BASE_MYSQL=y
+BR2_PACKAGE_QJSON=y
+BR2_PACKAGE_QUAZIP=y
+BR2_PACKAGE_PYTHON3=y
+BR2_PACKAGE_PYTHON3_2TO3=y
+BR2_PACKAGE_PYTHON3_BZIP2=y
+BR2_PACKAGE_PYTHON3_CODECSCJK=y
+BR2_PACKAGE_PYTHON3_CURSES=y
+BR2_PACKAGE_PYTHON3_SSL=y
+BR2_PACKAGE_PYTHON3_UNICODEDATA=y
+BR2_PACKAGE_PYTHON3_SQLITE=y
+BR2_PACKAGE_PYTHON3_XZ=y
+BR2_PACKAGE_PYTHON3_ZLIB=y
+BR2_PACKAGE_PYTHON_NUMPY=y
+BR2_PACKAGE_OPENCV4_LIB_PYTHON=y
+BR2_PACKAGE_OPENCV4_WITH_QT5=y
+BR2_PACKAGE_PYTHON_BSDIFF4=y
+BR2_PACKAGE_PYTHON_BEAUTIFULSOUP4=y
+BR2_PACKAGE_PYTHON_CFFI=y
+BR2_PACKAGE_PYTHON_CRC16=y
+BR2_PACKAGE_PYTHON_DBUS_FAST=y
+BR2_PACKAGE_PYTHON_DATEUTIL=y
+BR2_PACKAGE_PYTHON_DBUS_NEXT=y
+BR2_PACKAGE_PYTHON_DJANGO=y
+BR2_PACKAGE_PYTHON_FLASK=y
+BR2_PACKAGE_PYTHON_EVDEV=y
+BR2_PACKAGE_PYTHON_FLASK_BABEL=y
+BR2_PACKAGE_PYTHON_FLASK_CORS=y
+BR2_PACKAGE_PYTHON_FLASK_JSONRPC=y
+BR2_PACKAGE_PYTHON_FLASK_LOGIN=y
+BR2_PACKAGE_PYTHON_FLASK_SMOREST=y
+BR2_PACKAGE_PYTHON_FLASK_SQLALCHEMY=y
+BR2_PACKAGE_PYTHON_FLASK_WTF=y
+BR2_PACKAGE_PYTHON_HWDATA=y
+BR2_PACKAGE_PYTHON_PIP=y
+BR2_PACKAGE_PYTHON_PEXPECT=y
+BR2_PACKAGE_PYTHON_PSUTIL=y
+BR2_PACKAGE_PYTHON_PYAES=y
+BR2_PACKAGE_PYTHON_PYALSA=y
+BR2_PACKAGE_PYTHON_PYDEVMEM=y
+BR2_PACKAGE_PYTHON_PYUSB=y
+BR2_PACKAGE_PYTHON_REQUESTS=y
+BR2_PACKAGE_PYTHON_REQUESTS_OAUTHLIB=y
+BR2_PACKAGE_PYTHON_REQUESTS_TOOLBELT=y
+BR2_PACKAGE_PYTHON_SERIAL=y
+BR2_PACKAGE_PYTHON_SERIAL_ASYNCIO=y
+BR2_PACKAGE_PYTHON_WEBSOCKETS=y
+BR2_PACKAGE_PYTHON_WEBSOCKET_CLIENT=y
+BR2_PACKAGE_PYTHON_XMODEM=y
+BR2_PACKAGE_PYTHON3_PY_PYC=y
+BR2_PACKAGE_PYTHON_PYQT5=y
+BR2_PACKAGE_PYTHON_PYQRCODE=y
+BR2_PACKAGE_PYTHON_PYLIBFDT=y
+BR2_PACKAGE_PYTHON3_READLINE=y
+BR2_PACKAGE_PYTHON_JEDI=y
+BR2_PACKAGE_PYTHON_LIBUSB1=y
+BR2_PACKAGE_PYTHON_LXML=y
+BR2_PACKAGE_PYTHON_MARKDOWN=y
+BR2_PACKAGE_PYTHON_MSGPACK=y
+BR2_PACKAGE_PYTHON_PERIPHERY=y
+BR2_PACKAGE_PYTHON_PILLOW=y
+BR2_PACKAGE_PYTHON_POSIX_IPC=y
+BR2_PACKAGE_PYTHON_PROTOBUF=y
+BR2_PACKAGE_PYTHON_PYGAME=y
+BR2_PACKAGE_PYTHON_PYGAME_IMAGE=y
+BR2_PACKAGE_PYTHON_PYGAME_EXAMPLES=y
+BR2_PACKAGE_PYTHON_PYGAME_FONT=y
+BR2_PACKAGE_PYTHON_PYGAME_MIXER=y
+BR2_PACKAGE_PYTHON_PYUDEV=y
+BR2_PACKAGE_PYTHON_PYYAML=y
+BR2_PACKAGE_PYTHON_QRCODE=y
+BR2_PACKAGE_PYTHON_QRCODE_PIL=y
+BR2_PACKAGE_PYTHON_INTELHEX=y
+
+BR2_PACKAGE_VIM=y
+BR2_PACKAGE_VIM_RUNTIME=y
+
+BR2_PACKAGE_AXP2101=y
+
+BR2_TARGET_ROOTFS_EXT2=y
+BR2_TARGET_ROOTFS_EXT2_4=y
+BR2_TARGET_ROOTFS_EXT2_SIZE="1100M"
+
+BR2_ROOTFS_OVERLAY="$(TOPDIR)/board/cvitek/SG200X/overlay"
+BR2_PACKAGE_BUSYBOX_CONFIG_FRAGMENT_FILES="$(TOPDIR)/board/cvitek/SG200X/busybox-extra.config"
+
+BR2_TARGET_TZ_INFO=y
+BR2_TARGET_TZ_ZONELIST="default"
+BR2_TARGET_LOCALTIME="Etc/UTC"

buildroot/configs/cvitek_SG200X_musl_riscv64_defconfig

@@ -47,7 +47,8 @@ BR2_ENABLE_LOCALE_WHITELIST="C en_US en_US.utf8"
 BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_EUDEV=y
 BR2_PACKAGE_BUSYBOX_SHOW_OTHERS=y
 BR2_PACKAGE_KMOD=y
-BR2_PACKAGE_EUDEV_RULES_GEN=y
+# dont rename network card,
+# BR2_PACKAGE_EUDEV_RULES_GEN is not set
 BR2_PACKAGE_EUDEV_ENABLE_HWDB=y
 BR2_PACKAGE_BLUEZ5_UTILS=y
 BR2_PACKAGE_BLUEZ5_UTILS_CLIENT=y
@@ -65,10 +66,14 @@ BR2_PACKAGE_NTP_NTPD=y
 BR2_PACKAGE_NTP_NTPDATE=y
 BR2_PACKAGE_MACCHANGER=y
 BR2_PACKAGE_AVAHI=y
-BR2_PACKAGE_AVAHI_AUTOIPD=y
+# BR2_PACKAGE_AVAHI_AUTOIPD is not set
 BR2_PACKAGE_AVAHI_DAEMON=y
-BR2_PACKAGE_AVAHI_LIBDNSSD_COMPATIBILITY=y
+# BR2_PACKAGE_AVAHI_LIBDNSSD_COMPATIBILITY is not set
 BR2_PACKAGE_AVAHI_DEFAULT_SERVICES=y
+# BR2_PACKAGE_MDNSD is not set
+# BR2_PACKAGE_MDNSD_MQUERY is not set
+# BR2_PACKAGE_MDNSD_HTTP_SERVICE is not set
+# BR2_PACKAGE_MDNSD_SSH_SERVICE is not set
 BR2_PACKAGE_WIRELESS_TOOLS=y
 BR2_PACKAGE_WIRELESS_TOOLS_IFRENAME=y
 BR2_PACKAGE_WIRELESS_TOOLS_IWCONFIG=y
@@ -76,6 +81,12 @@ BR2_PACKAGE_WIRELESS_TOOLS_LIB=y
 BR2_PACKAGE_AIRCRACK_NG=y
 BR2_PACKAGE_UTIL_LINUX_RFKILL=y
 BR2_PACKAGE_IPERF3=y
+BR2_PACKAGE_IPMITOOL=y
+BR2_PACKAGE_IPMITOOL_PEN_REG_URI=y
+BR2_PACKAGE_IPMITOOL_LANPLUS=y
+BR2_PACKAGE_IPMITOOL_USB=y
+BR2_PACKAGE_IPMITOOL_IPMIEVD=y
+BR2_PACKAGE_IPMITOOL_IPMISHELL=y
 BR2_PACKAGE_ETHTOOL=y
 BR2_PACKAGE_DNSMASQ=y
 BR2_PACKAGE_DNSMASQ_DHCP=y
@@ -86,7 +97,11 @@ BR2_PACKAGE_WIRELESS_REGDB=y
 BR2_PACKAGE_MOSH=y
 BR2_PACKAGE_LRZSZ=y
 BR2_PACKAGE_IW=y
+BR2_PACKAGE_NETCAT=y
+BR2_PACKAGE_MTR=y
+# BR2_PACKAGE_WIREGUARD=y
 BR2_PACKAGE_WIREGUARD_TOOLS=y
+# BR2_PACKAGE_WIREGUARD_LINUX_COMPAT=y
 BR2_PACKAGE_WPA_SUPPLICANT=y
 BR2_PACKAGE_WPA_SUPPLICANT_NL80211=y
 BR2_PACKAGE_WPA_SUPPLICANT_WPA3=y
@@ -125,6 +140,7 @@ BR2_PACKAGE_PARTED=y
 BR2_PACKAGE_MEMTESTER=y
 BR2_PACKAGE_CACHE_CALIBRATOR=y
 BR2_PACKAGE_DHRYSTONE=y
+BR2_PACKAGE_COREMARK=y
 BR2_PACKAGE_RAMSPEED=y
 BR2_PACKAGE_SPIDEV_TEST=y
 BR2_PACKAGE_STRESS_NG=y
@@ -134,6 +150,7 @@ BR2_PACKAGE_ALSA_UTILS=y
 BR2_PACKAGE_ALSA_UTILS_ALSACTL=y
 BR2_PACKAGE_ALSA_UTILS_ALSAMIXER=y
 BR2_PACKAGE_ALSA_UTILS_APLAY=y
+BR2_PACKAGE_ALSA_UTILS_AMIXER=y
 BR2_PACKAGE_MPG123=y
 BR2_PACKAGE_BZIP2=y
 BR2_PACKAGE_LRZIP=y
@@ -152,8 +169,10 @@ BR2_PACKAGE_LZ4_PROGS=y
 BR2_PACKAGE_SZIP=y
 BR2_PACKAGE_CA_CERTIFICATES=y
 BR2_PACKAGE_EVTEST=y
+BR2_PACKAGE_BASH=y
 BR2_PACKAGE_FILE=y
 BR2_PACKAGE_EMPTY=y
+BR2_PACKAGE_EXFATPROGS=y
 BR2_PACKAGE_E2FSPROGS=y
 BR2_PACKAGE_E2FSPROGS_RESIZE2FS=y
 BR2_PACKAGE_TMUX=y
@@ -188,21 +207,14 @@ BR2_PACKAGE_TCPDUMP=y
 BR2_PACKAGE_SSDP_RESPONDER=y
 BR2_PACKAGE_PPPD=y
 BR2_PACKAGE_NFTABLES=y
+BR2_PACKAGE_BIND=y
+BR2_PACKAGE_SYSSTAT=y
+BR2_PACKAGE_TRACEROUTE=y
+BR2_PACKAGE_IPUTILS=y
+BR2_PACKAGE_IPROUTE2=y
 BR2_PACKAGE_IPTABLES=y
 BR2_PACKAGE_IPTABLES_NFTABLES=y
 BR2_PACKAGE_NCURSES_WCHAR=y
-BR2_PACKAGE_LIBEDIT=y
-BR2_PACKAGE_NGINX=y
-BR2_PACKAGE_NGINX_HTTP=y
-BR2_PACKAGE_NGINX_HTTP_DAV_MODULE=y
-BR2_PACKAGE_NGINX_HTTP_MP4_MODULE=y
-BR2_PACKAGE_NGINX_HTTP_FLV_MODULE=y
-BR2_PACKAGE_NGINX_HTTP_GUNZIP_MODULE=y
-BR2_PACKAGE_NGINX_STREAM=y
-BR2_PACKAGE_NGINX_SELECT_MODULE=y
-BR2_PACKAGE_NGINX_HTTP_FASTCGI_MODULE=y
-BR2_PACKAGE_NGINX_HTTP_UWSGI_MODULE=y
-BR2_PACKAGE_NGINX_HTTP_SCGI_MODULE=y
 BR2_PACKAGE_RTC_TOOLS=y
 BR2_PACKAGE_PICOCOM=y
 BR2_PACKAGE_FBGRAB=y
@@ -214,29 +226,28 @@ BR2_PACKAGE_UBOOT_TOOLS_MKIMAGE=y
 BR2_PACKAGE_UBOOT_TOOLS_DUMPIMAGE=y
 
 # if your sdnand is small, you can delete some package
-
-BR2_PACKAGE_IMAGEMAGICK=y
-BR2_PACKAGE_OCRAD=y
-BR2_PACKAGE_SDL=y
-BR2_PACKAGE_SDL_FBCON=y
-BR2_PACKAGE_SDL_GFX=y
-BR2_PACKAGE_SDL_IMAGE=y
-BR2_PACKAGE_SDL_IMAGE_BMP=y
-BR2_PACKAGE_SDL_IMAGE_GIF=y
-BR2_PACKAGE_SDL_IMAGE_JPEG=y
-BR2_PACKAGE_SDL_IMAGE_PNG=y
-BR2_PACKAGE_SDL_IMAGE_WEBP=y
-BR2_PACKAGE_SDL_MIXER=y
-BR2_PACKAGE_SDL_NET=y
-BR2_PACKAGE_SDL_SOUND=y
-BR2_PACKAGE_SDL_SOUND_PLAYSOUND=y
-BR2_PACKAGE_LBREAKOUT2=y
-BR2_PACKAGE_LBREAKOUT2_AUDIO=y
-BR2_PACKAGE_LBREAKOUT2_NET=y
-BR2_PACKAGE_LTRIS=y
-BR2_PACKAGE_LTRIS_AUDIO=y
-BR2_PACKAGE_PRBOOM=y
-BR2_PACKAGE_DOOM_WAD=y
+# BR2_PACKAGE_IMAGEMAGICK is not set
+# BR2_PACKAGE_OCRAD is not set
+# BR2_PACKAGE_SDL is not set
+# BR2_PACKAGE_SDL_FBCON is not set
+# BR2_PACKAGE_SDL_GFX is not set
+# BR2_PACKAGE_SDL_IMAGE is not set
+# BR2_PACKAGE_SDL_IMAGE_BMP is not set
+# BR2_PACKAGE_SDL_IMAGE_GIF is not set
+# BR2_PACKAGE_SDL_IMAGE_JPEG is not set
+# BR2_PACKAGE_SDL_IMAGE_PNG is not set
+# BR2_PACKAGE_SDL_IMAGE_WEBP is not set
+# BR2_PACKAGE_SDL_MIXER is not set
+# BR2_PACKAGE_SDL_NET is not set
+# BR2_PACKAGE_SDL_SOUND is not set
+# BR2_PACKAGE_SDL_SOUND_PLAYSOUND is not set
+# BR2_PACKAGE_LBREAKOUT2 is not set
+# BR2_PACKAGE_LBREAKOUT2_AUDIO is not set
+# BR2_PACKAGE_LBREAKOUT2_NET is not set
+# BR2_PACKAGE_LTRIS is not set
+# BR2_PACKAGE_LTRIS_AUDIO is not set
+# BR2_PACKAGE_PRBOOM is not set
+# BR2_PACKAGE_DOOM_WAD is not set
 BR2_PACKAGE_TCL=y
 # BR2_PACKAGE_TCL_SHLIB_ONLY is not set
 # BR2_PACKAGE_TCL_DEL_ENCODINGS is not set
@@ -271,65 +282,69 @@ BR2_PACKAGE_FFMPEG_FFPROBE=y
 BR2_PACKAGE_FFMPEG_GPL=y
 BR2_PACKAGE_FFMPEG_NONFREE=y
 BR2_PACKAGE_FFMPEG_POSTPROC=y
-BR2_PACKAGE_MULTICAT=y
-BR2_PACKAGE_WQY_ZENHEI=y
-BR2_PACKAGE_DEJAVU=y
-BR2_PACKAGE_GNUPLOT=y
-BR2_PACKAGE_TESSERACT_OCR=y
-BR2_PACKAGE_TESSERACT_OCR_LANG_ENG=y
-BR2_PACKAGE_TESSERACT_OCR_LANG_CHI_SIM=y
-BR2_PACKAGE_TESSERACT_OCR_LANG_CHI_TRA=y
-BR2_PACKAGE_QT5=y
-BR2_PACKAGE_QT5BASE_SQLITE_SYSTEM=y
-BR2_PACKAGE_QT5BASE_GUI=y
-BR2_PACKAGE_QT5BASE_LINUXFB=y
-BR2_PACKAGE_QT5BASE_WIDGETS=y
-BR2_PACKAGE_QT5BASE_DEFAULT_QPA="linuxfb"
-BR2_PACKAGE_QT5BASE_FONTCONFIG=y
-BR2_PACKAGE_QT5BASE_GIF=y
-BR2_PACKAGE_QT5BASE_PNG=y
-BR2_PACKAGE_QT5BASE_JPEG=y
-BR2_PACKAGE_QT5BASE_SYSLOG=y
-BR2_PACKAGE_QT5BASE_DBUS=y
-BR2_PACKAGE_QT5BASE_TSLIB=y
-BR2_PACKAGE_QT5BASE_EXAMPLES=y
-BR2_PACKAGE_QT5BASE_CONCURRENT=y
-BR2_PACKAGE_QT5CONNECTIVITY=y
-BR2_PACKAGE_QT5IMAGEFORMATS=y
-BR2_PACKAGE_QT5MULTIMEDIA=y
-BR2_PACKAGE_QT5SENSORS=y
-BR2_PACKAGE_QT5SERIALBUS=y
-BR2_PACKAGE_QT5CHARTS=y
-BR2_PACKAGE_QT5COAP=y
-BR2_PACKAGE_QT5ENGINIO=y
-BR2_PACKAGE_QT5KNX=y
-BR2_PACKAGE_QT5LOCATION=y
-BR2_PACKAGE_QT5MQTT=y
-BR2_PACKAGE_QT5OPCUA=y
-BR2_PACKAGE_QT5REMOTEOBJECTS=y
-BR2_PACKAGE_QT5SPEECH=y
-BR2_PACKAGE_QT5SVG=y
-BR2_PACKAGE_QT5WEBSOCKETS=y
-BR2_PACKAGE_QT5WEBCHANNEL=y
-BR2_PACKAGE_QEXTSERIALPORT=y
-BR2_PACKAGE_QT5X11EXTRAS=y
-BR2_PACKAGE_QT5XMLPATTERNS=y
-BR2_PACKAGE_QT5BASE_MYSQL=y
-BR2_PACKAGE_QJSON=y
-BR2_PACKAGE_QUAZIP=y
+# BR2_PACKAGE_MULTICAT is not set
+# BR2_PACKAGE_WQY_ZENHEI is not set
+# BR2_PACKAGE_DEJAVU is not set
+# BR2_PACKAGE_GNUPLOT is not set
+# BR2_PACKAGE_TESSERACT_OCR is not set
+# BR2_PACKAGE_TESSERACT_OCR_LANG_ENG is not set
+# BR2_PACKAGE_TESSERACT_OCR_LANG_CHI_SIM is not set
+# BR2_PACKAGE_TESSERACT_OCR_LANG_CHI_TRA is not set
+# BR2_PACKAGE_QT5 is not set
+# BR2_PACKAGE_QT5BASE_SQLITE_SYSTEM is not set
+# BR2_PACKAGE_QT5BASE_GUI is not set
+# BR2_PACKAGE_QT5BASE_LINUXFB is not set
+# BR2_PACKAGE_QT5BASE_WIDGETS is not set
+# BR2_PACKAGE_QT5BASE_DEFAULT_QPA="linuxf is not set
+# BR2_PACKAGE_QT5BASE_FONTCONFIG is not set
+# BR2_PACKAGE_QT5BASE_GIF is not set
+# BR2_PACKAGE_QT5BASE_PNG is not set
+# BR2_PACKAGE_QT5BASE_JPEG is not set
+# BR2_PACKAGE_QT5BASE_SYSLOG is not set
+# BR2_PACKAGE_QT5BASE_DBUS is not set
+# BR2_PACKAGE_QT5BASE_TSLIB is not set
+# BR2_PACKAGE_QT5BASE_EXAMPLES is not set
+# BR2_PACKAGE_QT5BASE_CONCURRENT is not set
+# BR2_PACKAGE_QT5CONNECTIVITY is not set
+# BR2_PACKAGE_QT5IMAGEFORMATS is not set
+# BR2_PACKAGE_QT5MULTIMEDIA is not set
+# BR2_PACKAGE_QT5SENSORS is not set
+# BR2_PACKAGE_QT5SERIALBUS is not set
+# BR2_PACKAGE_QT5CHARTS is not set
+# BR2_PACKAGE_QT5COAP is not set
+# BR2_PACKAGE_QT5ENGINIO is not set
+# BR2_PACKAGE_QT5KNX is not set
+# BR2_PACKAGE_QT5LOCATION is not set
+# BR2_PACKAGE_QT5MQTT is not set
+# BR2_PACKAGE_QT5OPCUA is not set
+# BR2_PACKAGE_QT5REMOTEOBJECTS is not set
+# BR2_PACKAGE_QT5SPEECH is not set
+# BR2_PACKAGE_QT5SVG is not set
+# BR2_PACKAGE_QT5WEBSOCKETS is not set
+# BR2_PACKAGE_QT5WEBCHANNEL is not set
+# BR2_PACKAGE_QEXTSERIALPORT is not set
+# BR2_PACKAGE_QT5X11EXTRAS is not set
+# BR2_PACKAGE_QT5XMLPATTERNS is not set
+# BR2_PACKAGE_QT5BASE_MYSQL is not set
+# BR2_PACKAGE_QJSON is not set
+# BR2_PACKAGE_QUAZIP is not set
+BR2_PACKAGE_OPENCV4_LIB_PYTHON=y
+# BR2_PACKAGE_OPENCV4_WITH_QT5 is not set
 BR2_PACKAGE_PYTHON3=y
 BR2_PACKAGE_PYTHON3_2TO3=y
 BR2_PACKAGE_PYTHON3_BZIP2=y
 BR2_PACKAGE_PYTHON3_CODECSCJK=y
 BR2_PACKAGE_PYTHON3_CURSES=y
+BR2_PACKAGE_PYTHON3_READLINE=y
 BR2_PACKAGE_PYTHON3_SSL=y
 BR2_PACKAGE_PYTHON3_UNICODEDATA=y
 BR2_PACKAGE_PYTHON3_SQLITE=y
+BR2_PACKAGE_PYTHON3_PYEXPAT=y
 BR2_PACKAGE_PYTHON3_XZ=y
 BR2_PACKAGE_PYTHON3_ZLIB=y
+BR2_PACKAGE_PYTHON3_PY_PYC=y
+
 BR2_PACKAGE_PYTHON_NUMPY=y
-BR2_PACKAGE_OPENCV4_LIB_PYTHON=y
-BR2_PACKAGE_OPENCV4_WITH_QT5=y
 BR2_PACKAGE_PYTHON_BSDIFF4=y
 BR2_PACKAGE_PYTHON_BEAUTIFULSOUP4=y
 BR2_PACKAGE_PYTHON_CFFI=y
@@ -363,11 +378,9 @@ BR2_PACKAGE_PYTHON_SERIAL_ASYNCIO=y
 BR2_PACKAGE_PYTHON_WEBSOCKETS=y
 BR2_PACKAGE_PYTHON_WEBSOCKET_CLIENT=y
 BR2_PACKAGE_PYTHON_XMODEM=y
-BR2_PACKAGE_PYTHON3_PY_PYC=y
 BR2_PACKAGE_PYTHON_PYQT5=y
 BR2_PACKAGE_PYTHON_PYQRCODE=y
 BR2_PACKAGE_PYTHON_PYLIBFDT=y
-BR2_PACKAGE_PYTHON3_READLINE=y
 BR2_PACKAGE_PYTHON_JEDI=y
 BR2_PACKAGE_PYTHON_LIBUSB1=y
 BR2_PACKAGE_PYTHON_LXML=y
@@ -377,23 +390,222 @@ BR2_PACKAGE_PYTHON_PERIPHERY=y
 BR2_PACKAGE_PYTHON_PILLOW=y
 BR2_PACKAGE_PYTHON_POSIX_IPC=y
 BR2_PACKAGE_PYTHON_PROTOBUF=y
-BR2_PACKAGE_PYTHON_PYGAME=y
-BR2_PACKAGE_PYTHON_PYGAME_IMAGE=y
-BR2_PACKAGE_PYTHON_PYGAME_EXAMPLES=y
-BR2_PACKAGE_PYTHON_PYGAME_FONT=y
-BR2_PACKAGE_PYTHON_PYGAME_MIXER=y
 BR2_PACKAGE_PYTHON_PYUDEV=y
 BR2_PACKAGE_PYTHON_PYYAML=y
 BR2_PACKAGE_PYTHON_QRCODE=y
 BR2_PACKAGE_PYTHON_QRCODE_PIL=y
 BR2_PACKAGE_PYTHON_INTELHEX=y
 
+#
+# External python modules
+#
+BR2_PACKAGE_PYTHON_AENUM=y
+BR2_PACKAGE_PYTHON_ALSAAUDIO=y
+BR2_PACKAGE_PYTHON_APISPEC=y
+BR2_PACKAGE_PYTHON_ARGH=y
+BR2_PACKAGE_PYTHON_ASGIREF=y
+BR2_PACKAGE_PYTHON_ASTTOKENS=y
+BR2_PACKAGE_PYTHON_ASYNC_GENERATOR=y
+BR2_PACKAGE_PYTHON_ASYNC_TIMEOUT=y
+BR2_PACKAGE_PYTHON_ATTRS=y
+BR2_PACKAGE_PYTHON_BABEL=y
+BR2_PACKAGE_PYTHON_BACKCALL=y
+BR2_PACKAGE_PYTHON_BEAUTIFULSOUP4=y
+BR2_PACKAGE_PYTHON_BIDICT=y
+BR2_PACKAGE_PYTHON_BLINKER=y
+
+#
+# python-bluezero needs a glibc toolchain, gcc >= 4.9, host gcc >= 8
+#
+BR2_PACKAGE_PYTHON_BROTLI=y
+BR2_PACKAGE_PYTHON_BSDIFF4=y
+BR2_PACKAGE_PYTHON_CERTIFI=y
+BR2_PACKAGE_PYTHON_CFFI=y
+BR2_PACKAGE_PYTHON_CHARSET_NORMALIZER=y
+BR2_PACKAGE_PYTHON_CLICK=y
+BR2_PACKAGE_PYTHON_CRC16=y
+BR2_PACKAGE_PYTHON_CRCMOD=y
+BR2_PACKAGE_PYTHON_CRONTAB=y
+BR2_PACKAGE_PYTHON_CYCLER=y
+BR2_PACKAGE_PYTHON_DATEUTIL=y
+BR2_PACKAGE_PYTHON_DBUS_FAST=y
+BR2_PACKAGE_PYTHON_DBUS_NEXT=y
+BR2_PACKAGE_PYTHON_DECORATOR=y
+BR2_PACKAGE_PYTHON_DJANGO=y
+BR2_PACKAGE_PYTHON_ENGINEIO=y
+BR2_PACKAGE_PYTHON_EVDEV=y
+BR2_PACKAGE_PYTHON_EXECUTING=y
+BR2_PACKAGE_PYTHON_FLASK=y
+BR2_PACKAGE_PYTHON_FLASK_BABEL=y
+BR2_PACKAGE_PYTHON_FLASK_CORS=y
+BR2_PACKAGE_PYTHON_FLASK_JSONRPC=y
+BR2_PACKAGE_PYTHON_FLASK_LOGIN=y
+BR2_PACKAGE_PYTHON_FLASK_SMOREST=y
+BR2_PACKAGE_PYTHON_FLASK_SQLALCHEMY=y
+BR2_PACKAGE_PYTHON_FLASK_WTF=y
+BR2_PACKAGE_PYTHON_FLATBUFFERS=y
+
+#
+# python-gobject needs a glibc toolchain, gcc >= 4.9, host gcc >= 8
+#
+BR2_PACKAGE_PYTHON_GREENLET_ARCH_SUPPORTS=y
+BR2_PACKAGE_PYTHON_H11=y
+BR2_PACKAGE_PYTHON_HTML5LIB=y
+BR2_PACKAGE_PYTHON_HUMANIZE=y
+BR2_PACKAGE_PYTHON_HWDATA=y
+BR2_PACKAGE_PYTHON_IDNA=y
+BR2_PACKAGE_PYTHON_IFADDR=y
+BR2_PACKAGE_PYTHON_INTELHEX=y
+BR2_PACKAGE_PYTHON_IPYTHON=y
+BR2_PACKAGE_PYTHON_IPYTHON_GENUTILS=y
+BR2_PACKAGE_PYTHON_ITSDANGEROUS=y
+BR2_PACKAGE_PYTHON_JEDI=y
+BR2_PACKAGE_PYTHON_JINJA2=y
+BR2_PACKAGE_PYTHON_KIWISOLVER=y
+
+#
+# python-libconfig needs a glibc or uClibc toolchain w/ C++, threads
+#
+BR2_PACKAGE_PYTHON_LIBEVDEV=y
+BR2_PACKAGE_PYTHON_LIBUSB1=y
+BR2_PACKAGE_PYTHON_LXML=y
+BR2_PACKAGE_PYTHON_MARKUPSAFE=y
+BR2_PACKAGE_PYTHON_MARSHMALLOW=y
+BR2_PACKAGE_PYTHON_MSGPACK=y
+BR2_PACKAGE_PYTHON_MYPY_EXTENSIONS=y
+BR2_PACKAGE_PYTHON_NETADDR=y
+BR2_PACKAGE_PYTHON_NETIFACES=y
+BR2_PACKAGE_PYTHON_NETWORKX=y
+BR2_PACKAGE_PYTHON_NUMPY_ARCH_SUPPORTS=y
+BR2_PACKAGE_PYTHON_NUMPY=y
+BR2_PACKAGE_PYTHON_OAUTHLIB=y
+BR2_PACKAGE_PYTHON_OUTCOME=y
+BR2_PACKAGE_PYTHON_PACKAGING=y
+BR2_PACKAGE_PYTHON_PAHO_MQTT=y
+BR2_PACKAGE_PYTHON_PARSO=y
+BR2_PACKAGE_PYTHON_PATHTOOLS=y
+BR2_PACKAGE_PYTHON_PERIPHERY=y
+BR2_PACKAGE_PYTHON_PEXPECT=y
+BR2_PACKAGE_PYTHON_PICKLESHARE=y
+BR2_PACKAGE_PYTHON_PILLOW=y
+BR2_PACKAGE_PYTHON_PIP=y
+BR2_PACKAGE_PYTHON_POSIX_IPC=y
+BR2_PACKAGE_PYTHON_PROMPT_TOOLKIT=y
+BR2_PACKAGE_PYTHON_PROTOBUF=y
+BR2_PACKAGE_PYTHON_PSUTIL=y
+BR2_PACKAGE_PYTHON_PTYPROCESS=y
+BR2_PACKAGE_PYTHON_PURE_EVAL=y
+BR2_PACKAGE_PYTHON_PYAES=y
+BR2_PACKAGE_PYTHON_PYALSA=y
+BR2_PACKAGE_PYTHON_PYASN1=y
+BR2_PACKAGE_PYTHON_PYCPARSER=y
+BR2_PACKAGE_PYTHON_PYDEVMEM=y
+BR2_PACKAGE_PYTHON_PYGMENTS=y
+BR2_PACKAGE_PYTHON_PYLIBFDT=y
+BR2_PACKAGE_PYTHON_PYMODBUS=y
+
+#
+# python-pymupdf needs Xorg
+#
+BR2_PACKAGE_PYTHON_PYPARSING=y
+BR2_PACKAGE_PYTHON_PYQRCODE=y
+
+#
+# python-pyqt5 needs Qt5
+#
+BR2_PACKAGE_PYTHON_PYSMB=y
+BR2_PACKAGE_PYTHON_PYSOCKS=y
+BR2_PACKAGE_PYTHON_PYTZ=y
+BR2_PACKAGE_PYTHON_PYUDEV=y
+BR2_PACKAGE_PYTHON_PYUSB=y
+BR2_PACKAGE_PYTHON_PYYAML=y
+BR2_PACKAGE_PYTHON_PYZMQ=y
+BR2_PACKAGE_PYTHON_QRCODE=y
+BR2_PACKAGE_PYTHON_QRCODE_PIL=y
+BR2_PACKAGE_PYTHON_REQUESTS=y
+BR2_PACKAGE_PYTHON_REQUESTS_OAUTHLIB=y
+BR2_PACKAGE_PYTHON_REQUESTS_TOOLBELT=y
+BR2_PACKAGE_PYTHON_SCAPY=y
+
+#
+# python-scipy needs glibc or musl toolchain w/ fortran, c++, gcc >= 9, host gcc >= 9
+#
+BR2_PACKAGE_PYTHON_SELENIUM=y
+BR2_PACKAGE_PYTHON_SERIAL=y
+BR2_PACKAGE_PYTHON_SERIAL_ASYNCIO=y
+BR2_PACKAGE_PYTHON_SETUPTOOLS=y
+BR2_PACKAGE_PYTHON_SIX=y
+BR2_PACKAGE_PYTHON_SMBUS_CFFI=y
+BR2_PACKAGE_PYTHON_SNAPPY=y
+BR2_PACKAGE_PYTHON_SNIFFIO=y
+BR2_PACKAGE_PYTHON_SOCKETIO=y
+BR2_PACKAGE_PYTHON_SORTEDCONTAINERS=y
+BR2_PACKAGE_PYTHON_SOUPSIEVE=y
+BR2_PACKAGE_PYTHON_SPIDEV=y
+BR2_PACKAGE_PYTHON_SQLALCHEMY=y
+BR2_PACKAGE_PYTHON_SQLPARSE=y
+BR2_PACKAGE_PYTHON_STACK_DATA=y
+
+#
+# python-systemd needs systemd
+#
+BR2_PACKAGE_PYTHON_TINYRPC=y
+BR2_PACKAGE_PYTHON_TOML=y
+BR2_PACKAGE_PYTHON_TORNADO=y
+BR2_PACKAGE_PYTHON_TQDM=y
+BR2_PACKAGE_PYTHON_TRAITLETS=y
+BR2_PACKAGE_PYTHON_TRIO=y
+BR2_PACKAGE_PYTHON_TRIO_WEBSOCKET=y
+BR2_PACKAGE_PYTHON_TYPEGUARD=y
+BR2_PACKAGE_PYTHON_TYPING_EXTENSIONS=y
+BR2_PACKAGE_PYTHON_TYPING_INSPECT=y
+BR2_PACKAGE_PYTHON_UBJSON=y
+BR2_PACKAGE_PYTHON_UHID=y
+BR2_PACKAGE_PYTHON_UJSON=y
+BR2_PACKAGE_PYTHON_URLLIB3=y
+BR2_PACKAGE_PYTHON_WATCHDOG=y
+BR2_PACKAGE_PYTHON_WCWIDTH=y
+BR2_PACKAGE_PYTHON_WEBARGS=y
+BR2_PACKAGE_PYTHON_WEBENCODINGS=y
+BR2_PACKAGE_PYTHON_WEBSOCKET_CLIENT=y
+BR2_PACKAGE_PYTHON_WEBSOCKETS=y
+BR2_PACKAGE_PYTHON_WERKZEUG=y
+BR2_PACKAGE_PYTHON_WSPROTO=y
+BR2_PACKAGE_PYTHON_WTFORMS=y
+BR2_PACKAGE_PYTHON_XLRD=y
+BR2_PACKAGE_PYTHON_XLSXWRITER=y
+BR2_PACKAGE_PYTHON_XLUTILS=y
+BR2_PACKAGE_PYTHON_XLWT=y
+BR2_PACKAGE_PYTHON_XMODEM=y
+BR2_PACKAGE_PYTHON_ZEROCONF=y
+
+# BR2_PACKAGE_MGBA is not set
+# BR2_PACKAGE_GB_TEST_ROMS is not set
+
+# BR2_PACKAGE_NGINX=y
+# BR2_PACKAGE_NGINX_HTTP=y
+# BR2_PACKAGE_NGINX_HTTP_DAV_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_MP4_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_FLV_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_GUNZIP_MODULE=y
+# BR2_PACKAGE_NGINX_STREAM=y
+# BR2_PACKAGE_NGINX_SELECT_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_FASTCGI_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_UWSGI_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_SCGI_MODULE=y
+
 BR2_PACKAGE_VIM=y
 BR2_PACKAGE_VIM_RUNTIME=y
 
+BR2_PACKAGE_AXP2101=y
+
 BR2_TARGET_ROOTFS_EXT2=y
 BR2_TARGET_ROOTFS_EXT2_4=y
-BR2_TARGET_ROOTFS_EXT2_SIZE="900M"
+BR2_TARGET_ROOTFS_EXT2_SIZE="1536M"
 
 BR2_ROOTFS_OVERLAY="$(TOPDIR)/board/cvitek/SG200X/overlay"
 BR2_PACKAGE_BUSYBOX_CONFIG_FRAGMENT_FILES="$(TOPDIR)/board/cvitek/SG200X/busybox-extra.config"
+
+BR2_TARGET_TZ_INFO=y
+BR2_TARGET_TZ_ZONELIST="default"
+BR2_TARGET_LOCALTIME="Etc/UTC"

buildroot/package/Config.in

@@ -2680,6 +2680,7 @@ menu "System tools"
 	source "package/atop/Config.in"
 	source "package/attr/Config.in"
 	source "package/audit/Config.in"
+	source "package/axp2101/Config.in"
 	source "package/balena-engine/Config.in"
 	source "package/bubblewrap/Config.in"
 	source "package/cgroupfs-mount/Config.in"
@@ -2808,6 +2809,8 @@ menu "Sipeed"
 	source "package/tpudemo-sg200x/Config.in"
 	source "package/xuantie-gdb/Config.in"
 	source "package/sg2002-codec-firmware/Config.in"
+	source "package/mgba/Config.in"
+	source "package/gb-test-roms/Config.in"
 endmenu
 
 

buildroot/package/axp2101/Config.in

@@ -0,0 +1,5 @@
+config BR2_PACKAGE_AXP2101
+    bool "axp2101"
+    help
+      If you say Y here you get support for the X-Powers AXP2101 power
+      management ICs (PMICs) controlled with I2C.

buildroot/package/axp2101/axp2101.mk

@@ -0,0 +1,20 @@
+################################################################################
+#
+# axp2101
+#
+################################################################################
+
+AXP2101_VERSION = 1.1.0
+AXP2101_SITE = $(TOPDIR)/package/axp2101/src
+AXP2101_SITE_METHOD = local
+AXP2101_CFLAGS = -Iinclude -IXPowersLib -IXPowersLib/REG -Wall -Wextra
+
+define AXP2101_BUILD_CMDS
+    $(MAKE) $(TARGET_CONFIGURE_OPTS) CFLAGS="$(AXP2101_CFLAGS)" -C $(@D)
+endef
+
+define AXP2101_INSTALL_TARGET_CMDS
+    $(INSTALL) -D -m 0755 $(@D)/axp2101 $(TARGET_DIR)/usr/bin/axp2101
+endef
+
+$(eval $(generic-package))

buildroot/package/axp2101/src/Makefile

@@ -0,0 +1,26 @@
+APP_DIR = ./src
+SRC_DIR = ./XPowersLib
+DIR_BIN = ./bin
+
+OBJ_C = $(wildcard ${SRC_DIR}/*.cpp ${APP_DIR}/*.cpp)
+OBJ_O = $(patsubst %.cpp,${DIR_BIN}/%.o,$(notdir ${OBJ_C}))
+
+TARGET = axp2101
+
+$(shell mkdir -p $(DIR_BIN))
+
+MSG = -g -O0 -Wall 
+CFLAGS += $(MSG)
+
+${TARGET}:${OBJ_O}
+	$(CXX) $(CFLAGS) $(OBJ_O) -o $@ $(LIB)
+
+${DIR_BIN}/%.o:$(APP_DIR)/%.cpp
+	$(CXX) $(CFLAGS) -c  $< -o $@ -I $(SRC_DIR)
+
+${DIR_BIN}/%.o:$(SRC_DIR)/%.cpp
+	$(CXX) $(CFLAGS) -c  $< -o $@ $(LIB)
+
+clean :
+	rm $(DIR_BIN)/*.* 
+	rm $(TARGET) 

buildroot/package/axp2101/src/XPowersLib/PowerDeliveryHUSB238.hpp

@@ -0,0 +1,171 @@
+/**
+ *
+ * @license MIT License
+ *
+ * Copyright (c) 2024 lewis he
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * @file      PowerDeliveryHUSB238.tpp
+ * @author    Lewis He (lewishe@outlook.com)
+ * @date      2024-07-24
+ *
+ */
+#if defined(ARDUINO)
+#include <Arduino.h>
+#else
+#include <math.h>
+#endif /*ARDUINO*/
+#include "XPowersCommon.tpp"
+#include "REG/HUSB238Constants.h"
+
+class PowerDeliveryHUSB238 :
+    public XPowersCommon<PowerDeliveryHUSB238>
+{
+    friend class XPowersCommon<PowerDeliveryHUSB238>;
+
+public:
+
+    enum PD_Status {
+        NO_RESPONSE,
+        SUCCESS,
+        INVALID_CMD,
+        NOT_SUPPORT,
+        TRANSACTION_FAIL
+    };
+
+    enum PD_Voltage {
+        PD_5V = 1,
+        PD_9V,
+        PD_12V,
+        PD_15V,
+        PD_18V,
+        PD_20V
+    };
+
+
+#if defined(ARDUINO)
+    PowerDeliveryHUSB238(TwoWire &w, int sda = SDA, int scl = SCL, uint8_t addr = HUSB238_SLAVE_ADDRESS)
+    {
+        __wire = &w;
+        __sda = sda;
+        __scl = scl;
+        __addr = addr;
+    }
+#endif
+
+    PowerDeliveryHUSB238(uint8_t addr, iic_fptr_t readRegCallback, iic_fptr_t writeRegCallback)
+    {
+        thisReadRegCallback = readRegCallback;
+        thisWriteRegCallback = writeRegCallback;
+        __addr = addr;
+    }
+
+    PowerDeliveryHUSB238()
+    {
+#if defined(ARDUINO)
+        __wire = &Wire;
+        __sda = SDA;
+        __scl = SCL;
+#endif
+        __addr = HUSB238_SLAVE_ADDRESS;
+    }
+
+
+    ~PowerDeliveryHUSB238()
+    {
+        log_i("~PowerDeliveryHUSB238");
+        deinit();
+    }
+
+#if defined(ARDUINO)
+    bool init(TwoWire &w, int sda = SDA, int scl = SCL, uint8_t addr = HUSB238_SLAVE_ADDRESS)
+    {
+        __wire = &w;
+        __sda = sda;
+        __scl = scl;
+        __addr = addr;
+        return begin();
+    }
+#endif
+
+    void deinit()
+    {
+        end();
+    }
+
+    uint8_t getPdVoltage()
+    {
+        int val =  readRegister(HUSB238_PD_STATUS0);
+        if (val == -1)return 0;
+        val &= 0xF0;
+        val >>= 4;
+        return pd_voltage_list[val];
+    }
+
+    float getPdCurrent()
+    {
+        int val =  readRegister(HUSB238_PD_STATUS0);
+        if (val == -1)return 0;
+        val &= 0x0F;
+        return pd_current_list[val];
+    }
+
+    void setPdVoltage(PD_Voltage vol)
+    {
+        writeRegister(HUSB238_SRC_PDO, vol);
+        writeRegister(HUSB238_GO_COMMAND, 0x01);
+    }
+
+    void resetPdVoltage()
+    {
+        writeRegister(HUSB238_GO_COMMAND, 0x10);
+    }
+
+    bool attach()
+    {
+        return getRegisterBit(HUSB238_PD_STATUS1, 6);
+    }
+
+    PD_Status status()
+    {
+        int val = readRegister(HUSB238_PD_STATUS1);
+        if (val == -1)return NO_RESPONSE;
+        val >>= 3;
+        val &= 0x03;
+        return static_cast<PD_Status>(val);
+    }
+
+
+private:
+    const uint8_t pd_voltage_list[7] = {0, 5, 9, 12, 15, 18, 20};
+    const float pd_current_list[16] = {
+        0.5, 0.7, 1, 1.25, 1.5, 1.75, 2, 2.25, 2.5,
+        2.75, 3, 3.25, 3.5, 4, 4.5, 5
+    };
+
+    bool initImpl()
+    {
+        return readRegister(HUSB238_PD_STATUS0) != -1;
+    }
+
+};
+
+
+

buildroot/package/axp2101/src/XPowersLib/REG/AXP192Constants.h

@@ -0,0 +1,182 @@
+#pragma once
+
+#define AXP192_SLAVE_ADDRESS                            (0x34)
+
+#define XPOWERS_AXP192_CHIP_ID                          (0x03)
+
+#define XPOWERS_AXP192_STATUS                           (0x00)
+#define XPOWERS_AXP192_MODE_CHGSTATUS                   (0x01)
+#define XPOWERS_AXP192_OTG_STATUS                       (0x02)
+#define XPOWERS_AXP192_IC_TYPE                          (0x03)
+
+#define XPOWERS_AXP192_DATA_BUFFER1                     (0x06)
+#define XPOWERS_AXP192_DATA_BUFFER2                     (0x07)
+#define XPOWERS_AXP192_DATA_BUFFER3                     (0x08)
+#define XPOWERS_AXP192_DATA_BUFFER4                     (0x09)
+#define XPOWERS_AXP192_DATA_BUFFER5                     (0x0A)
+#define XPOWERS_AXP192_DATA_BUFFER6                     (0x0B)
+#define XPOWERS_AXP192_DATA_BUFFER_SIZE                 (6)
+
+
+#define XPOWERS_AXP192_LDO23_DC123_EXT_CTL              (0x12)
+#define XPOWERS_AXP192_DC2OUT_VOL                       (0x23)
+#define XPOWERS_AXP192_DC2_DVM                          (0x25)
+#define XPOWERS_AXP192_DC3OUT_VOL                       (0x27)
+#define XPOWERS_AXP192_LDO24OUT_VOL                     (0x28)
+#define XPOWERS_AXP192_LDO3OUT_VOL                      (0x29)
+#define XPOWERS_AXP192_IPS_SET                          (0x30)
+#define XPOWERS_AXP192_VOFF_SET                         (0x31)
+#define XPOWERS_AXP192_OFF_CTL                          (0x32)
+#define XPOWERS_AXP192_CHARGE1                          (0x33)
+#define XPOWERS_AXP192_CHARGE2                          (0x34)
+#define XPOWERS_AXP192_BACKUP_CHG                       (0x35)
+#define XPOWERS_AXP192_POK_SET                          (0x36)
+#define XPOWERS_AXP192_DCDC_FREQSET                     (0x37)
+#define XPOWERS_AXP192_VLTF_CHGSET                      (0x38)
+#define XPOWERS_AXP192_VHTF_CHGSET                      (0x39)
+#define XPOWERS_AXP192_APS_WARNING1                     (0x3A)
+#define XPOWERS_AXP192_APS_WARNING2                     (0x3B)
+#define XPOWERS_AXP192_TLTF_DISCHGSET                   (0x3C)
+#define XPOWERS_AXP192_THTF_DISCHGSET                   (0x3D)
+#define XPOWERS_AXP192_DCDC_MODESET                     (0x80)
+#define XPOWERS_AXP192_ADC_EN1                          (0x82)
+#define XPOWERS_AXP192_ADC_EN2                          (0x83)
+#define XPOWERS_AXP192_ADC_SPEED                        (0x84)
+#define XPOWERS_AXP192_ADC_INPUTRANGE                   (0x85)
+#define XPOWERS_AXP192_ADC_IRQ_RETFSET                  (0x86)
+#define XPOWERS_AXP192_ADC_IRQ_FETFSET                  (0x87)
+#define XPOWERS_AXP192_TIMER_CTL                        (0x8A)
+#define XPOWERS_AXP192_VBUS_DET_SRP                     (0x8B)
+#define XPOWERS_AXP192_HOTOVER_CTL                      (0x8F)
+
+#define XPOWERS_AXP192_PWM1_FREQ_SET                    (0x98)
+#define XPOWERS_AXP192_PWM1_DUTY_SET1                   (0x99)
+#define XPOWERS_AXP192_PWM1_DUTY_SET2                   (0x9A)
+
+#define XPOWERS_AXP192_PWM2_FREQ_SET                    (0x9B)
+#define XPOWERS_AXP192_PWM2_DUTY_SET1                   (0x9C)
+#define XPOWERS_AXP192_PWM2_DUTY_SET2                   (0x9D)
+
+
+// INTERRUPT REGISTER
+#define XPOWERS_AXP192_INTEN1                           (0x40)
+#define XPOWERS_AXP192_INTEN2                           (0x41)
+#define XPOWERS_AXP192_INTEN3                           (0x42)
+#define XPOWERS_AXP192_INTEN4                           (0x43)
+#define XPOWERS_AXP192_INTEN5                           (0x4A)
+
+// INTERRUPT STATUS REGISTER
+#define XPOWERS_AXP192_INTSTS1                          (0x44)
+#define XPOWERS_AXP192_INTSTS2                          (0x45)
+#define XPOWERS_AXP192_INTSTS3                          (0x46)
+#define XPOWERS_AXP192_INTSTS4                          (0x47)
+#define XPOWERS_AXP192_INTSTS5                          (0x4D)
+#define XPOWERS_AXP192_INTSTS_CNT                       (5)
+
+#define XPOWERS_AXP192_DC1_VLOTAGE                      (0x26)
+#define XPOWERS_AXP192_LDO23OUT_VOL                     (0x28)
+#define XPOWERS_AXP192_GPIO0_CTL                        (0x90)
+#define XPOWERS_AXP192_GPIO0_VOL                        (0x91)
+#define XPOWERS_AXP192_GPIO1_CTL                        (0X92)
+#define XPOWERS_AXP192_GPIO2_CTL                        (0x93)
+#define XPOWERS_AXP192_GPIO012_SIGNAL                   (0x94)
+#define XPOWERS_AXP192_GPIO34_CTL                       (0x95)
+#define XPOWERS_AXP192_GPIO34_SIGNAL                    (0x96)
+#define XPOWERS_AXP192_GPIO012_PULLDOWN                 (0x97)
+#define XPOWERS_AXP192_GPIO5_CTL                        (0x9E)
+
+#define XPOWERS_AXP192_GPIO0_VOL_ADC_H8                 (0x64)
+#define XPOWERS_AXP192_GPIO0_VOL_ADC_L4                 (0x65)
+#define XPOWERS_AXP192_GPIO1_VOL_ADC_H8                 (0x66)
+#define XPOWERS_AXP192_GPIO1_VOL_ADC_L4                 (0x67)
+#define XPOWERS_AXP192_GPIO2_VOL_ADC_H8                 (0x68)
+#define XPOWERS_AXP192_GPIO2_VOL_ADC_L4                 (0x69)
+#define XPOWERS_AXP192_GPIO3_VOL_ADC_H8                 (0x6A)
+#define XPOWERS_AXP192_GPIO3_VOL_ADC_L4                 (0x6B)
+
+#define XPOWERS_AXP192_GPIO0_STEP                       (0.5F)
+#define XPOWERS_AXP192_GPIO1_STEP                       (0.5F)
+#define XPOWERS_AXP192_TS_IN_H8                         (0x62)
+#define XPOWERS_AXP192_TS_IN_L4                         (0x63)
+
+#define XPOWERS_AXP192_BAT_AVERCHGCUR_H8                (0x7A)
+#define XPOWERS_AXP192_BAT_AVERCHGCUR_L5                (0x7B)
+
+
+#define XPOWERS_AXP192_ACIN_VOL_H8                      (0x56)
+#define XPOWERS_AXP192_ACIN_VOL_L4                      (0x57)
+#define XPOWERS_AXP192_ACIN_CUR_H8                      (0x58)
+#define XPOWERS_AXP192_ACIN_CUR_L4                      (0x59)
+#define XPOWERS_AXP192_VBUS_VOL_H8                      (0x5A)
+#define XPOWERS_AXP192_VBUS_VOL_L4                      (0x5B)
+#define XPOWERS_AXP192_VBUS_CUR_H8                      (0x5C)
+#define XPOWERS_AXP192_VBUS_CUR_L4                      (0x5D)
+
+#define XPOWERS_AXP192_BAT_AVERDISCHGCUR_H8             (0x7C)
+#define XPOWERS_AXP192_BAT_AVERDISCHGCUR_L5             (0x7D)
+#define XPOWERS_AXP192_APS_AVERVOL_H8                   (0x7E)
+#define XPOWERS_AXP192_APS_AVERVOL_L4                   (0x7F)
+#define XPOWERS_AXP192_BAT_AVERVOL_H8                   (0x78)
+#define XPOWERS_AXP192_BAT_AVERVOL_L4                   (0x79)
+
+#define XPOWERS_AXP192_BAT_CHGCOULOMB3                  (0xB0)
+#define XPOWERS_AXP192_BAT_CHGCOULOMB2                  (0xB1)
+#define XPOWERS_AXP192_BAT_CHGCOULOMB1                  (0xB2)
+#define XPOWERS_AXP192_BAT_CHGCOULOMB0                  (0xB3)
+#define XPOWERS_AXP192_BAT_DISCHGCOULOMB3               (0xB4)
+#define XPOWERS_AXP192_BAT_DISCHGCOULOMB2               (0xB5)
+#define XPOWERS_AXP192_BAT_DISCHGCOULOMB1               (0xB6)
+#define XPOWERS_AXP192_BAT_DISCHGCOULOMB0               (0xB7)
+#define XPOWERS_AXP192_COULOMB_CTL                      (0xB8)
+
+
+#define XPOWERS_AXP192_BATT_VOLTAGE_STEP                (1.1F)
+#define XPOWERS_AXP192_BATT_DISCHARGE_CUR_STEP          (0.5F)
+#define XPOWERS_AXP192_BATT_CHARGE_CUR_STEP             (0.5F)
+#define XPOWERS_AXP192_ACIN_VOLTAGE_STEP                (1.7F)
+#define XPOWERS_AXP192_ACIN_CUR_STEP                    (0.625F)
+#define XPOWERS_AXP192_VBUS_VOLTAGE_STEP                (1.7F)
+#define XPOWERS_AXP192_VBUS_CUR_STEP                    (0.375F)
+#define XPOWERS_AXP192_APS_VOLTAGE_STEP                 (1.4F)
+#define XPOWERS_AXP192_TS_PIN_OUT_STEP                  (0.8F)
+
+
+#define XPOWERS_AXP192_LDO2_VOL_MIN                     (1800u)
+#define XPOWERS_AXP192_LDO2_VOL_MAX                     (3300u)
+#define XPOWERS_AXP192_LDO2_VOL_STEPS                   (100u)
+#define XPOWERS_AXP192_LDO2_VOL_BIT_MASK                (4u)
+
+#define XPOWERS_AXP192_LDO3_VOL_MIN                     (1800u)
+#define XPOWERS_AXP192_LDO3_VOL_MAX                     (3300u)
+#define XPOWERS_AXP192_LDO3_VOL_STEPS                   (100u)
+
+
+#define XPOWERS_AXP192_DC1_VOL_STEPS                    (25u)
+#define XPOWERS_AXP192_DC1_VOL_MIN                      (700u)
+#define XPOWERS_AXP192_DC1_VOL_MAX                      (3500u)
+
+#define XPOWERS_AXP192_DC2_VOL_STEPS                    (25u)
+#define XPOWERS_AXP192_DC2_VOL_MIN                      (700u)
+#define XPOWERS_AXP192_DC2_VOL_MAX                      (3500u)
+
+#define XPOWERS_AXP192_DC3_VOL_STEPS                    (25u)
+#define XPOWERS_AXP192_DC3_VOL_MIN                      (700u)
+#define XPOWERS_AXP192_DC3_VOL_MAX                      (3500u)
+
+#define XPOWERS_AXP192_LDOIO_VOL_STEPS                  (100)
+#define XPOWERS_AXP192_LDOIO_VOL_MIN                    (1800)
+#define XPOWERS_AXP192_LDOIO_VOL_MAX                    (3300)
+
+#define XPOWERS_AXP192_SYS_VOL_STEPS                    (100)
+#define XPOWERS_AXP192_VOFF_VOL_MIN                     (2600)
+#define XPOWERS_AXP192_VOFF_VOL_MAX                     (3300)
+
+#define XPOWERS_AXP192_CHG_EXT_CURR_MIN                 (300)
+#define XPOWERS_AXP192_CHG_EXT_CURR_MAX                 (1000)
+#define XPOWERS_AXP192_CHG_EXT_CURR_STEP                (100)
+
+
+#define XPOWERS_AXP192_INTERNAL_TEMP_H8                 (0x5E)
+#define XPOWERS_AXP192_INTERNAL_TEMP_L4                 (0x5F)
+#define XPOWERS_AXP192_INTERNAL_TEMP_STEP               (0.1F)
+#define XPOWERS_AXP192_INERNAL_TEMP_OFFSET              (144.7)

buildroot/package/axp2101/src/XPowersLib/REG/AXP202Constants.h

@@ -0,0 +1,192 @@
+#pragma once
+
+#define AXP202_SLAVE_ADDRESS                            (0x35)
+
+#define XPOWERS_AXP202_CHIP_ID                          (0x41)
+
+#define XPOWERS_AXP202_STATUS                           (0x00)
+#define XPOWERS_AXP202_MODE_CHGSTATUS                   (0x01)
+#define XPOWERS_AXP202_OTG_STATUS                       (0x02)
+#define XPOWERS_AXP202_IC_TYPE                          (0x03)
+#define XPOWERS_AXP202_DATA_BUFFER1                     (0x04)
+#define XPOWERS_AXP202_DATA_BUFFER2                     (0x05)
+#define XPOWERS_AXP202_DATA_BUFFER3                     (0x06)
+#define XPOWERS_AXP202_DATA_BUFFER4                     (0x07)
+#define XPOWERS_AXP202_DATA_BUFFER5                     (0x08)
+#define XPOWERS_AXP202_DATA_BUFFER6                     (0x09)
+#define XPOWERS_AXP202_DATA_BUFFER7                     (0x0A)
+#define XPOWERS_AXP202_DATA_BUFFER8                     (0x0B)
+#define XPOWERS_AXP202_DATA_BUFFER9                     (0x0C)
+#define XPOWERS_AXP202_DATA_BUFFERA                     (0x0D)
+#define XPOWERS_AXP202_DATA_BUFFERB                     (0x0E)
+#define XPOWERS_AXP202_DATA_BUFFERC                     (0x0F)
+#define XPOWERS_AXP202_LDO234_DC23_CTL                  (0x12)
+#define XPOWERS_AXP202_DC2OUT_VOL                       (0x23)
+#define XPOWERS_AXP202_LDO3_DC2_DVM                     (0x25)
+#define XPOWERS_AXP202_DC3OUT_VOL                       (0x27)
+#define XPOWERS_AXP202_LDO24OUT_VOL                     (0x28)
+#define XPOWERS_AXP202_LDO3OUT_VOL                      (0x29)
+#define XPOWERS_AXP202_IPS_SET                          (0x30)
+#define XPOWERS_AXP202_VOFF_SET                         (0x31)
+#define XPOWERS_AXP202_OFF_CTL                          (0x32)
+#define XPOWERS_AXP202_CHARGE1                          (0x33)
+#define XPOWERS_AXP202_CHARGE2                          (0x34)
+#define XPOWERS_AXP202_BACKUP_CHG                       (0x35)
+#define XPOWERS_AXP202_POK_SET                          (0x36)
+#define XPOWERS_AXP202_DCDC_FREQSET                     (0x37)
+#define XPOWERS_AXP202_VLTF_CHGSET                      (0x38)
+#define XPOWERS_AXP202_VHTF_CHGSET                      (0x39)
+#define XPOWERS_AXP202_APS_WARNING1                     (0x3A)
+#define XPOWERS_AXP202_APS_WARNING2                     (0x3B)
+#define XPOWERS_AXP202_TLTF_DISCHGSET                   (0x3C)
+#define XPOWERS_AXP202_THTF_DISCHGSET                   (0x3D)
+#define XPOWERS_AXP202_DCDC_MODESET                     (0x80)
+#define XPOWERS_AXP202_ADC_EN1                          (0x82)
+#define XPOWERS_AXP202_ADC_EN2                          (0x83)
+#define XPOWERS_AXP202_ADC_SPEED                        (0x84)
+#define XPOWERS_AXP202_ADC_INPUTRANGE                   (0x85)
+#define XPOWERS_AXP202_ADC_IRQ_RETFSET                  (0x86)
+#define XPOWERS_AXP202_ADC_IRQ_FETFSET                  (0x87)
+#define XPOWERS_AXP202_TIMER_CTL                        (0x8A)
+#define XPOWERS_AXP202_VBUS_DET_SRP                     (0x8B)
+#define XPOWERS_AXP202_HOTOVER_CTL                      (0x8F)
+
+#define XPOWERS_AXP202_DATA_BUFFER_SIZE                 (12)
+#define XPOWERS_AXP202_GPIO0_CTL                        (0x90)
+#define XPOWERS_AXP202_GPIO0_VOL                        (0x91)
+#define XPOWERS_AXP202_GPIO1_CTL                        (0x92)
+#define XPOWERS_AXP202_GPIO2_CTL                        (0x93)
+#define XPOWERS_AXP202_GPIO012_SIGNAL                   (0x94)
+#define XPOWERS_AXP202_GPIO3_CTL                        (0x95)
+
+// INTERRUPT REGISTER
+#define XPOWERS_AXP202_INTEN1                           (0x40)
+#define XPOWERS_AXP202_INTEN2                           (0x41)
+#define XPOWERS_AXP202_INTEN3                           (0x42)
+#define XPOWERS_AXP202_INTEN4                           (0x43)
+#define XPOWERS_AXP202_INTEN5                           (0x44)
+
+//INTERRUPT STATUS REGISTER
+#define XPOWERS_AXP202_INTSTS1                          (0x48)
+#define XPOWERS_AXP202_INTSTS2                          (0x49)
+#define XPOWERS_AXP202_INTSTS3                          (0x4A)
+#define XPOWERS_AXP202_INTSTS4                          (0x4B)
+#define XPOWERS_AXP202_INTSTS5                          (0x4C)
+#define XPOWERS_AXP202_INTSTS_CNT                       (5)
+
+
+//AXP ADC DATA REGISTER
+#define XPOWERS_AXP202_GPIO0_VOL_ADC_H8                 (0x64)
+#define XPOWERS_AXP202_GPIO0_VOL_ADC_L4                 (0x65)
+#define XPOWERS_AXP202_GPIO1_VOL_ADC_H8                 (0x66)
+#define XPOWERS_AXP202_GPIO1_VOL_ADC_L4                 (0x67)
+
+
+#define XPOWERS_AXP202_GPIO0_STEP                       (0.5F)
+#define XPOWERS_AXP202_GPIO1_STEP                       (0.5F)
+
+#define XPOWERS_AXP202_BAT_AVERVOL_H8                   (0x78)
+#define XPOWERS_AXP202_BAT_AVERVOL_L4                   (0x79)
+
+#define XPOWERS_AXP202_BAT_AVERCHGCUR_H8                (0x7A)
+#define XPOWERS_AXP202_BAT_AVERCHGCUR_L4                (0x7B)
+
+#define XPOWERS_AXP202_BAT_AVERCHGCUR_L5                (0x7B)
+#define XPOWERS_AXP202_ACIN_VOL_H8                      (0x56)
+#define XPOWERS_AXP202_ACIN_VOL_L4                      (0x57)
+#define XPOWERS_AXP202_ACIN_CUR_H8                      (0x58)
+#define XPOWERS_AXP202_ACIN_CUR_L4                      (0x59)
+#define XPOWERS_AXP202_VBUS_VOL_H8                      (0x5A)
+#define XPOWERS_AXP202_VBUS_VOL_L4                      (0x5B)
+#define XPOWERS_AXP202_VBUS_CUR_H8                      (0x5C)
+#define XPOWERS_AXP202_VBUS_CUR_L4                      (0x5D)
+#define XPOWERS_AXP202_INTERNAL_TEMP_H8                 (0x5E)
+#define XPOWERS_AXP202_INTERNAL_TEMP_L4                 (0x5F)
+#define XPOWERS_AXP202_TS_IN_H8                         (0x62)
+#define XPOWERS_AXP202_TS_IN_L4                         (0x63)
+#define XPOWERS_AXP202_GPIO0_VOL_ADC_H8                 (0x64)
+#define XPOWERS_AXP202_GPIO0_VOL_ADC_L4                 (0x65)
+#define XPOWERS_AXP202_GPIO1_VOL_ADC_H8                 (0x66)
+#define XPOWERS_AXP202_GPIO1_VOL_ADC_L4                 (0x67)
+
+#define XPOWERS_AXP202_BAT_AVERDISCHGCUR_H8             (0x7C)
+#define XPOWERS_AXP202_BAT_AVERDISCHGCUR_L5             (0x7D)
+#define XPOWERS_AXP202_APS_AVERVOL_H8                   (0x7E)
+#define XPOWERS_AXP202_APS_AVERVOL_L4                   (0x7F)
+#define XPOWERS_AXP202_INT_BAT_CHGCUR_H8                (0xA0)
+#define XPOWERS_AXP202_INT_BAT_CHGCUR_L4                (0xA1)
+#define XPOWERS_AXP202_EXT_BAT_CHGCUR_H8                (0xA2)
+#define XPOWERS_AXP202_EXT_BAT_CHGCUR_L4                (0xA3)
+#define XPOWERS_AXP202_INT_BAT_DISCHGCUR_H8             (0xA4)
+#define XPOWERS_AXP202_INT_BAT_DISCHGCUR_L4             (0xA5)
+#define XPOWERS_AXP202_EXT_BAT_DISCHGCUR_H8             (0xA6)
+#define XPOWERS_AXP202_EXT_BAT_DISCHGCUR_L4             (0xA7)
+#define XPOWERS_AXP202_BAT_CHGCOULOMB3                  (0xB0)
+#define XPOWERS_AXP202_BAT_CHGCOULOMB2                  (0xB1)
+#define XPOWERS_AXP202_BAT_CHGCOULOMB1                  (0xB2)
+#define XPOWERS_AXP202_BAT_CHGCOULOMB0                  (0xB3)
+#define XPOWERS_AXP202_BAT_DISCHGCOULOMB3               (0xB4)
+#define XPOWERS_AXP202_BAT_DISCHGCOULOMB2               (0xB5)
+#define XPOWERS_AXP202_BAT_DISCHGCOULOMB1               (0xB6)
+#define XPOWERS_AXP202_BAT_DISCHGCOULOMB0               (0xB7)
+#define XPOWERS_AXP202_COULOMB_CTL                      (0xB8)
+#define XPOWERS_AXP202_BATT_PERCENTAGE                  (0xB9)
+
+#define XPOWERS_AXP202_BAT_POWERH8                      (0x70)
+#define XPOWERS_AXP202_BAT_POWERM8                      (0x71)
+#define XPOWERS_AXP202_BAT_POWERL8                      (0x72)
+
+#define XPOWERS_AXP202_BATT_VOLTAGE_STEP                (1.1F)
+#define XPOWERS_AXP202_BATT_DISCHARGE_CUR_STEP          (0.5F)
+#define XPOWERS_AXP202_BATT_CHARGE_CUR_STEP             (0.5F)
+#define XPOWERS_AXP202_ACIN_VOLTAGE_STEP                (1.7F)
+#define XPOWERS_AXP202_ACIN_CUR_STEP                    (0.625F)
+#define XPOWERS_AXP202_VBUS_VOLTAGE_STEP                (1.7F)
+#define XPOWERS_AXP202_VBUS_CUR_STEP                    (0.375F)
+#define XPOWERS_AXP202_INTERNAL_TEMP_STEP               (0.1F)
+#define XPOWERS_AXP202_APS_VOLTAGE_STEP                 (1.4F)
+#define XPOWERS_AXP202_TS_PIN_OUT_STEP                  (0.8F)
+
+#define XPOWERS_AXP202_LDO2_VOL_MIN                     (1800u)
+#define XPOWERS_AXP202_LDO2_VOL_MAX                     (3300u)
+#define XPOWERS_AXP202_LDO2_VOL_STEPS                   (100u)
+#define XPOWERS_AXP202_LDO2_VOL_BIT_MASK                (4u)
+
+#define XPOWERS_AXP202_LDO3_VOL_MIN                     (1800u)
+#define XPOWERS_AXP202_LDO3_VOL_MAX                     (3300u)
+#define XPOWERS_AXP202_LDO3_VOL_STEPS                   (100u)
+
+#define XPOWERS_AXP202_DC2_VOL_STEPS                    (25u)
+#define XPOWERS_AXP202_DC2_VOL_MIN                      (700u)
+#define XPOWERS_AXP202_DC2_VOL_MAX                      (3500u)
+
+#define XPOWERS_AXP202_DC3_VOL_STEPS                    (25u)
+#define XPOWERS_AXP202_DC3_VOL_MIN                      (700u)
+#define XPOWERS_AXP202_DC3_VOL_MAX                      (3500u)
+
+#define XPOWERS_AXP202_LDOIO_VOL_STEPS                  (100)
+#define XPOWERS_AXP202_LDOIO_VOL_MIN                    (1800)
+#define XPOWERS_AXP202_LDOIO_VOL_MAX                    (3300)
+
+
+#define XPOWERS_AXP202_SYS_VOL_STEPS                    (100)
+#define XPOWERS_AXP202_VOFF_VOL_MIN                     (2600)
+#define XPOWERS_AXP202_VOFF_VOL_MAX                     (3300)
+
+#define XPOWERS_AXP202_CHG_EXT_CURR_MIN                 (300)
+#define XPOWERS_AXP202_CHG_EXT_CURR_MAX                 (1000)
+#define XPOWERS_AXP202_CHG_EXT_CURR_STEP                (100)
+
+#define XPOWERS_AXP202_INERNAL_TEMP_OFFSET              (144.7)
+
+
+
+
+
+
+
+
+
+
+
+

buildroot/package/axp2101/src/XPowersLib/REG/AXP2101Constants.h

@@ -0,0 +1,243 @@
+#pragma once
+
+#define AXP2101_SLAVE_ADDRESS                            (0x34)
+
+#define XPOWERS_AXP2101_CHIP_ID                          (0x4A)
+#define XPOWERS_AXP2101_CHIP_ID_2                        (0x47)
+
+#define XPOWERS_AXP2101_STATUS1                          (0x00)
+#define XPOWERS_AXP2101_STATUS2                          (0x01)
+#define XPOWERS_AXP2101_IC_TYPE                          (0x03)
+
+
+#define XPOWERS_AXP2101_DATA_BUFFER1                     (0x04)
+#define XPOWERS_AXP2101_DATA_BUFFER2                     (0x05)
+#define XPOWERS_AXP2101_DATA_BUFFER3                     (0x06)
+#define XPOWERS_AXP2101_DATA_BUFFER4                     (0x07)
+#define XPOWERS_AXP2101_DATA_BUFFER_SIZE                 (4u)
+
+#define XPOWERS_AXP2101_COMMON_CONFIG                    (0x10)
+#define XPOWERS_AXP2101_BATFET_CTRL                      (0x12)
+#define XPOWERS_AXP2101_DIE_TEMP_CTRL                    (0x13)
+#define XPOWERS_AXP2101_MIN_SYS_VOL_CTRL                 (0x14)
+#define XPOWERS_AXP2101_INPUT_VOL_LIMIT_CTRL             (0x15)
+#define XPOWERS_AXP2101_INPUT_CUR_LIMIT_CTRL             (0x16)
+#define XPOWERS_AXP2101_RESET_FUEL_GAUGE                 (0x17)
+#define XPOWERS_AXP2101_CHARGE_GAUGE_WDT_CTRL            (0x18)
+
+
+#define XPOWERS_AXP2101_WDT_CTRL                         (0x19)
+#define XPOWERS_AXP2101_LOW_BAT_WARN_SET                 (0x1A)
+
+
+#define XPOWERS_AXP2101_PWRON_STATUS                     (0x20)
+#define XPOWERS_AXP2101_PWROFF_STATUS                    (0x21)
+#define XPOWERS_AXP2101_PWROFF_EN                        (0x22)
+#define XPOWERS_AXP2101_DC_OVP_UVP_CTRL                  (0x23)
+#define XPOWERS_AXP2101_VOFF_SET                         (0x24)
+#define XPOWERS_AXP2101_PWROK_SEQU_CTRL                  (0x25)
+#define XPOWERS_AXP2101_SLEEP_WAKEUP_CTRL                (0x26)
+#define XPOWERS_AXP2101_IRQ_OFF_ON_LEVEL_CTRL            (0x27)
+
+#define XPOWERS_AXP2101_FAST_PWRON_SET0                  (0x28)
+#define XPOWERS_AXP2101_FAST_PWRON_SET1                  (0x29)
+#define XPOWERS_AXP2101_FAST_PWRON_SET2                  (0x2A)
+#define XPOWERS_AXP2101_FAST_PWRON_CTRL                  (0x2B)
+
+#define XPOWERS_AXP2101_ADC_CHANNEL_CTRL                 (0x30)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST0                 (0x34)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST1                 (0x35)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST2                 (0x36)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST3                 (0x37)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST4                 (0x38)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST5                 (0x39)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST6                 (0x3A)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST7                 (0x3B)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST8                 (0x3C)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST9                 (0x3D)
+
+
+//XPOWERS INTERRUPT REGISTER
+#define XPOWERS_AXP2101_INTEN1                           (0x40)
+#define XPOWERS_AXP2101_INTEN2                           (0x41)
+#define XPOWERS_AXP2101_INTEN3                           (0x42)
+
+
+//XPOWERS INTERRUPT STATUS REGISTER
+#define XPOWERS_AXP2101_INTSTS1                          (0x48)
+#define XPOWERS_AXP2101_INTSTS2                          (0x49)
+#define XPOWERS_AXP2101_INTSTS3                          (0x4A)
+#define XPOWERS_AXP2101_INTSTS_CNT                       (3)
+
+#define XPOWERS_AXP2101_TS_PIN_CTRL                      (0x50)
+#define XPOWERS_AXP2101_TS_HYSL2H_SET                    (0x52)
+#define XPOWERS_AXP2101_TS_LYSL2H_SET                    (0x53)
+
+
+#define XPOWERS_AXP2101_VLTF_CHG_SET                     (0x54)
+#define XPOWERS_AXP2101_VHLTF_CHG_SET                    (0x55)
+#define XPOWERS_AXP2101_VLTF_WORK_SET                    (0x56)
+#define XPOWERS_AXP2101_VHLTF_WORK_SET                   (0x57)
+
+
+#define XPOWERS_AXP2101_JIETA_EN_CTRL                    (0x58)
+#define XPOWERS_AXP2101_JIETA_SET0                       (0x59)
+#define XPOWERS_AXP2101_JIETA_SET1                       (0x5A)
+#define XPOWERS_AXP2101_JIETA_SET2                       (0x5B)
+
+
+#define XPOWERS_AXP2101_IPRECHG_SET                      (0x61)
+#define XPOWERS_AXP2101_ICC_CHG_SET                      (0x62)
+#define XPOWERS_AXP2101_ITERM_CHG_SET_CTRL               (0x63)
+
+#define XPOWERS_AXP2101_CV_CHG_VOL_SET                   (0x64)
+
+#define XPOWERS_AXP2101_THE_REGU_THRES_SET               (0x65)
+#define XPOWERS_AXP2101_CHG_TIMEOUT_SET_CTRL             (0x67)
+
+#define XPOWERS_AXP2101_BAT_DET_CTRL                     (0x68)
+#define XPOWERS_AXP2101_CHGLED_SET_CTRL                  (0x69)
+
+#define XPOWERS_AXP2101_BTN_VOL_MIN                      (2600)
+#define XPOWERS_AXP2101_BTN_VOL_MAX                      (3300)
+#define XPOWERS_AXP2101_BTN_VOL_STEPS                    (100)
+
+
+#define XPOWERS_AXP2101_BTN_BAT_CHG_VOL_SET              (0x6A)
+
+
+#define XPOWERS_AXP2101_DC_ONOFF_DVM_CTRL                (0x80)
+#define XPOWERS_AXP2101_DC_FORCE_PWM_CTRL                (0x81)
+#define XPOWERS_AXP2101_DC_VOL0_CTRL                     (0x82)
+#define XPOWERS_AXP2101_DC_VOL1_CTRL                     (0x83)
+#define XPOWERS_AXP2101_DC_VOL2_CTRL                     (0x84)
+#define XPOWERS_AXP2101_DC_VOL3_CTRL                     (0x85)
+#define XPOWERS_AXP2101_DC_VOL4_CTRL                     (0x86)
+
+
+#define XPOWERS_AXP2101_LDO_ONOFF_CTRL0                  (0x90)
+#define XPOWERS_AXP2101_LDO_ONOFF_CTRL1                  (0x91)
+#define XPOWERS_AXP2101_LDO_VOL0_CTRL                    (0x92)
+#define XPOWERS_AXP2101_LDO_VOL1_CTRL                    (0x93)
+#define XPOWERS_AXP2101_LDO_VOL2_CTRL                    (0x94)
+#define XPOWERS_AXP2101_LDO_VOL3_CTRL                    (0x95)
+#define XPOWERS_AXP2101_LDO_VOL4_CTRL                    (0x96)
+#define XPOWERS_AXP2101_LDO_VOL5_CTRL                    (0x97)
+#define XPOWERS_AXP2101_LDO_VOL6_CTRL                    (0x98)
+#define XPOWERS_AXP2101_LDO_VOL7_CTRL                    (0x99)
+#define XPOWERS_AXP2101_LDO_VOL8_CTRL                    (0x9A)
+
+
+#define XPOWERS_AXP2101_BAT_PARAME                       (0xA1)
+#define XPOWERS_AXP2101_FUEL_GAUGE_CTRL                  (0xA2)
+#define XPOWERS_AXP2101_BAT_PERCENT_DATA                 (0xA4)
+
+// DCDC 1~5
+#define XPOWERS_AXP2101_DCDC1_VOL_MIN                    (1500)
+#define XPOWERS_AXP2101_DCDC1_VOL_MAX                    (3400)
+#define XPOWERS_AXP2101_DCDC1_VOL_STEPS                  (100u)
+
+#define XPOWERS_AXP2101_DCDC2_VOL1_MIN                  (500u)
+#define XPOWERS_AXP2101_DCDC2_VOL1_MAX                  (1200u)
+#define XPOWERS_AXP2101_DCDC2_VOL2_MIN                  (1220u)
+#define XPOWERS_AXP2101_DCDC2_VOL2_MAX                  (1540u)
+
+#define XPOWERS_AXP2101_DCDC2_VOL_STEPS1                 (10u)
+#define XPOWERS_AXP2101_DCDC2_VOL_STEPS2                 (20u)
+
+#define XPOWERS_AXP2101_DCDC2_VOL_STEPS1_BASE            (0u)
+#define XPOWERS_AXP2101_DCDC2_VOL_STEPS2_BASE            (71)
+
+
+#define XPOWERS_AXP2101_DCDC3_VOL1_MIN                  (500u)
+#define XPOWERS_AXP2101_DCDC3_VOL1_MAX                  (1200u)
+#define XPOWERS_AXP2101_DCDC3_VOL2_MIN                  (1220u)
+#define XPOWERS_AXP2101_DCDC3_VOL2_MAX                  (1540u)
+#define XPOWERS_AXP2101_DCDC3_VOL3_MIN                  (1600u)
+#define XPOWERS_AXP2101_DCDC3_VOL3_MAX                  (3400u)
+
+#define XPOWERS_AXP2101_DCDC3_VOL_MIN                    (500)
+#define XPOWERS_AXP2101_DCDC3_VOL_MAX                    (3400)
+
+#define XPOWERS_AXP2101_DCDC3_VOL_STEPS1                 (10u)
+#define XPOWERS_AXP2101_DCDC3_VOL_STEPS2                 (20u)
+#define XPOWERS_AXP2101_DCDC3_VOL_STEPS3                 (100u)
+
+#define XPOWERS_AXP2101_DCDC3_VOL_STEPS1_BASE            (0u)
+#define XPOWERS_AXP2101_DCDC3_VOL_STEPS2_BASE            (71)
+#define XPOWERS_AXP2101_DCDC3_VOL_STEPS3_BASE            (88)
+
+
+
+#define XPOWERS_AXP2101_DCDC4_VOL1_MIN                  (500u)
+#define XPOWERS_AXP2101_DCDC4_VOL1_MAX                  (1200u)
+#define XPOWERS_AXP2101_DCDC4_VOL2_MIN                  (1220u)
+#define XPOWERS_AXP2101_DCDC4_VOL2_MAX                  (1840u)
+
+#define XPOWERS_AXP2101_DCDC4_VOL_STEPS1                 (10u)
+#define XPOWERS_AXP2101_DCDC4_VOL_STEPS2                 (20u)
+
+#define XPOWERS_AXP2101_DCDC4_VOL_STEPS1_BASE            (0u)
+#define XPOWERS_AXP2101_DCDC4_VOL_STEPS2_BASE            (71)
+
+
+
+#define XPOWERS_AXP2101_DCDC5_VOL_1200MV                 (1200)
+#define XPOWERS_AXP2101_DCDC5_VOL_VAL                    (0x19)
+#define XPOWERS_AXP2101_DCDC5_VOL_MIN                    (1400)
+#define XPOWERS_AXP2101_DCDC5_VOL_MAX                    (3700)
+#define XPOWERS_AXP2101_DCDC5_VOL_STEPS                  (100u)
+
+#define XPOWERS_AXP2101_VSYS_VOL_THRESHOLD_MIN          (2600)
+#define XPOWERS_AXP2101_VSYS_VOL_THRESHOLD_MAX          (3300)
+#define XPOWERS_AXP2101_VSYS_VOL_THRESHOLD_STEPS        (100)
+
+// ALDO 1~4
+
+#define XPOWERS_AXP2101_ALDO1_VOL_MIN                    (500)
+#define XPOWERS_AXP2101_ALDO1_VOL_MAX                    (3500)
+#define XPOWERS_AXP2101_ALDO1_VOL_STEPS                  (100u)
+
+#define XPOWERS_AXP2101_ALDO2_VOL_MIN                    (500)
+#define XPOWERS_AXP2101_ALDO2_VOL_MAX                    (3500)
+#define XPOWERS_AXP2101_ALDO2_VOL_STEPS                  (100u)
+
+
+#define XPOWERS_AXP2101_ALDO3_VOL_MIN                    (500)
+#define XPOWERS_AXP2101_ALDO3_VOL_MAX                    (3500)
+#define XPOWERS_AXP2101_ALDO3_VOL_STEPS                  (100u)
+
+
+#define XPOWERS_AXP2101_ALDO4_VOL_MIN                    (500)
+#define XPOWERS_AXP2101_ALDO4_VOL_MAX                    (3500)
+#define XPOWERS_AXP2101_ALDO4_VOL_STEPS                  (100u)
+
+// BLDO 1~2
+
+#define XPOWERS_AXP2101_BLDO1_VOL_MIN                    (500)
+#define XPOWERS_AXP2101_BLDO1_VOL_MAX                    (3500)
+#define XPOWERS_AXP2101_BLDO1_VOL_STEPS                  (100u)
+
+#define XPOWERS_AXP2101_BLDO2_VOL_MIN                    (500)
+#define XPOWERS_AXP2101_BLDO2_VOL_MAX                    (3500)
+#define XPOWERS_AXP2101_BLDO2_VOL_STEPS                  (100u)
+
+// CPUSLDO
+
+#define XPOWERS_AXP2101_CPUSLDO_VOL_MIN                  (500)
+#define XPOWERS_AXP2101_CPUSLDO_VOL_MAX                  (1400)
+#define XPOWERS_AXP2101_CPUSLDO_VOL_STEPS                (50)
+
+
+// DLDO 1~2
+#define XPOWERS_AXP2101_DLDO1_VOL_MIN                  (500)
+#define XPOWERS_AXP2101_DLDO1_VOL_MAX                  (3400)
+#define XPOWERS_AXP2101_DLDO1_VOL_STEPS                (100u)
+
+#define XPOWERS_AXP2101_DLDO2_VOL_MIN                  (500)
+#define XPOWERS_AXP2101_DLDO2_VOL_MAX                  (3400)
+#define XPOWERS_AXP2101_DLDO2_VOL_STEPS                (100u)
+
+
+#define XPOWERS_AXP2101_CONVERSION(raw)                 (22.0 + (7274 - raw) / 20.0)
+

buildroot/package/axp2101/src/XPowersLib/REG/AXP216Constants.h

@@ -0,0 +1,95 @@
+#pragma once
+
+#define AXP216_SLAVE_ADDRESS                            (0x34)
+
+#define XPOWERS_AXP216_CHIP_ID                          (0x41)
+
+//CONTROL REGISTER
+#define XPOWERS_AXP216_STATUS                           (0x00)
+#define XPOWERS_AXP216_MODE_CHGSTATUS                   (0x01)
+#define XPOWERS_AXP216_DATA_BUFFER1                     (0x04)
+#define XPOWERS_AXP216_DATA_BUFFER2                     (0x05)
+#define XPOWERS_AXP216_DATA_BUFFER3                     (0x06)
+#define XPOWERS_AXP216_DATA_BUFFER4                     (0x07)
+#define XPOWERS_AXP216_DATA_BUFFER5                     (0x08)
+#define XPOWERS_AXP216_DATA_BUFFER6                     (0x09)
+#define XPOWERS_AXP216_DATA_BUFFER7                     (0x0A)
+#define XPOWERS_AXP216_DATA_BUFFER8                     (0x0B)
+#define XPOWERS_AXP216_DATA_BUFFER9                     (0x0C)
+#define XPOWERS_AXP216_DATA_BUFFERA                     (0x0D)
+#define XPOWERS_AXP216_DATA_BUFFERB                     (0x0E)
+#define XPOWERS_AXP216_DATA_BUFFERC                     (0x0F)
+
+#define XPOWERS_AXP216_IC_TYPE                          (0x03)
+
+#define XPOWERS_AXP216_DC12345_ALDO12_CTL               (0x10)
+#define XPOWERS_AXP216_LDO123_CTL                       (0x12)
+#define XPOWERS_AXP216_OUTPUT_CTL                       (0x13)
+#define XPOWERS_AXP216_ELDO1_VCTL                       (0x19)
+#define XPOWERS_AXP216_ELDO2_VCTL                       (0x1A)
+#define XPOWERS_AXP216_DCDC1_VCTL                       (0x21)
+#define XPOWERS_AXP216_DCDC2_VCTL                       (0x22)
+#define XPOWERS_AXP216_DCDC3_VCTL                       (0x23)
+
+#define XPOWERS_AXP216_DCDC4_VCTL                       (0x24)
+#define XPOWERS_AXP216_DCDC5_VCTL                       (0x25)
+#define XPOWERS_AXP216_DCDC23_VOLX                      (0x27)
+#define XPOWERS_AXP216_ALDO1_VCTL                       (0x28)
+#define XPOWERS_AXP216_ALDO2_VCTL                       (0x29)
+#define XPOWERS_AXP216_ALDO3_VCTL                       (0x2A)
+#define XPOWERS_AXP216_VBUS_IPSOUT                      (0x30)
+#define XPOWERS_AXP216_VOFF_SET                         (0x31)
+#define XPOWERS_AXP216_OFF_CTL                          (0x32)
+#define XPOWERS_AXP216_CHARGE1                          (0x33)
+#define XPOWERS_AXP216_CHARGE2                          (0x34)
+#define XPOWERS_AXP216_CHARGE3                          (0x35)
+#define XPOWERS_AXP216_PEK_SET                          (0x36)
+#define XPOWERS_AXP216_OFFLEVEL                         (0x37)
+#define XPOWERS_AXP216_VLTF_CHGSET                      (0x38)
+#define XPOWERS_AXP216_VHTF_CHGSET                      (0x39)
+#define XPOWERS_AXP216_DCDC_FREQ                        (0x3B)
+#define XPOWERS_AXP216_TLTF_DISCHGSET                   (0x3C)
+#define XPOWERS_AXP216_THTF_DISCHGSET                   (0x3D)
+#define XPOWERS_AXP216_DCDC_MODESET                     (0x80)
+#define XPOWERS_AXP216_ADC_CTL                          (0x82)
+#define XPOWERS_AXP216_ADC_SPEED                        (0x84)
+#define XPOWERS_AXP216_TS_ADC                           (0x85)
+#define XPOWERS_AXP216_TIMER_CTL                        (0x8A)
+#define XPOWERS_AXP216_HOTOVER_CTL                      (0x8F)
+
+//GPIO REGISTER
+#define XPOWERS_AXP216_GPIO1_CTL                        (0x92)
+#define XPOWERS_AXP216_GPIO1_LDO_CTL                    (0x93)
+#define XPOWERS_AXP216_GPIO01_STATUS                    (0x94)
+#define XPOWERS_AXP216_GPIO1_PULLDOWN_CTL               (0x97)
+
+//XPOWERS INTERRUPT REGISTER
+#define XPOWERS_AXP216_INTEN1                           (0x40)
+#define XPOWERS_AXP216_INTEN2                           (0x41)
+#define XPOWERS_AXP216_INTEN3                           (0x42)
+#define XPOWERS_AXP216_INTEN4                           (0x43)
+#define XPOWERS_AXP216_INTEN5                           (0x44)
+
+//XPOWERS INTERRUPT STATUS REGISTER
+#define XPOWERS_AXP216_INTSTS1                          (0x48)
+#define XPOWERS_AXP216_INTSTS2                          (0x49)
+#define XPOWERS_AXP216_INTSTS3                          (0x4A)
+#define XPOWERS_AXP216_INTSTS4                          (0x4B)
+#define XPOWERS_AXP216_INTSTS5                          (0x4C)
+
+//XPOWERS ADC DATA REGISTER
+#define XPOWERS_AXP216_INTERNAL_TEMP_H8                 (0x56)
+#define XPOWERS_AXP216_INTERNAL_TEMP_L4                 (0x57)
+#define XPOWERS_AXP216_TS_IN_H8                         (0x58)
+#define XPOWERS_AXP216_TS_IN_L4                         (0x59)
+#define XPOWERS_AXP216_BAT_VOLTAGE_H8                   (0x78)
+#define XPOWERS_AXP216_BAT_VOLTAGE_L4                   (0x79)
+#define XPOWERS_AXP216_BAT_CHGCURCUR_H8                 (0x7A)
+#define XPOWERS_AXP216_BAT_CHGCURCUR_L4                 (0x7B)
+#define XPOWERS_AXP216_BAT_DISCHGCUR_H8                 (0x7C)
+#define XPOWERS_AXP216_BAT_DISCHGCUR_L4                 (0x7D)
+#define XPOWERS_AXP216_FUEL_GAUGE_CTRL                  (0xB8)
+#define XPOWERS_AXP216_FUEL_GAUGE_REULST                (0xB9)
+#define XPOWERS_AXP216_BAT_CAPACITY_0                   (0xE0)
+#define XPOWERS_AXP216_BAT_CAPACITY_1                   (0xE1)
+#define XPOWERS_AXP216_BAT_LOW_WARNING_CTRL             (0xE6)

buildroot/package/axp2101/src/XPowersLib/REG/HUSB238Constants.h

@@ -0,0 +1,45 @@
+/**
+ *
+ * @license MIT License
+ *
+ * Copyright (c) 2022 lewis he
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * @file      HUSB238Constants.h
+ * @author    Lewis He (lewishe@outlook.com)
+ * @date      2024-07-24
+ *
+ */
+#pragma once
+
+#define HUSB238_SLAVE_ADDRESS                                    (0x8)
+
+#define HUSB238_PD_STATUS0                                       (0x0)
+#define HUSB238_PD_STATUS1                                       (0x1)
+#define HUSB238_SRC_PDO_5V                                       (0x2)
+#define HUSB238_SRC_PDO_9V                                       (0x3)
+#define HUSB238_SRC_PDO_12V                                      (0x4)
+#define HUSB238_SRC_PDO_15V                                      (0x5)
+#define HUSB238_SRC_PDO_18V                                      (0x6)
+#define HUSB238_SRC_PDO_20V                                      (0x7)
+#define HUSB238_SRC_PDO                                          (0x8)
+#define HUSB238_GO_COMMAND                                       (0x9)
+
+

buildroot/package/axp2101/src/XPowersLib/REG/SY6970Constants.h

@@ -0,0 +1,126 @@
+/**
+ *
+ * @license MIT License
+ *
+ * Copyright (c) 2022 lewis he
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * @file      SY6970Constants.h
+ * @author    Lewis He (lewishe@outlook.com)
+ * @date      2023-07-20
+ *
+ */
+#pragma once
+
+#define SY6970_SLAVE_ADDRESS                                    (0x6A)
+// https://www.ti.com/product/BQ25896
+#define BQ25896_SLAVE_ADDRESS                                   (0x6B)
+// https://www.sg-micro.com/cnproduct/SGM41511
+#define SGM41511_SLAVE_ADDRESS                                  (0x6B)
+
+#define SY6970_DEV_REV                                          (0x00)
+#define BQ25896_DEV_REV                                         (0x02)
+
+#define POWERS_SY6970_REG_00H                                   (0x00)
+#define POWERS_SY6970_REG_01H                                   (0x01)
+#define POWERS_SY6970_REG_02H                                   (0x02)
+#define POWERS_SY6970_REG_03H                                   (0x03)
+#define POWERS_SY6970_REG_04H                                   (0x04)
+#define POWERS_SY6970_REG_05H                                   (0x05)
+#define POWERS_SY6970_REG_06H                                   (0x06)
+#define POWERS_SY6970_REG_07H                                   (0x07)
+#define POWERS_SY6970_REG_08H                                   (0x08)
+#define POWERS_SY6970_REG_09H                                   (0x09)
+#define POWERS_SY6970_REG_0AH                                   (0x0A)
+// Read only STATUS REG
+#define POWERS_SY6970_REG_0BH                                   (0x0B)
+// Read only CHARGE IRQ REG
+#define POWERS_SY6970_REG_0CH                                   (0x0C)
+// Absolute VINDPM Threshold
+#define POWERS_SY6970_REG_0DH                                   (0x0D)
+// Read only BATTERY VOLTAGE
+#define POWERS_SY6970_REG_0EH                                   (0x0E)
+// Read only SYSTEM VOLTAGE
+#define POWERS_SY6970_REG_0FH                                   (0x0F)
+// Read only NTC PERCENTAGE
+#define POWERS_SY6970_REG_10H                                   (0x10)
+// Read only VBUS VOLTAGE
+#define POWERS_SY6970_REG_11H                                   (0x11)
+// Read only CHARGE CURRENT
+#define POWERS_SY6970_REG_12H                                   (0x12)
+// Read only VINDPM/IINDPM STATUS/CURR LIMIT SETTING 
+#define POWERS_SY6970_REG_13H                                   (0x13)
+// RESET REG
+#define POWERS_SY6970_REG_14H                                   (0x14)
+
+#define POWERS_SY6970_VBUS_MASK_VAL(val)                        (val & 0x7F)
+#define POWERS_SY6970_VBAT_MASK_VAL(val)                        (val & 0x7F)
+#define POWERS_SY6970_VSYS_MASK_VAL(val)                        (val & 0x7F)
+#define POWERS_SY6970_NTC_MASK_VAL(val)                         (val & 0x7F)
+
+#define POWERS_SY6970_VBUS_BASE_VAL                             (2600)
+#define POWERS_SY6970_VBAT_BASE_VAL                             (2304)
+#define POWERS_SY6970_VSYS_BASE_VAL                             (2304)
+#define POWERS_SY6970_NTC_BASE_VAL                              (21)
+
+#define POWERS_SY6970_VBUS_VOL_STEP                             (100)
+#define POWERS_SY6970_VBAT_VOL_STEP                             (20)
+#define POWERS_SY6970_VSYS_VOL_STEP                             (20)
+#define POWERS_SY6970_NTC_VOL_STEP                              (0.465)
+#define POWERS_SY6970_CHG_STEP_VAL                              (50)
+
+#define POWERS_SY6970_PRE_CHG_CUR_BASE                          (64)
+#define POWERS_SY6970_FAST_CHG_CUR_STEP                         (64)
+#define POWERS_SY6970_PRE_CHG_CUR_STEP                          (64)
+
+#define POWERS_FAST_CHG_CURRENT_MIN                             (0)
+#define POWERS_FAST_CHG_CURRENT_MAX                             (5056)
+
+#define POWERS_PRE_CHG_CURRENT_MIN                              (64)
+#define POWERS_PRE_CHG_CURRENT_MAX                              (1024)
+
+#define POWERS_SY6970_CHG_VOL_BASE                              (3840)
+#define POWERS_SY6970_CHG_VOL_STEP                              (16)
+#define POWERS_FAST_CHG_VOL_MIN                                 (3840)
+#define POWERS_FAST_CHG_VOL_MAX                                 (4608)
+
+#define POWERS_SY6970_SYS_VOL_STEPS                             (100)
+#define POWERS_SY6970_SYS_VOFF_VOL_MIN                          (3000)
+#define POWERS_SY6970_SYS_VOFF_VOL_MAX                          (3700)
+
+#define POWERS_SY6970_IN_CURRENT_STEP                           (50)
+#define POWERS_SY6970_IN_CURRENT_MIN                            (100)
+#define POWERS_SY6970_IN_CURRENT_MAX                            (3250)
+
+#define POWERS_SY6970_BOOTS_VOL_BASE                            (4550)
+#define POWERS_SY6970_BOOTS_VOL_STEP                            (64)
+#define POWERS_SY6970_BOOST_VOL_MIN                             (4550)
+#define POWERS_SY6970_BOOST_VOL_MAX                             (5510)
+
+#define POWERS_SY6970_IRQ_WTD_FAULT(x)                          (bool)(( x & 0xFF ) >> 7)
+#define POWERS_SY6970_IRQ_BOOST_FAULT(x)                        (bool)(( x & 0xFF ) >> 6)
+#define POWERS_SY6970_IRQ_CHG_FAULT(x)                          (bool)(( x & 0xFF ) >> 5)
+#define POWERS_SY6970_IRQ_BAT_FAULT(x)                          (bool)(( x & 0xFF ) >> 4)
+#define POWERS_SY6970_IRQ_NTC_FAULT(x)                          (bool)(( x & 0xFF ) & 0x03)
+
+#define POWERS_SY6970_VINDPM_VOL_BASE                           (4550)
+#define POWERS_SY6970_VINDPM_VOL_STEPS                          (100)
+#define POWERS_SY6970_VINDPM_VOL_MIN                            (3900)
+#define POWERS_SY6970_VINDPM_VOL_MAX                            (15300)

buildroot/package/axp2101/src/XPowersLib/XPowersCommon.tpp

@@ -0,0 +1,512 @@
+/**
+ *
+ * @license MIT License
+ *
+ * Copyright (c) 2022 lewis he
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * @file      XPowersCommon.h
+ * @author    Lewis He (lewishe@outlook.com)
+ * @date      2022-05-07
+ *
+ */
+
+
+#pragma once
+
+#include <stdint.h>
+
+#if defined(ARDUINO)
+#include <Wire.h>
+#elif defined(ESP_PLATFORM)
+#include "esp_log.h"
+#include "esp_err.h"
+#include <cstring>
+#include "esp_idf_version.h"
+#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5,0,0)) && defined(CONFIG_XPOWERS_ESP_IDF_NEW_API)
+#include "driver/i2c_master.h"
+#else
+#include "driver/i2c.h"
+#define XPOWERSLIB_I2C_MASTER_TX_BUF_DISABLE   0                          /*!< I2C master doesn't need buffer */
+#define XPOWERSLIB_I2C_MASTER_RX_BUF_DISABLE   0                          /*!< I2C master doesn't need buffer */
+#define XPOWERSLIB_I2C_MASTER_TIMEOUT_MS       1000
+#endif //ESP_IDF_VERSION
+
+
+#endif //ESP_PLATFORM
+
+#define XPOWERSLIB_I2C_MASTER_SPEED            400000
+
+
+#ifdef _BV
+#undef _BV
+#endif
+#define _BV(b)                          (1ULL << (uint64_t)(b))
+
+
+#ifndef constrain
+#define constrain(amt,low,high) ((amt)<(low)?(low):((amt)>(high)?(high):(amt)))
+#endif
+
+
+
+#define XPOWERS_ATTR_NOT_IMPLEMENTED    __attribute__((error("Not implemented")))
+#define IS_BIT_SET(val,mask)            (((val)&(mask)) == (mask))
+
+#if !defined(ARDUINO)
+#ifdef linux
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+#define log_e(__info,...)          printf("error :"  __info,##__VA_ARGS__)
+#define log_i(__info,...)          printf("info  :"  __info,##__VA_ARGS__)
+#define log_d(__info,...)          printf("debug :"  __info,##__VA_ARGS__)
+#else
+#define log_e(...)
+#define log_i(...)
+#define log_d(...)
+#endif
+
+#define LOW                 0x0
+#define HIGH                0x1
+
+//GPIO FUNCTIONS
+#define INPUT               0x01
+#define OUTPUT              0x03
+#define PULLUP              0x04
+#define INPUT_PULLUP        0x05
+#define PULLDOWN            0x08
+#define INPUT_PULLDOWN      0x09
+
+#define RISING              0x01
+#define FALLING             0x02
+#endif
+
+#ifndef ESP32
+#ifdef LOG_FILE_LINE_INFO
+#undef LOG_FILE_LINE_INFO
+#endif
+#define LOG_FILE_LINE_INFO __FILE__, __LINE__
+#ifndef log_e
+#define log_e(fmt, ...)     Serial.printf("[E][%s:%d] " fmt "\n", LOG_FILE_LINE_INFO, ##__VA_ARGS__)
+#endif
+#ifndef log_i
+#define log_i(fmt, ...)     Serial.printf("[I][%s:%d] " fmt "\n", LOG_FILE_LINE_INFO, ##__VA_ARGS__)
+#endif
+#ifndef log_d
+#define log_d(fmt, ...)     Serial.printf("[D][%s:%d] " fmt "\n", LOG_FILE_LINE_INFO, ##__VA_ARGS__)
+#endif
+#endif
+
+
+#if defined(NRF52840_XXAA) || defined(NRF52832_XXAA)
+#ifndef SDA
+#define SDA     (0xFF)
+#endif
+
+#ifndef SCL
+#define SCL     (0xFF)
+#endif
+#endif
+
+
+typedef int (*iic_fptr_t)(uint8_t devAddr, uint8_t regAddr, uint8_t *data, uint8_t len);
+
+template <class chipType>
+class XPowersCommon
+{
+
+public:
+
+#if defined(ARDUINO)
+    bool begin(TwoWire &w, uint8_t addr, int sda, int scl)
+    {
+        if (__has_init)return thisChip().initImpl();
+        __has_init = true;
+        __sda = sda;
+        __scl = scl;
+        __wire = &w;
+
+#if defined(NRF52840_XXAA) || defined(NRF52832_XXAA)
+        if (__sda != 0xFF && __scl != 0xFF) {
+            __wire->setPins(__sda, __scl);
+        }
+        __wire->begin();
+#elif defined(ARDUINO_ARCH_RP2040) || defined(ARDUINO_ARCH_STM32)
+        if (__sda != 0xFF && __scl != 0xFF) {
+            __wire->end();
+            __wire->setSDA(__sda);
+            __wire->setSCL(__scl);
+        }
+        __wire->begin();
+#elif defined(ARDUINO_ARCH_ESP32)
+        __wire->begin(__sda, __scl);
+#else
+        __wire->begin();
+#endif
+        __addr = addr;
+        return thisChip().initImpl();
+    }
+#elif defined(ESP_PLATFORM)
+
+
+#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5,0,0)) && defined(CONFIG_XPOWERS_ESP_IDF_NEW_API)
+
+    // * Using the new API of esp-idf 5.x, you need to pass the I2C BUS handle,
+    // * which is useful when the bus shares multiple devices.
+    bool begin(i2c_master_bus_handle_t i2c_dev_bus_handle, uint8_t addr)
+    {
+        log_i("Using ESP-IDF Driver interface.");
+        if (i2c_dev_bus_handle == NULL) return false;
+        if (__has_init)return thisChip().initImpl();
+
+        thisReadRegCallback = NULL;
+        thisWriteRegCallback = NULL;
+
+        /*
+            i2c_master_bus_config_t i2c_bus_config;
+            memset(&i2c_bus_config, 0, sizeof(i2c_bus_config));
+            i2c_bus_config.clk_source = I2C_CLK_SRC_DEFAULT;
+            i2c_bus_config.i2c_port = port_num;
+            i2c_bus_config.scl_io_num = (gpio_num_t)__scl;
+            i2c_bus_config.sda_io_num = (gpio_num_t)__sda;
+            i2c_bus_config.glitch_ignore_cnt = 7;
+
+            i2c_new_master_bus(&i2c_bus_config, &bus_handle);
+        */
+
+        bus_handle = i2c_dev_bus_handle;
+
+        i2c_device_config_t i2c_dev_conf = {
+            .dev_addr_length = I2C_ADDR_BIT_LEN_7,
+            .device_address = addr,
+            .scl_speed_hz = XPOWERSLIB_I2C_MASTER_SPEED,
+#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5,3,0))
+#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5,4,0))
+            // New fields since esp-idf-v5.3-beta1
+            .scl_wait_us = 0,
+#endif
+            .flags = {
+                . disable_ack_check = 0
+            }
+#endif
+        };
+
+        if (ESP_OK != i2c_master_bus_add_device(bus_handle,
+                                                &i2c_dev_conf,
+                                                &__i2c_device)) {
+            return false;
+        }
+
+        __has_init = thisChip().initImpl();
+
+        if (!__has_init) {
+            // Initialization failed, delete device
+            i2c_master_bus_rm_device(__i2c_device);
+        }
+        return __has_init;
+    }
+
+
+#else //ESP 4.X
+
+
+    bool begin(i2c_port_t port_num, uint8_t addr, int sda, int scl)
+    {
+        __i2c_num = port_num;
+        log_i("Using ESP-IDF Driver interface.");
+        if (__has_init)return thisChip().initImpl();
+        __sda = sda;
+        __scl = scl;
+        __addr = addr;
+        thisReadRegCallback = NULL;
+        thisWriteRegCallback = NULL;
+
+        i2c_config_t i2c_conf;
+        memset(&i2c_conf, 0, sizeof(i2c_conf));
+        i2c_conf.mode = I2C_MODE_MASTER;
+        i2c_conf.sda_io_num = sda;
+        i2c_conf.scl_io_num = scl;
+        i2c_conf.sda_pullup_en = GPIO_PULLUP_ENABLE;
+        i2c_conf.scl_pullup_en = GPIO_PULLUP_ENABLE;
+        i2c_conf.master.clk_speed = XPOWERSLIB_I2C_MASTER_SPEED;
+
+        /**
+         * @brief Without checking whether the initialization is successful,
+         * I2C may be initialized externally,
+         * so just make sure there is an initialization here.
+         */
+        i2c_param_config(__i2c_num, &i2c_conf);
+        i2c_driver_install(__i2c_num,
+                           i2c_conf.mode,
+                           XPOWERSLIB_I2C_MASTER_RX_BUF_DISABLE,
+                           XPOWERSLIB_I2C_MASTER_TX_BUF_DISABLE, 0);
+        __has_init = thisChip().initImpl();
+        return __has_init;
+    }
+#endif //ESP 5.X
+#endif //ESP_PLATFORM
+
+    bool begin(uint8_t addr, iic_fptr_t readRegCallback, iic_fptr_t writeRegCallback)
+    {
+        if (__has_init)return thisChip().initImpl();
+        __has_init = true;
+        thisReadRegCallback = readRegCallback;
+        thisWriteRegCallback = writeRegCallback;
+        __addr = addr;
+        return thisChip().initImpl();
+    }
+
+    int readRegister(uint8_t reg)
+    {
+        uint8_t val = 0;
+        return readRegister(reg, &val, 1) == -1 ? -1 : val;
+    }
+
+    int writeRegister(uint8_t reg, uint8_t val)
+    {
+        return writeRegister(reg, &val, 1);
+    }
+
+    int readRegister(uint8_t reg, uint8_t *buf, uint8_t length)
+    {
+        if (thisReadRegCallback) {
+            return thisReadRegCallback(__addr, reg, buf, length);
+        }
+#if defined(ARDUINO)
+        if (__wire) {
+            __wire->beginTransmission(__addr);
+            __wire->write(reg);
+            if (__wire->endTransmission() != 0) {
+                return -1;
+            }
+            __wire->requestFrom(__addr, length);
+            return __wire->readBytes(buf, length) == length ? 0 : -1;
+        }
+#elif defined(ESP_PLATFORM)
+
+#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5,0,0)) && defined(CONFIG_XPOWERS_ESP_IDF_NEW_API)
+        if (ESP_OK == i2c_master_transmit_receive(
+                    __i2c_device,
+                    (const uint8_t *)&reg,
+                    1,
+                    buf,
+                    length,
+                    -1)) {
+            return 0;
+        }
+#else //ESP_IDF_VERSION
+        if (ESP_OK == i2c_master_write_read_device(__i2c_num,
+                __addr,
+                (uint8_t *)&reg,
+                1,
+                buf,
+                length,
+                XPOWERSLIB_I2C_MASTER_TIMEOUT_MS / portTICK_PERIOD_MS)) {
+            return 0;
+        }
+#endif //ESP_IDF_VERSION
+#endif //ESP_PLATFORM
+        return -1;
+    }
+
+    int writeRegister(uint8_t reg, uint8_t *buf, uint8_t length)
+    {
+        if (thisWriteRegCallback) {
+            return thisWriteRegCallback(__addr, reg, buf, length);
+        }
+#if defined(ARDUINO)
+        if (__wire) {
+            __wire->beginTransmission(__addr);
+            __wire->write(reg);
+            __wire->write(buf, length);
+            return (__wire->endTransmission() == 0) ? 0 : -1;
+        }
+        return -1;
+#elif defined(ESP_PLATFORM)
+        uint8_t *write_buffer = (uint8_t *)malloc(sizeof(uint8_t) * (length + 1));
+        if (!write_buffer) {
+            return -1;
+        }
+        write_buffer[0] = reg;
+        memcpy(write_buffer + 1, buf, length);
+
+
+#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5,0,0)) && defined(CONFIG_XPOWERS_ESP_IDF_NEW_API)
+        if (ESP_OK != i2c_master_transmit(
+                    __i2c_device,
+                    write_buffer,
+                    length + 1,
+                    -1)) {
+            free(write_buffer);
+            return -1;
+        }
+#else //ESP_IDF_VERSION
+        if (ESP_OK != i2c_master_write_to_device(__i2c_num,
+                __addr,
+                write_buffer,
+                length + 1,
+                XPOWERSLIB_I2C_MASTER_TIMEOUT_MS / portTICK_PERIOD_MS)) {
+            free(write_buffer);
+            return -1;
+        }
+#endif //ESP_IDF_VERSION
+        free(write_buffer);
+        return 0;
+#endif //ESP_PLATFORM
+        return 0;
+    }
+
+
+    bool inline clrRegisterBit(uint8_t registers, uint8_t bit)
+    {
+        int val = readRegister(registers);
+        if (val == -1) {
+            return false;
+        }
+        return  writeRegister(registers, (val & (~_BV(bit)))) == 0;
+    }
+
+    bool inline setRegisterBit(uint8_t registers, uint8_t bit)
+    {
+        int val = readRegister(registers);
+        if (val == -1) {
+            return false;
+        }
+        return  writeRegister(registers, (val | (_BV(bit)))) == 0;
+    }
+
+    bool inline getRegisterBit(uint8_t registers, uint8_t bit)
+    {
+        int val = readRegister(registers);
+        if (val == -1) {
+            return false;
+        }
+        return val & _BV(bit);
+    }
+
+    uint16_t inline readRegisterH8L4(uint8_t highReg, uint8_t lowReg)
+    {
+        int h8 = readRegister(highReg);
+        int l4 = readRegister(lowReg);
+        if (h8 == -1 || l4 == -1)return 0;
+        return (h8 << 4) | (l4 & 0x0F);
+    }
+
+    uint16_t inline readRegisterH8L5(uint8_t highReg, uint8_t lowReg)
+    {
+        int h8 = readRegister(highReg);
+        int l5 = readRegister(lowReg);
+        if (h8 == -1 || l5 == -1)return 0;
+        return (h8 << 5) | (l5 & 0x1F);
+    }
+
+    uint16_t inline readRegisterH6L8(uint8_t highReg, uint8_t lowReg)
+    {
+        int h6 = readRegister(highReg);
+        int l8 = readRegister(lowReg);
+        if (h6 == -1 || l8 == -1)return 0;
+        return ((h6 & 0x3F) << 8) | l8;
+    }
+
+    uint16_t inline readRegisterH5L8(uint8_t highReg, uint8_t lowReg)
+    {
+        int h5 = readRegister(highReg);
+        int l8 = readRegister(lowReg);
+        if (h5 == -1 || l8 == -1)return 0;
+        return ((h5 & 0x1F) << 8) | l8;
+    }
+
+    /*
+     * CRTP Helper
+     */
+protected:
+
+    bool begin()
+    {
+#if defined(ARDUINO)
+        if (__has_init) return thisChip().initImpl();
+        __has_init = true;
+        if (__wire) {
+            log_i("SDA:%d SCL:%d", __sda, __scl);
+#if defined(NRF52840_XXAA) || defined(NRF52832_XXAA)
+            if (__sda != 0xFF && __scl != 0xFF) {
+                __wire->setPins(__sda, __scl);
+            }
+            __wire->begin();
+#elif defined(ARDUINO_ARCH_RP2040) || defined(ARDUINO_ARCH_STM32)
+            if (__sda != 0xFF && __scl != 0xFF) {
+                __wire->end();
+                __wire->setSDA(__sda);
+                __wire->setSCL(__scl);
+            }
+            __wire->begin();
+#elif defined(ARDUINO_ARCH_ESP32)
+            __wire->begin(__sda, __scl);
+#else
+            __wire->begin();
+#endif
+        }
+#endif  /*ARDUINO*/
+        return thisChip().initImpl();
+    }
+
+    void end()
+    {
+#if defined(ARDUINO)
+        if (__wire) {
+#if defined(ESP_IDF_VERSION)
+#if ESP_IDF_VERSION > ESP_IDF_VERSION_VAL(4,4,0)
+            __wire->end();
+#endif  /*ESP_IDF_VERSION*/
+#endif  /*ESP_IDF_VERSION*/
+        }
+#endif /*ARDUINO*/
+    }
+
+
+    inline const chipType &thisChip() const
+    {
+        return static_cast<const chipType &>(*this);
+    }
+
+    inline chipType &thisChip()
+    {
+        return static_cast<chipType &>(*this);
+    }
+
+protected:
+    bool        __has_init              = false;
+#if defined(ARDUINO)
+    TwoWire     *__wire                 = NULL;
+#elif defined(ESP_PLATFORM)
+    i2c_port_t  __i2c_num;
+#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5,0,0)) && defined(CONFIG_XPOWERS_ESP_IDF_NEW_API)
+    i2c_master_bus_handle_t  bus_handle;
+    i2c_master_dev_handle_t  __i2c_device;
+#endif //ESP_IDF_VERSION
+
+#endif //ESP_PLATFORM
+    int         __sda                   = -1;
+    int         __scl                   = -1;
+    uint8_t     __addr                  = 0xFF;
+    iic_fptr_t  thisReadRegCallback     = NULL;
+    iic_fptr_t  thisWriteRegCallback    = NULL;
+};