perf: reclaim NanoKVM cvifb memory

* board: reclaim NanoKVM cvifb memory

.gitignore

@@ -1,6 +1,14 @@
 *~
 *.swp
+*.o
+*.ko
+*.d
+# keep init.d directory
+!kvm/init.d/*
+!buildroot/board/cvitek/SG200X/overlay/etc/init.d/
+!buildroot/board/cvitek/SG200X/overlay/etc/init.d/*
 host-tools/
+host-tools
 *.sqfs
 build/tools/common/sd_tools/genimage.cfg.tmp
 fsbl/build/*
@@ -180,3 +188,238 @@ buildroot/board/cvitek/SG200X/overlay/mnt/system/sdk-release
 buildroot/board/cvitek/SG200X/overlay/mnt/system/auto.sh
 middleware/v2/mod_tmp/*
 cscope.out
+middleware/v2/3rdparty/inih/ini.d
+middleware/v2/3rdparty/inih/ini.o
+middleware/v2/component/isp/sensor/cv182x/gcore_gc4653/gc4653_cmos.d
+middleware/v2/component/isp/sensor/cv182x/gcore_gc4653/gc4653_cmos.o
+middleware/v2/component/isp/sensor/cv182x/gcore_gc4653/gc4653_sensor_ctl.d
+middleware/v2/component/isp/sensor/cv182x/gcore_gc4653/gc4653_sensor_ctl.o
+middleware/v2/component/isp/sensor/cv182x/ov_os04a10/os04a10_cmos.d
+middleware/v2/component/isp/sensor/cv182x/ov_os04a10/os04a10_cmos.o
+middleware/v2/component/isp/sensor/cv182x/ov_os04a10/os04a10_sensor_ctl.d
+middleware/v2/component/isp/sensor/cv182x/ov_os04a10/os04a10_sensor_ctl.o
+middleware/v2/lib/libsns_os04a10.a
+middleware/v2/lib/libsns_os04a10.so
+middleware/v2/modules/bin/src/cvi_bin.d
+middleware/v2/modules/bin/src/cvi_bin.o
+middleware/v2/modules/bin/src/md5.d
+middleware/v2/modules/bin/src/md5.o
+middleware/v2/modules/bin/src/rw_json.d
+middleware/v2/modules/bin/src/rw_json.o
+middleware/v2/modules/bin/src/vo_bin.d
+middleware/v2/modules/bin/src/vo_bin.o
+middleware/v2/modules/bin/src/vo_json_struct.d
+middleware/v2/modules/bin/src/vo_json_struct.o
+middleware/v2/modules/bin/src/vpss_bin.d
+middleware/v2/modules/bin/src/vpss_bin.o
+middleware/v2/modules/bin/src/vpss_json_struct.d
+middleware/v2/modules/bin/src/vpss_json_struct.o
+middleware/v2/modules/ive/src/cvi_ive.d
+middleware/v2/modules/ive/src/cvi_ive.o
+middleware/v2/modules/mipi_tx/src/mipi_tx.d
+middleware/v2/modules/mipi_tx/src/mipi_tx.o
+middleware/v2/modules/misc/src/cvi_misc.d
+middleware/v2/modules/misc/src/cvi_misc.o
+middleware/v2/modules/osdc/src/cmpr_canvas.d
+middleware/v2/modules/osdc/src/cmpr_canvas.o
+middleware/v2/modules/osdc/src/cvi_osdc.d
+middleware/v2/modules/osdc/src/cvi_osdc.o
+middleware/v2/modules/osdc/src/osd_cmpr.d
+middleware/v2/modules/osdc/src/osd_cmpr.o
+middleware/v2/modules/sys/src/cvi_base.d
+middleware/v2/modules/sys/src/cvi_base.o
+middleware/v2/modules/sys/src/cvi_sys.d
+middleware/v2/modules/sys/src/cvi_sys.o
+middleware/v2/modules/sys/src/cvi_thermal.d
+middleware/v2/modules/sys/src/cvi_thermal.o
+middleware/v2/modules/sys/src/cvi_tracer.d
+middleware/v2/modules/sys/src/cvi_tracer.o
+middleware/v2/modules/sys/src/cvi_vb.d
+middleware/v2/modules/sys/src/cvi_vb.o
+middleware/v2/modules/sys/src/devmem.d
+middleware/v2/modules/sys/src/devmem.o
+middleware/v2/modules/sys/src/hashmap.d
+middleware/v2/modules/sys/src/hashmap.o
+middleware/v2/modules/sys/src/peri.d
+middleware/v2/modules/sys/src/peri.o
+middleware/v2/modules/sys/src/sys_ioctl.d
+middleware/v2/modules/sys/src/sys_ioctl.o
+middleware/v2/modules/sys/src/vb_ioctl.d
+middleware/v2/modules/sys/src/vb_ioctl.o
+middleware/v2/modules/vdec/src/cvi_vdec.d
+middleware/v2/modules/vdec/src/cvi_vdec.o
+middleware/v2/modules/venc/src/cvi_venc.d
+middleware/v2/modules/venc/src/cvi_venc.o
+middleware/v2/modules/vpu/src/cvi_gdc_1822.d
+middleware/v2/modules/vpu/src/cvi_gdc_1822.o
+middleware/v2/modules/vpu/src/cvi_region.d
+middleware/v2/modules/vpu/src/cvi_region.o
+middleware/v2/modules/vpu/src/cvi_vi.d
+middleware/v2/modules/vpu/src/cvi_vi.o
+middleware/v2/modules/vpu/src/cvi_vo.d
+middleware/v2/modules/vpu/src/cvi_vo.o
+middleware/v2/modules/vpu/src/cvi_vpss.d
+middleware/v2/modules/vpu/src/cvi_vpss.o
+middleware/v2/modules/vpu/src/dump_register.d
+middleware/v2/modules/vpu/src/dump_register.o
+middleware/v2/modules/vpu/src/dwa_ioctl.d
+middleware/v2/modules/vpu/src/dwa_ioctl.o
+middleware/v2/modules/vpu/src/gdc_mesh_1822.d
+middleware/v2/modules/vpu/src/gdc_mesh_1822.o
+middleware/v2/modules/vpu/src/rgn_ioctl.d
+middleware/v2/modules/vpu/src/rgn_ioctl.o
+middleware/v2/modules/vpu/src/vi_ioctl.d
+middleware/v2/modules/vpu/src/vi_ioctl.o
+middleware/v2/modules/vpu/src/vo_ioctl.d
+middleware/v2/modules/vpu/src/vo_ioctl.o
+middleware/v2/modules/vpu/src/vpss_ioctl.d
+middleware/v2/modules/vpu/src/vpss_ioctl.o
+middleware/v2/sample/audio/aac_sample/cvi_audio_aac_adp.d
+middleware/v2/sample/audio/aac_sample/cvi_audio_aac_adp.o
+middleware/v2/sample/audio/cvi_audio_dl_adp.d
+middleware/v2/sample/audio/cvi_audio_dl_adp.o
+middleware/v2/sample/audio/cvi_audio_parse_param.d
+middleware/v2/sample/audio/cvi_audio_parse_param.o
+middleware/v2/sample/audio/cvi_sample_audio.d
+middleware/v2/sample/audio/cvi_sample_audio.o
+middleware/v2/sample/audio/sample_audio
+middleware/v2/sample/common/loadbmp.d
+middleware/v2/sample/common/loadbmp.o
+middleware/v2/sample/common/md5sum.d
+middleware/v2/sample/common/md5sum.o
+middleware/v2/sample/common/sample_common_bin.d
+middleware/v2/sample/common/sample_common_bin.o
+middleware/v2/sample/common/sample_common_isp.d
+middleware/v2/sample/common/sample_common_isp.o
+middleware/v2/sample/common/sample_common_peripheral.d
+middleware/v2/sample/common/sample_common_peripheral.o
+middleware/v2/sample/common/sample_common_platform.d
+middleware/v2/sample/common/sample_common_platform.o
+middleware/v2/sample/common/sample_common_region.d
+middleware/v2/sample/common/sample_common_region.o
+middleware/v2/sample/common/sample_common_sensor.d
+middleware/v2/sample/common/sample_common_sensor.o
+middleware/v2/sample/common/sample_common_sys.d
+middleware/v2/sample/common/sample_common_sys.o
+middleware/v2/sample/common/sample_common_vdec.d
+middleware/v2/sample/common/sample_common_vdec.o
+middleware/v2/sample/common/sample_common_venc.d
+middleware/v2/sample/common/sample_common_venc.o
+middleware/v2/sample/common/sample_common_vi.d
+middleware/v2/sample/common/sample_common_vi.o
+middleware/v2/sample/common/sample_common_vo.d
+middleware/v2/sample/common/sample_common_vo.o
+middleware/v2/sample/common/sample_common_vpss.d
+middleware/v2/sample/common/sample_common_vpss.o
+middleware/v2/sample/fisheye/sample_fisheye
+middleware/v2/sample/fisheye/sample_fisheye.d
+middleware/v2/sample/fisheye/sample_fisheye.o
+middleware/v2/sample/ir_auto/ir_auto
+middleware/v2/sample/ir_auto/ir_auto.d
+middleware/v2/sample/ir_auto/ir_auto.o
+middleware/v2/sample/ive/sample_16bitto8bit
+middleware/v2/sample/ive/sample_add
+middleware/v2/sample/ive/sample_and
+middleware/v2/sample/ive/sample_bernsen
+middleware/v2/sample/ive/sample_bgmodel
+middleware/v2/sample/ive/sample_cannyedge
+middleware/v2/sample/ive/sample_cannyhysedge
+middleware/v2/sample/ive/sample_csc
+middleware/v2/sample/ive/sample_dilate
+middleware/v2/sample/ive/sample_dma
+middleware/v2/sample/ive/sample_erode
+middleware/v2/sample/ive/sample_filter
+middleware/v2/sample/ive/sample_filterandcsc
+middleware/v2/sample/ive/sample_framediffmotion
+middleware/v2/sample/ive/sample_gmm
+middleware/v2/sample/ive/sample_gmm2
+middleware/v2/sample/ive/sample_gradfg
+middleware/v2/sample/ive/sample_hist
+middleware/v2/sample/ive/sample_integ
+middleware/v2/sample/ive/sample_lbp
+middleware/v2/sample/ive/sample_magandang
+middleware/v2/sample/ive/sample_map
+middleware/v2/sample/ive/sample_ncc
+middleware/v2/sample/ive/sample_normgrad
+middleware/v2/sample/ive/sample_or
+middleware/v2/sample/ive/sample_ordstatfilter
+middleware/v2/sample/ive/sample_query
+middleware/v2/sample/ive/sample_resize
+middleware/v2/sample/ive/sample_sad
+middleware/v2/sample/ive/sample_sobel
+middleware/v2/sample/ive/sample_stcandicorner
+middleware/v2/sample/ive/sample_sub
+middleware/v2/sample/ive/sample_thresh
+middleware/v2/sample/ive/sample_thresh_S16
+middleware/v2/sample/ive/sample_thresh_U16
+middleware/v2/sample/ive/sample_xor
+middleware/v2/sample/mipi_tx/lt9611/lt9611
+middleware/v2/sample/mipi_tx/lt9611/lt9611.d
+middleware/v2/sample/mipi_tx/lt9611/lt9611.o
+middleware/v2/sample/mipi_tx/sample_dsi
+middleware/v2/sample/mipi_tx/sample_dsi.d
+middleware/v2/sample/mipi_tx/sample_dsi.o
+middleware/v2/sample/osdc/sample_osdc
+middleware/v2/sample/osdc/sample_osdc.d
+middleware/v2/sample/osdc/sample_osdc.o
+middleware/v2/sample/overlay/sample_overlay
+middleware/v2/sample/overlay/sample_overlay.d
+middleware/v2/sample/overlay/sample_overlay.o
+middleware/v2/sample/region/sample_region
+middleware/v2/sample/region/sample_region.d
+middleware/v2/sample/region/sample_region.o
+middleware/v2/sample/sample_panel/sample_panel.d
+middleware/v2/sample/sample_panel/sample_panel.o
+middleware/v2/sample/scene_auto/sample_scene_auto
+middleware/v2/sample/scene_auto/src/core/cvi_scene.d
+middleware/v2/sample/scene_auto/src/core/cvi_scene.o
+middleware/v2/sample/scene_auto/src/core/cvi_scene_setparam.d
+middleware/v2/sample/scene_auto/src/core/cvi_scene_setparam.o
+middleware/v2/sample/scene_auto/src/sample/cvi_scene_decode.d
+middleware/v2/sample/scene_auto/src/sample/cvi_scene_decode.o
+middleware/v2/sample/scene_auto/src/sample/cvi_scene_loadparam.d
+middleware/v2/sample/scene_auto/src/sample/cvi_scene_loadparam.o
+middleware/v2/sample/scene_auto/src/sample/sample_scene.d
+middleware/v2/sample/scene_auto/src/sample/sample_scene.o
+middleware/v2/sample/scene_auto/src/sample/sample_scene_main.d
+middleware/v2/sample/scene_auto/src/sample/sample_scene_main.o
+middleware/v2/sample/scene_auto/tools/iniparser/src/dictionary.d
+middleware/v2/sample/scene_auto/tools/iniparser/src/dictionary.o
+middleware/v2/sample/scene_auto/tools/iniparser/src/iniparser.d
+middleware/v2/sample/scene_auto/tools/iniparser/src/iniparser.o
+middleware/v2/sample/sensor_test/sensor_test
+middleware/v2/sample/sensor_test/sensor_test.d
+middleware/v2/sample/sensor_test/sensor_test.o
+middleware/v2/sample/sensor_test/src/ae_test.d
+middleware/v2/sample/sensor_test/src/ae_test.o
+middleware/v2/sample/vdec/sample_vdec
+middleware/v2/sample/vdec/sample_vdec.d
+middleware/v2/sample/vdec/sample_vdec.o
+middleware/v2/sample/vdec/sample_vdec_asan
+middleware/v2/sample/vdec/src/sample_vdec_lib.d
+middleware/v2/sample/vdec/src/sample_vdec_lib.o
+middleware/v2/sample/vdec/src/sample_vdec_testcase.d
+middleware/v2/sample/vdec/src/sample_vdec_testcase.o
+middleware/v2/sample/vdecvo/sample_vdecvo
+middleware/v2/sample/vdecvo/sample_vdecvo.d
+middleware/v2/sample/vdecvo/sample_vdecvo.o
+middleware/v2/sample/venc/sample_vcodec
+middleware/v2/sample/venc/sample_vcodec.d
+middleware/v2/sample/venc/sample_vcodec.o
+middleware/v2/sample/venc/sample_vcodec_asan
+middleware/v2/sample/venc/sample_venc
+middleware/v2/sample/venc/sample_venc.d
+middleware/v2/sample/venc/sample_venc.o
+middleware/v2/sample/venc/sample_venc_asan
+middleware/v2/sample/venc/src/sample_venc_lib.d
+middleware/v2/sample/venc/src/sample_venc_lib.o
+middleware/v2/sample/venc/src/sample_venc_testcase.d
+middleware/v2/sample/venc/src/sample_venc_testcase.o
+middleware/v2/sample/vio/sample_vio
+middleware/v2/sample/vio/sample_vio.d
+middleware/v2/sample/vio/sample_vio.o
+middleware/v2/sample/vio/sample_vio_main.d
+middleware/v2/sample/vio/sample_vio_main.o
+osdrv/extdrv/wireless/.tmp_4261/
+middleware/v2/lib
+host-tools/

README.md

@@ -1,13 +1,696 @@
-# LicheeRV-Nano-Build
+# 构建 NanoKVM 镜像
 
-# how to build
+完整的 NanoKVM 镜像由两部分组成：
 
+1. `LicheeRV-Nano` 的 Linux 系统镜像。
+2. `NanoKVM APP`，也就是设备启动后运行的 KVM 应用、Web 前端、后端服务和硬件辅助组件。
+
+整体流程是：先编译 `LicheeRV-Nano Linux` 镜像，再编译 `NanoKVM APP`，最后把 `kvmapp` 合并进系统镜像。
+
+## 0. 路径约定
+
+为避免后续构建、复制和挂载命令中的路径混乱，本文固定使用下面的目录结构。所有源码都放在用户目录下的 `LicheeRV_NanoKVM` 文件夹中：
+
+```text
+~/LicheeRV_NanoKVM/
+├── LicheeRV-Nano-Build/  # SDK 和系统镜像构建目录
+└── NanoKVM/              # NanoKVM APP 源码目录
 ```
-git clone https://github.com/LicheeRV-Nano-Build --depth=1
-cd LicheeRV-Nano-Build
-wget https://sophon-file.sophon.cn/sophon-prod-s3/drive/23/03/07/16/host-tools.tar.gz
-tar xf host-tools.tar.gz
+
+先在终端里定义这几个固定路径变量，后续命令都基于它们执行：
+
+```shell
+export WORKDIR="$HOME/LicheeRV_NanoKVM"
+export SDK_DIR="$WORKDIR/LicheeRV-Nano-Build"
+export APP_DIR="$WORKDIR/NanoKVM"
+```
+
+首次构建前创建工作目录：
+
+```shell
+mkdir -p "$WORKDIR"
+```
+
+不要把 `LicheeRV-Nano-Build` 和 `NanoKVM` 分散到其他目录，否则后文的复制、合并镜像命令需要同步调整。新开终端后需要重新执行上面的变量定义。
+
+## 1. 构建 LicheeRV-Nano Linux 镜像
+
+### 1.1 源码和分支
+
+- SDK 仓库：<https://github.com/sipeed/LicheeRV-Nano-Build>
+- SDK 分支：`NanoKVM`
+- 工具链仓库：<https://github.com/sophgo/host-tools>
+
+`host-tools` 中包含 `riscv64-unknown-linux-musl-gcc`，后续编译 `NanoKVM APP` 的后端服务也会用到同一套工具链。
+
+### 1.2 拉取源码
+
+```shell
+cd "$WORKDIR"
+
+git clone -b NanoKVM https://github.com/sipeed/LicheeRV-Nano-Build --depth=1
+cd "$SDK_DIR"
+git clone https://github.com/sophgo/host-tools --depth=1
+```
+
+如果源码已经存在，可以跳过 clone，直接进入目录：
+
+```shell
+cd "$SDK_DIR"
+```
+
+### 1.3 编译系统镜像
+
+进入 SDK 目录并加载编译环境：
+
+```shell
+cd "$SDK_DIR"
 source build/cvisetup.sh
+```
+
+执行后会注册 `defconfig`、`build_all`、`clean_all` 等命令，并打印当前 SDK 支持的板型配置说明。
+
+选择 `LicheeRV Nano` 的板级配置：
+
+```shell
 defconfig sg2002_licheervnano_sd
+```
+
+如果要编译 A53 版本，可以改用：
+
+```shell
+defconfig sg2002_licheea53nano_sd
+```
+
+开始完整编译：
+
+```shell
 build_all
 ```
+
+`build_all` 会依次编译 `U-Boot`、`Kernel`、`ramdisk/rootfs`、驱动、第三方库、中间件，并打包最终镜像。
+
+如果需要从干净状态重新完整编译，可以执行：
+
+```shell
+cd "$SDK_DIR"
+source build/cvisetup.sh
+defconfig sg2002_licheervnano_sd
+clean_all
+build_all
+```
+
+不要在另一个 `build_all` 还在运行时执行 `clean_all`。
+
+### 1.4 WSL 下的 PATH 问题
+
+如果在 WSL 中编译，可能会遇到类似错误：
+
+```text
+Your PATH contains spaces, TABs, and/or newline (\n) characters.
+This doesn't work. Fix you PATH.
+make: *** [support/dependencies/dependencies.mk:27: dependencies] Error 1
+```
+
+这是因为 `PATH` 里混入了带空格的 Windows 路径，Buildroot 不允许 `PATH` 包含空格、Tab 或换行。可以在当前终端临时过滤掉这些路径后再重新编译：
+
+```shell
+export PATH="$(printf '%s' "$PATH" | tr ':' '\n' | grep -v '[[:space:]]' | paste -sd: -)"
+```
+
+### 1.5 编译产物
+
+编译成功后，产物通常位于：
+
+```shell
+"$SDK_DIR/install/soc_sg2002_licheervnano_sd/"
+```
+
+镜像文件通常在：
+
+```shell
+"$SDK_DIR/install/soc_sg2002_licheervnano_sd/images/"
+```
+
+常见产物包括：
+
+```text
+fip.bin
+boot.sd
+rootfs.sd
+system.sd
+upgrade.zip
+*.img
+```
+
+查看最新生成的整盘镜像：
+
+```shell
+ls -lh "$SDK_DIR"/install/soc_sg2002_licheervnano_sd/images/*.img
+```
+
+### 1.6 编译 minimal 镜像
+
+如果需要更小的 rootfs，可以选择 minimal 板型：
+
+```shell
+cd "$SDK_DIR"
+source build/cvisetup.sh
+defconfig sg2002_licheervnano_sd_minimal
+clean_all
+build_all
+```
+
+minimal 产物位于：
+
+```shell
+"$SDK_DIR/install/soc_sg2002_licheervnano_sd_minimal/"
+```
+
+minimal 镜像不预装 Python3、FRP 和 Tailscale，但保留 NanoKVM、SSH、mDNS、Bash 及基础网络功能。合并 APP 时需要显式指定 minimal 镜像：
+
+```shell
+./kvm/merge_nanokvm_app.sh \
+    -i install/soc_sg2002_licheervnano_sd_minimal/images/your-image-name.img
+```
+
+如果编译过程中停在下载进度位置，例如 `Buildroot` 正在下载 `Pillow`、`qt5base`、`qt5svg` 等源码包，通常是网络较慢，不一定是编译卡死。可以观察对应的临时下载文件大小是否仍在增长。
+
+如果首次构建在 `qt5svg` 或 `qt5base` 附近失败，可以先重新执行：
+
+```shell
+build_all
+```
+
+## 2. 构建 NanoKVM APP
+
+### 2.1 拉取源码
+
+```shell
+cd "$WORKDIR"
+git clone https://github.com/sipeed/NanoKVM.git --depth=1
+cd "$APP_DIR"
+```
+
+这里的 `kvmapp` 是 NanoKVM 设备上的应用目录，不是完整烧录镜像。完整系统镜像还需要依赖前面编译出的 `LicheeRV-Nano Linux` 镜像。
+
+`NanoKVM` 仓库的主要目录如下：
+
+```text
+NanoKVM/
+├── server/          # Go 后端服务
+├── web/             # 前端页面
+├── support/sg2002/  # kvm_system 等硬件辅助组件
+├── kvmapp/          # 本地应用包目录
+└── Makefile         # Docker builder 编译入口
+```
+
+最终 `kvmapp` 中至少需要这些关键内容：
+
+```text
+kvmapp/server/NanoKVM-Server
+kvmapp/server/dl_lib/
+kvmapp/server/web/
+kvmapp/kvm_system/kvm_system
+kvmapp/kvm_system/kvm_stream
+kvmapp/system/init.d/S95nanokvm
+```
+
+需要编译或更新的组件主要是：
+
+- `server/`：Go 后端，生成 `NanoKVM-Server`。
+- `web/`：前端页面，生成 `dist/` 后放入 `kvmapp/server/web/`。
+- `support/sg2002/kvm_system`：硬件辅助进程，生成 `kvm_system`。
+
+通常不需要单独编译的内容：
+
+- `kvmapp/system/init.d/`：启动脚本，直接复制。
+- `kvmapp/picoclaw/`：运行时配置和技能文件，`picoclaw` 二进制由设备侧安装或下载逻辑处理。
+- `kvmapp/jpg_stream/`：旧版本升级兼容文件，保留即可。
+- `tools/logo_generator/`：Python 辅助脚本，不参与 `kvmapp` 主流程编译。
+
+按需编译的内容：
+
+- `support/sg2002/kvm_vision`：只有修改图像采集或编码动态库时才需要重新编译。
+- `tools/nanokvm_update_edid`：EDID 更新工具。如果后续从 SDK 镜像挂载目录里的 `mnt/system/tool/` 补齐，可以不重新编译。
+
+### 2.2 准备 Go 环境
+
+`server/` 是 Go 后端项目，编译 `NanoKVM-Server` 需要本机安装 Go。项目 `server/go.mod` 使用：
+
+```go
+go 1.24.0
+```
+
+先检查当前电脑是否已经有 Go：
+
+```shell
+which go
+go version
+```
+
+期望 Go 版本为 `1.24.0` 或更高，例如：
+
+```text
+/usr/local/go/bin/go
+go version go1.24.0 linux/amd64
+```
+
+如果提示 `go: command not found`，或者版本低于 `1.24.0`，可以安装官方 Go：
+
+```shell
+cd /tmp
+wget https://go.dev/dl/go1.24.0.linux-amd64.tar.gz
+sudo rm -rf /usr/local/go
+sudo tar -C /usr/local -xzf go1.24.0.linux-amd64.tar.gz
+
+echo 'export PATH=/usr/local/go/bin:$PATH' >> ~/.bashrc
+source ~/.bashrc
+hash -r
+
+which go
+go version
+```
+
+如果 `which go` 指向 `/usr/bin/go`，或者执行 `go mod tidy` 时出现：
+
+```text
+invalid go version '1.24.0': must match format 1.23
+```
+
+说明当前 Go 太旧，或者用到了 Ubuntu 自带的 `gccgo`。确认 `/usr/local/go/bin` 已经排在 `PATH` 前面，然后重新执行：
+
+```shell
+hash -r
+go version
+```
+
+如果 Go 依赖下载很慢，可以设置代理：
+
+```shell
+go env -w GOPROXY=https://goproxy.cn,direct
+go env -w GOSUMDB=sum.golang.google.cn
+```
+
+### 2.3 准备 server 编译依赖
+
+除了 Go，`server/build.sh` 还需要：
+
+- `patchelf`
+- `riscv64-unknown-linux-musl-gcc`
+
+检查依赖：
+
+```shell
+which patchelf
+which riscv64-unknown-linux-musl-gcc
+```
+
+安装 `patchelf`：
+
+```shell
+sudo apt update
+sudo apt install -y patchelf
+```
+
+如果 RISC-V 工具链没有加入 `PATH`，可以使用 SDK 里的 `host-tools`：
+
+```shell
+export PATH="$SDK_DIR/host-tools/gcc/riscv64-linux-musl-x86_64/bin:$PATH"
+
+which riscv64-unknown-linux-musl-gcc
+riscv64-unknown-linux-musl-gcc -v
+```
+
+### 2.4 编译后端 server
+
+推荐使用仓库里的脚本，因为它会自动设置 `RPATH`：
+
+```shell
+cd "$APP_DIR/server"
+go mod tidy
+./build.sh
+```
+
+成功后生成：
+
+```text
+server/NanoKVM-Server
+```
+
+确认架构和 `RPATH`：
+
+```shell
+file NanoKVM-Server
+patchelf --print-rpath NanoKVM-Server
+```
+
+期望输出包含：
+
+```text
+ELF 64-bit ... RISC-V ...
+$ORIGIN/dl_lib
+```
+
+如果看到类似警告：
+
+```text
+warning: libopencv_video.so.409, needed by .../libkvm.so, not found
+```
+
+但同时看到：
+
+```text
+[SUCCESS] Binary 'NanoKVM-Server' created successfully.
+[DONE] Build script completed successfully!
+```
+
+说明 `server` 已经编译成功。这个警告表示本机交叉链接时没有找到某个运行时库，后续需要确认设备或 `kvmapp/server/dl_lib` 中有对应库。
+
+把后端放入本地 `kvmapp`：
+
+```shell
+cd "$APP_DIR"
+mkdir -p kvmapp/server
+cp server/NanoKVM-Server kvmapp/server/NanoKVM-Server
+cp -a server/dl_lib kvmapp/server/
+```
+
+### 2.5 编译前端 web
+
+进入前端目录：
+
+```shell
+cd "$APP_DIR/web"
+pnpm install
+pnpm build
+```
+
+如果执行 `pnpm install` 时报错：
+
+```text
+ERROR packages field missing or empty
+```
+
+说明当前 `pnpm` 版本识别到了 `web/pnpm-workspace.yaml`，但这个文件里缺少 `packages` 字段。可以给 `pnpm-workspace.yaml` 补上当前目录作为 workspace 包：
+
+```yaml
+packages:
+  - "."
+
+allowBuilds:
+  bufferutil: true
+  es5-ext: true
+  esbuild: true
+  msw: true
+  utf-8-validate: true
+```
+
+修改后重新执行：
+
+```shell
+pnpm install
+pnpm build
+```
+
+成功后生成：
+
+```text
+web/dist
+```
+
+放入本地 `kvmapp`：
+
+```shell
+cd "$APP_DIR/web"
+rm -rf "$APP_DIR/kvmapp/server/web"
+mkdir -p "$APP_DIR/kvmapp/server"
+cp -a dist "$APP_DIR/kvmapp/server/web"
+```
+
+检查前端文件：
+
+```shell
+ls "$APP_DIR/kvmapp/server/web"
+ls "$APP_DIR/kvmapp/server/web/assets"
+```
+
+应包含：
+
+```text
+index.html
+assets/
+sipeed.ico
+```
+
+### 2.6 编译 support 组件
+
+仓库顶层 `Makefile` 使用 Docker builder 编译 support 组件，需要 Docker 已安装并运行。
+
+检查 Docker：
+
+```shell
+docker --version
+```
+
+构建 builder 镜像：
+
+```shell
+cd "$APP_DIR"
+make builder-image
+```
+
+编译 support：
+
+```shell
+make support
+```
+
+`make support` 会在 Docker 中使用 `MaixCDK` 编译 `support/sg2002/kvm_system`，并执行：
+
+```text
+./build kvm_system
+./build kvm_system add_to_kvmapp
+```
+
+生成或更新：
+
+```text
+kvmapp/kvm_system/kvm_system
+```
+
+如果修改过图像采集或编码相关动态库，可以按需编译 `kvm_vision`：
+
+```shell
+cd "$APP_DIR/support/sg2002"
+./build kvm_vision
+./build kvm_vision add_to_kvmapp
+```
+
+这会把 `kvm_vision_test/dist/kvm_vision_test_release/dl_lib/` 更新到 `kvmapp/server/dl_lib/`。没有修改这部分时，通常直接使用仓库或镜像中已有的 `dl_lib/` 即可。
+
+注意：顶层 `make all` 等于：
+
+```text
+make app
+make support
+```
+
+但是 `make all` 不会编译前端 `web`，并且 `make app` 没有执行 `patchelf --add-rpath '$ORIGIN/dl_lib'`。因此 `server` 更推荐使用 `server/build.sh` 编译。
+
+### 2.7 可选：编译 EDID 更新工具
+
+如果不从 SDK 镜像挂载目录里的 `mnt/system/tool/` 复制 EDID 工具，可以手动编译：
+
+```shell
+cd "$APP_DIR/tools/nanokvm_update_edid"
+make
+
+cd "$APP_DIR"
+mkdir -p kvmapp/system/tool
+cp tools/nanokvm_update_edid/nanokvm_update_edid kvmapp/system/tool/
+cp tools/nanokvm_update_edid/E21_NanoKVM.bin kvmapp/system/tool/
+```
+
+如果板子烧录的是当前 SDK 编译出的镜像，更推荐后续从 `mountpoint` 补齐，避免工具版本和镜像不一致。
+
+### 2.8 补充 version 文件
+
+在 `kvmapp` 目录中写入应用版本号：
+
+```shell
+cd "$APP_DIR/kvmapp"
+echo 2.4.3 > version
+```
+
+### 2.9 检查 kvmapp 文件
+
+构建完后的 `kvmapp` 目录应该包含以下关键文件。不同版本的文件数量可能略有差异，但这些核心路径应当存在：
+
+```text
+kvmapp
+├── jpg_stream
+│   ├── S95nanokvm
+│   └── jpg_stream
+├── kvm_new_app
+├── kvm_system
+│   ├── kvm_stream
+│   └── kvm_system
+├── picoclaw
+│   ├── AGENT.md
+│   ├── AGENT_KVM.md
+│   └── skills
+│       └── kvm-control
+├── server
+│   ├── NanoKVM-Server
+│   ├── dl_lib
+│   └── web
+│       ├── assets
+│       ├── index.html
+│       ├── mockServiceWorker.js
+│       └── sipeed.ico
+├── system
+│   ├── init.d
+│   │   ├── S00kmod
+│   │   ├── S01fs
+│   │   ├── S03usbdev
+│   │   ├── S03usbhid
+│   │   ├── S15kvmhwd
+│   │   ├── S30eth
+│   │   ├── S30wifi
+│   │   ├── S50avahi-daemon
+│   │   ├── S50ssdpd
+│   │   ├── S50sshd
+│   │   ├── S80dnsmasq
+│   │   ├── S95nanokvm
+│   │   ├── S96picoclaw
+│   │   └── S98tailscaled
+│   ├── ko
+│   │   └── soph_mipi_rx.ko
+│   └── update-nanokvm.py
+└── version
+```
+
+可以用下面的命令快速检查关键文件：
+
+```shell
+test -x "$APP_DIR/kvmapp/server/NanoKVM-Server"
+test -d "$APP_DIR/kvmapp/server/dl_lib"
+test -f "$APP_DIR/kvmapp/server/web/index.html"
+test -x "$APP_DIR/kvmapp/kvm_system/kvm_system"
+test -f "$APP_DIR/kvmapp/system/init.d/S95nanokvm"
+test -f "$APP_DIR/kvmapp/version"
+```
+
+## 3. 合并系统镜像和 NanoKVM APP
+
+SDK 的 `kvm/merge_nanokvm_app.sh` 脚本可以自动完成合并流程，包括：
+
+- 从 `NanoKVM/kvmapp` 复制应用文件到 SDK 的 `kvm/kvmapp`。
+- 自动选择最新生成的原始 `.img`，或者使用你手动指定的镜像。
+- 默认复制出一个新的 `*-nanokvm.img`，只修改这个输出镜像，不原地修改原始镜像。
+- 挂载镜像的 ext4 分区。
+- 写入 `kvmapp`、内核模块、启动脚本、默认数据和默认 KVM 配置；普通镜像还会写入 `frpc`、`tailscale` 和 `tailscaled`。
+- 每个关键步骤后检查挂载状态或目标文件，并校验第二分区之前的 boot 区域没有变化；失败时打印具体失败步骤并终止。
+- 写入完成后自动卸载镜像。
+
+### 3.1 默认用法
+
+确认目录结构符合本文约定：
+
+```text
+~/LicheeRV_NanoKVM/
+├── LicheeRV-Nano-Build/
+└── NanoKVM/
+```
+
+然后进入 SDK 目录执行：
+
+```shell
+cd "$SDK_DIR"
+./kvm/merge_nanokvm_app.sh
+```
+
+默认情况下，脚本会：
+
+- 从 `"$APP_DIR/kvmapp"` 复制应用文件。
+- 使用 `"$SDK_DIR/install/soc_sg2002_licheervnano_sd/images/"` 中最新的原始 `.img`。
+- 生成同目录下的 `*-nanokvm.img` 作为输出镜像。
+- 使用 `"$SDK_DIR/mountpoint"` 作为临时挂载目录。
+
+执行完成后，终端会打印已经写入 NanoKVM APP 的镜像路径，例如：
+
+```text
+NanoKVM APP has been merged into:
+/home/xxx/LicheeRV_NanoKVM/LicheeRV-Nano-Build/install/soc_sg2002_licheervnano_sd/images/xxx-nanokvm.img
+```
+
+把这个 `.img` 烧录到 SD 卡即可。
+
+### 3.2 指定镜像文件
+
+如果你不想使用最新镜像，可以用 `-i` 指定某一个 `.img`：
+
+```shell
+cd "$SDK_DIR"
+./kvm/merge_nanokvm_app.sh -i install/soc_sg2002_licheervnano_sd/images/your-image-name.img
+```
+
+脚本默认会生成 `your-image-name-nanokvm.img`。如果想指定输出路径，可以使用 `-o`：
+
+```shell
+./kvm/merge_nanokvm_app.sh \
+    -i install/soc_sg2002_licheervnano_sd/images/your-image-name.img \
+    -o install/soc_sg2002_licheervnano_sd/images/your-output-name.img
+```
+
+如果输出镜像已经存在，需要加 `-f` 覆盖：
+
+```shell
+./kvm/merge_nanokvm_app.sh -i your-image-name.img -o your-output-name.img -f
+```
+
+也可以使用绝对路径：
+
+```shell
+./kvm/merge_nanokvm_app.sh -i "$SDK_DIR/install/soc_sg2002_licheervnano_sd/images/your-image-name.img"
+```
+
+### 3.3 指定 NanoKVM 源码目录
+
+如果 `NanoKVM` 源码没有放在 `~/LicheeRV_NanoKVM/NanoKVM`，可以用 `-a` 指定：
+
+```shell
+cd "$SDK_DIR"
+./kvm/merge_nanokvm_app.sh -a /path/to/NanoKVM
+```
+
+不过为了减少路径错误，仍然推荐按本文约定放置源码。
+
+### 3.4 使用已有的 SDK kvm/kvmapp
+
+如果你已经手动准备好了 `"$SDK_DIR/kvm/kvmapp"`，不想让脚本重新从 `NanoKVM/kvmapp` 覆盖它，可以加 `--skip-copy-kvmapp`：
+
+```shell
+cd "$SDK_DIR"
+./kvm/merge_nanokvm_app.sh --skip-copy-kvmapp
+```
+
+这种方式会直接使用现有的 `kvm/kvmapp` 写入镜像。
+
+### 3.5 查看脚本帮助
+
+脚本支持的参数可以通过 `--help` 查看：
+
+```shell
+cd "$SDK_DIR"
+./kvm/merge_nanokvm_app.sh --help
+```
+
+### 3.6 注意事项
+
+- 执行脚本前，先确保第 1 节的系统镜像已经编译完成。
+- 执行脚本前，先确保第 2 节的 `NanoKVM/kvmapp` 已经准备完整。
+- 脚本会覆盖 SDK 目录下的 `kvm/kvmapp`，除非使用 `--skip-copy-kvmapp`。
+- 脚本不会原地修改输入 `.img`，而是生成新的输出镜像；烧录时请使用脚本最后打印的 `*-nanokvm.img`。
+- 如果脚本提示 `mountpoint` 目录已经挂载，先执行 `umount "$SDK_DIR/mountpoint"` 后再重试。

build/Makefile

@@ -543,6 +543,10 @@ br-rootfs-prepare:export CROSS_COMPILE_SDK=$(patsubst "%",%,$(CONFIG_CROSS_COMPI
 br-rootfs-prepare:
 	$(call print_target)
 	# copy ko and mmf libs
+	${Q}rm -rf $(BR_OVERLAY_DIR)
+	${Q}mkdir -p $(BR_OVERLAY_DIR)
+	${Q}cp -a $(BR_BASE_OVERLAY_DIR)/. $(BR_OVERLAY_DIR)/
+	${Q}rm -rf $(BR_OVERLAY_DIR)/mnt/system
 	${Q}mkdir -p $(BR_OVERLAY_DIR)/mnt/system
 	${Q}cp -arf ${SYSTEM_OUT_DIR}/* $(BR_OVERLAY_DIR)/mnt/system/
 	# strip
@@ -550,16 +554,16 @@ br-rootfs-prepare:
 	${Q}find $(BR_OVERLAY_DIR) -name "*.so*" -type f -printf 'striping %p\n' -exec $(CROSS_COMPILE_KERNEL)strip --strip-all {} \;
 	${Q}find $(BR_OVERLAY_DIR) -executable -type f ! -name "*.sh" ! -path "*etc*" ! -path "*.ko" -printf 'striping %p\n' -exec $(CROSS_COMPILE_SDK)strip --strip-all {} 2>/dev/null \;
 
-br-rootfs-pack:export TARGET_OUTPUT_DIR=$(BR_DIR)/output/$(BR_BOARD)
+br-rootfs-pack:export TARGET_OUTPUT_DIR=$(BR_OUTPUT_DIR)
 br-rootfs-pack:
 	$(call print_target)
-	${Q}$(MAKE) -C $(BR_DIR) $(BR_DEFCONFIG) BR2_TOOLCHAIN_EXTERNAL_PATH=$(CROSS_COMPILE_PATH)
-	${Q}$(MAKE) -j${NPROC} -C $(BR_DIR) source
-	${Q}$(MAKE) -j${NPROC} -C $(BR_DIR)
+	${Q}$(MAKE) -C $(BR_DIR) O=$(TARGET_OUTPUT_DIR) $(BR_DEFCONFIG) BR2_DEFCONFIG=$(BR2_DEFCONFIG) BR2_ROOTFS_OVERLAY=$(BR_OVERLAY_DIR) BR2_TOOLCHAIN_EXTERNAL_PATH=$(CROSS_COMPILE_PATH)
+	${Q}$(MAKE) -j${NPROC} -C $(BR_DIR) O=$(TARGET_OUTPUT_DIR) BR2_ROOTFS_OVERLAY=$(BR_OVERLAY_DIR) source
+	${Q}$(MAKE) -j${NPROC} -C $(BR_DIR) O=$(TARGET_OUTPUT_DIR) BR2_ROOTFS_OVERLAY=$(BR_OVERLAY_DIR)
 	# ${Q}rm -rf $(BR_ROOTFS_DIR)/*
 	# copy rootfs to rawimg dir
-	${Q}cp $(BR_DIR)/output/images/rootfs.ext4 $(OUTPUT_DIR)/rawimages/rootfs.$(STORAGE_TYPE)
-	${Q}tar zcvf $(OUTPUT_DIR)/licheervnano-drivers.tar.gz $(BR_DIR)/output/target/mnt
+	${Q}cp $(TARGET_OUTPUT_DIR)/images/rootfs.ext4 $(OUTPUT_DIR)/rawimages/rootfs.$(STORAGE_TYPE)
+	${Q}tar zcvf $(OUTPUT_DIR)/licheervnano-drivers.tar.gz $(TARGET_OUTPUT_DIR)/target/mnt
 	$(call raw2cimg ,rootfs.$(STORAGE_TYPE))
 
 ifeq ($(CONFIG_BUILDROOT_FS),y)

build/boards/default/dts/sg200x/soph_base.dtsi

@@ -156,21 +156,21 @@
 		compatible = "cvitek,cvi-pwm";
 		reg = <0x0 0x3060000 0x0 0x1000>;
 		clocks = <&clk CV181X_CLK_PWM>;
-		#pwm-cells = <1>;
+		#pwm-cells = <4>;
 	};
 
 	pwm1: pwm@3061000 {
 		compatible = "cvitek,cvi-pwm";
 		reg = <0x0 0x3061000 0x0 0x1000>;
 		clocks = <&clk CV181X_CLK_PWM>;
-		#pwm-cells = <2>;
+		#pwm-cells = <4>;
 	};
 
 	pwm2: pwm@3062000 {
 		compatible = "cvitek,cvi-pwm";
 		reg = <0x0 0x3062000 0x0 0x1000>;
 		clocks = <&clk CV181X_CLK_PWM>;
-		#pwm-cells = <3>;
+		#pwm-cells = <4>;
 	};
 
 	pwm3: pwm@3063000 {
@@ -233,6 +233,7 @@
 		clocks = <&clk CV181X_CLK_SPI>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		bias-pull-up;
 	};
 
 	spi3:spi3@041B0000 {
@@ -865,13 +866,13 @@
 
 			trips {
 				soc_thermal_trip_0: soc_thermal_trip_0 {
-					temperature = <100000>; /* millicelsius */
+					temperature = <110000>; /* millicelsius */
 					hysteresis = <5000>; /* millicelsius */
 					type = "passive";
 				};
 
 				soc_thermal_trip_1: soc_thermal_trip_1 {
-					temperature = <110000>; /* millicelsius */
+					temperature = <120000>; /* millicelsius */
 					hysteresis = <5000>; /* millicelsius */
 					type = "passive";
 				};

build/boards/sg200x/sg2002_licheea53nano_sd/config.json

@@ -0,0 +1,8 @@
+{
+    "ddr_cfg_list": [
+        "ddr3_1866_x16",
+        "ddr3_2133_x16",
+        "ddr_auto_x16"
+    ],
+    "board_information": "CA53"
+}

build/boards/sg200x/sg2002_licheea53nano_sd/dts_arm/sg2002_licheea53nano_sd.dts

@@ -0,0 +1,185 @@
+/dts-v1/;
+#include "soph_base_arm.dtsi"
+#include "soph_asic_qfn.dtsi"
+#include "soph_asic_sd.dtsi"
+#include "soph_default_memmap.dtsi"
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/gpio.h>
+
+&i2c0 {
+        status = "disabled";
+        /delete-property/ scl-pinmux;
+        /delete-property/ sda-pinmux;
+        /delete-property/ scl-gpios;
+        /delete-property/ sda-gpios;
+};
+
+&i2c1 {
+        status = "disabled";
+        /delete-property/ scl-pinmux;
+        /delete-property/ sda-pinmux;
+        /delete-property/ scl-gpios;
+        /delete-property/ sda-gpios;
+};
+
+&sd {
+        min-frequency = <400000>; // 400Khz
+        //max-frequency = <50000000>; // 50Mhz
+        max-frequency = <25000000>; // 25Mhz
+        //max-frequency = <10000000>; // 10Mhz
+        //max-frequency = <5000000>; // 5Mhz
+};
+
+&cvi_vo {
+#ifndef __UBOOT__
+	/delete-property/ reset-gpio;
+	/delete-property/ pwm-gpio;
+#else
+	// for uboot
+        reset-gpio = <&porte 0 1>;
+        pwm-gpio = <&porte 2 1>;
+#endif
+        /delete-property/ power-ct-gpio;
+
+};
+
+&mipi_tx {
+#ifndef __UBOOT__
+	// for linux kernel
+        reset-gpio = <&porte 0 1>;
+        pwm-gpio = <&porte 2 1>;
+#else
+        /delete-property/ reset-gpio;
+        /delete-property/ pwm-gpio;
+#endif
+        /delete-property/ power-ct-gpio;
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&pwm0 {
+        status = "okay";
+};
+
+&pwm1 {
+      status = "okay";
+};
+
+&pwm2 {
+      status = "okay";
+};
+
+&i2c2 {
+        status = "disabled";
+        /delete-property/ scl-pinmux;
+        /delete-property/ sda-pinmux;
+        /delete-property/ scl-gpios;
+        /delete-property/ sda-gpios;
+};
+
+&i2c3 {
+        status = "disabled";
+        /delete-property/ scl-pinmux;
+        /delete-property/ sda-pinmux;
+        /delete-property/ scl-gpios;
+        /delete-property/ sda-gpios;
+};
+
+&i2c4 {
+        statuc = "okay";
+        gt9xx: gt9xx@14 {
+                compatible = "goodix,gt9xx";
+                reg = <0x14>;
+                goodix,irq-gpio = <&porte 3 0>;
+                goodix,rst-gpio = <&porte 4 0>;
+                status = "okay";
+        };
+	hytr: hynitron@5a {
+		compatible = "hynitron,hyn_ts";
+		reg = <0x5a>;
+		hynitron,irq-gpio = <&porte 3 0>;
+		hynitron,reset-gpio = <&porte 4 0>;
+		hynitron,max-touch-number = <5>;
+		hynitron,display-coords = <368 552>;
+                status = "okay";
+	};
+};
+
+&dac {
+        status = "okay";
+        /delete-property/ mute-gpio-r;
+};
+
+&fb_reserved {
+        status = "okay";
+};
+
+&cvi_fb {
+        status = "okay";
+};
+
+&mipi_rx {
+        snsr-reset = <&porte 1 GPIO_ACTIVE_LOW>;
+};
+
+/ {
+        model = "LicheeRv Nano";
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                key-user {
+                        label = "User Key";
+                        linux,code = <KEY_DISPLAYTOGGLE>;
+                        debounce-interval = <1>;
+                        gpios = <&porta 30 1>;
+                };
+        };
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-user {
+			gpios = <&porta 14 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "activity";
+		};
+	};
+
+	lcd0_backlight: pwm-backlight@0 {
+		compatible = "pwm-backlight";
+		pwms = <&pwm2 2 50000000>; // 20Khz
+		brightness-levels = <0 2 4 8 16 32 64 128 255>;
+		default-brightness-level = <4>;
+	};
+
+        wifisd:wifi-sd@4320000 {                                                    
+                compatible = "cvitek,cv181x-sdio";                                  
+                bus-width = <4>;                                                    
+                reg = <0x0 0x4320000 0x0 0x1000>;                                   
+                reg_names = "core_mem";                                             
+                src-frequency = <375000000>;                                        
+                min-frequency = <400000>; // 400Khz                                 
+                //max-frequency = <50000000>; // 50Mhz                              
+                //max-frequency = <45000000>; // 45Mhz                              
+                //max-frequency = <40000000>; // 40Mhz                              
+                //max-frequency = <35000000>; // 35Mhz                              
+                //max-frequency = <30000000>; // 30Mhz                              
+                max-frequency = <25000000>; // 25Mhz                                
+                //max-frequency = <20000000>; // 20Mhz                              
+                //max-frequency = <15000000>; // 15Mhz                              
+                //max-frequency = <10000000>; // 10Mhz                              
+                //max-frequency = <5000000>; // 5Mhz                                
+                64_addressing;                                                      
+                reset_tx_rx_phy;                                                    
+                non-removable;                                                      
+                pll_index = <0x7>;                                                  
+                pll_reg = <0x300207C>;                                              
+                no-mmc;                                                             
+                no-sd;                                                              
+                status = "okay";                                                    
+		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+        };
+};

build/boards/sg200x/sg2002_licheea53nano_sd/linux/sg2002_licheea53nano_sd_defconfig

@@ -0,0 +1,370 @@
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_LOG_BUF_SHIFT=15
+CONFIG_BLK_DEV_INITRD=n
+# CONFIG_UID16 is not set
+# CONFIG_SYSFS_SYSCALL is not set
+# CONFIG_FHANDLE is not set
+# CONFIG_BASE_FULL is not set
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+# CONFIG_SLUB_DEBUG is not set
+CONFIG_ARM_LPAE=y
+CONFIG_SWP_EMULATE=y
+# CONFIG_VDSO is not set
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_ARM_PSCI=y
+CONFIG_THUMB2_KERNEL=y
+CONFIG_FORCE_MAX_ZONEORDER=10
+# CONFIG_ATAGS is not set
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_SUSPEND is not set
+CONFIG_ARCH_CVITEK=y
+CONFIG_ARCH_CV181X=y
+CONFIG_ARCH_CVITEK_CHIP="mars"
+CONFIG_ARCH_CV181X_ASIC=y
+CONFIG_POWER_RESET=y
+# CONFIG_STACKPROTECTOR is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_MQ_IOSCHED_DEADLINE is not set
+# CONFIG_MQ_IOSCHED_KYBER is not set
+# CONFIG_COREDUMP is not set
+CONFIG_CMA=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_CFG80211=m
+CONFIG_RFKILL=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+CONFIG_DMA_CMA=n
+CONFIG_CMA_SIZE_MBYTES=0
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_OF_PARTS is not set
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_MTD_NAND_CVSNFC=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_SPI_CVI_SPIF=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CORE is not set
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_AURORA is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CADENCE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_DWMAC_GENERIC is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_CVITEK_PHY=y
+# CONFIG_USB_NET_DRIVERS is not set
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATH is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+# CONFIG_WLAN_VENDOR_BROADCOM is not set
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_MARVELL is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+# CONFIG_RTL8188FU is not set
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=5
+CONFIG_SERIAL_8250_RUNTIME_UARTS=5
+CONFIG_SERIAL_8250_DW=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_SMBUS=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+# CONFIG_PTP_1588_CLOCK is not set
+CONFIG_CVITEK_PINCTRL_CV1835=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_NETLINK=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_WATCHDOG=y
+CONFIG_MEDIA_SUPPORT=n
+CONFIG_VIDEO_CVITEK=m
+CONFIG_VIDEO_CVITEK_CIF=m
+CONFIG_VIDEO_CVITEK_SNS_I2C=m
+CONFIG_VIDEO_CVITEK_MIPI_TX=m
+CONFIG_FB=y
+CONFIG_FB_CVITEK=m
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_PROC_FS is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_HDA_PREALLOC_SIZE=n
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_CV182XA_CV182XAADC=y
+CONFIG_SND_SOC_CV182XA_CV182XADAC=y
+CONFIG_SND_CV1835_I2S=y
+CONFIG_SND_SOC_CV182XAADC=y
+CONFIG_SND_SOC_CV182XADAC=y
+# CONFIG_SND_SOC_CV182X_CV182XPDM is not set
+# CONFIG_SND_SOC_CV1835PDM is not set
+# CONFIG_SND_SOC_CV1835_CONCURRENT_I2S is not set
+CONFIG_SND_SOC_CV1835_USE_AUDIO_PLL=y
+CONFIG_CV1835_I2S_SUBSYS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_CVI=y
+CONFIG_DMADEVICES=n
+CONFIG_DW_DMAC_CVITEK=n
+# CONFIG_VIRTIO_MENU is not set
+CONFIG_STAGING=y
+CONFIG_ION=y
+CONFIG_ION_SYSTEM_HEAP=y
+CONFIG_ION_CARVEOUT_HEAP=y
+CONFIG_ION_CMA_HEAP=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_CV1835_SYSDMA_REMAP=n
+CONFIG_PWM=y
+CONFIG_ANDROID=y
+# CONFIG_TEE=y
+# CONFIG_OPTEE=y
+# CONFIG_MANDATORY_FILE_LOCKING is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_CONFIGFS_FS=m
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_FILE_DIRECT=y
+# CONFIG_SQUASHFS_ZLIB is not set
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_EMBEDDED=y
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=1
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V2=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+# CONFIG_CRYPTO_ECHAINIV is not set
+CONFIG_CRYPTO_SHA256=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_FTRACE is not set
+# CONFIG_RUNTIME_TESTING_MENU is not set
+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
+
+CONFIG_RTC_CLASS=y
+
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_USB=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_LIBCOMPOSITE=y
+CONFIG_USB_F_ACM=y
+CONFIG_USB_U_SERIAL=y
+CONFIG_USB_U_ETHER=y
+CONFIG_USB_U_AUDIO=y
+CONFIG_USB_F_SERIAL=y
+CONFIG_USB_F_ECM=y
+CONFIG_USB_F_EEM=y
+CONFIG_USB_F_RNDIS=y
+CONFIG_USB_F_MASS_STORAGE=y
+CONFIG_USB_F_UAC1=y
+CONFIG_USB_F_UVC=y
+CONFIG_USB_UAS=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC2_DUAL_ROLE=y
+CONFIG_USB_GADGET=y
+CONFIG_U_SERIAL_CONSOLE=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_UAC1=y
+CONFIG_USB_CONFIGFS_F_UVC=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_UEVENT=y
+CONFIG_USB_PHY=y
+CONFIG_USB_GPIO_VBUS=y
+
+# for licheervnano
+CONFIG_FB_SIMPLE=y
+CONFIG_IP_MULTICAST=y
+CONFIG_SND_PROC_FS=y
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BREDR=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HS=y
+CONFIG_BT_LE=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SWAP=y
+CONFIG_USB_LIBCOMPOSITE=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_F_ACM=y
+CONFIG_USB_F_EEM=y
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_IPV6=y
+# CONFIG_IPV6_SIT is not set
+CONFIG_PACKET_DIAG=y
+CONFIG_UNIX_DIAG=y
+CONFIG_NETLINK_DIAG=y
+CONFIG_AIC_WLAN_SUPPORT=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_HYNITRON_TS=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_MAGIC_SYSRQ_SERIAL is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CLASS_FLASH=y
+CONFIG_LEDS_USER=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_LEDS_TRIGGER_ACTIVITY=y
+CONFIG_LEDS_TRIGGER_NETDEV=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_V4L2_FLASH_LED_CLASS=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_AIC_WLAN_SUPPORT=y     
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y           
+CONFIG_INPUT_TOUCHSCREEN=y 
+CONFIG_TOUCHSCREEN_HYNITRON_TS=y
+CONFIG_USB_DWC2=y
+CONFIG_VT=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=m
+CONFIG_BACKLIGHT_PWM=m
+
+
+
+# these driver may broken codec driver
+# CONFIG_FUSE_FS is not set
+# CONFIG_CUSE is not set
+# CONFIG_OVERLAY_FS is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_MEMCG is not set
+# CONFIG_BLK_CGROUP is not set
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_FAIR_GROUP_SCHED is not set
+# CONFIG_CFS_BANDWIDTH is not set
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_CGROUP_PIDS is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CHECKPOINT_RESTORE is not set
+CONFIG_EPOLL=y
+CONFIG_IO_URING=y
+CONFIG_SIGNALFD=y

build/boards/sg200x/sg2002_licheea53nano_sd/memmap.py

@@ -0,0 +1,85 @@
+SIZE_1M = 0x100000
+SIZE_1K = 1024
+
+
+# Only attributes in class MemoryMap are generated to .h
+class MemoryMap:
+    # No prefix "CVIMMAP_" for the items in _no_prefix[]
+    _no_prefix = [
+        "CONFIG_SYS_TEXT_BASE"  # u-boot's CONFIG_SYS_TEXT_BASE is used without CPP.
+    ]
+
+    DRAM_BASE = 0x80000000
+    DRAM_SIZE = 256 * SIZE_1M
+
+    # ==============
+    # C906L FreeRTOS
+    # ==============
+    FREERTOS_SIZE = 768 * SIZE_1K
+    # FreeRTOS is at the end of DRAM
+    FREERTOS_ADDR = DRAM_BASE + DRAM_SIZE - FREERTOS_SIZE
+    FSBL_C906L_START_ADDR = FREERTOS_ADDR
+
+    # ==============================
+    # OpenSBI | arm-trusted-firmware
+    # ==============================
+    # Monitor is at the begining of DRAM
+    MONITOR_ADDR = DRAM_BASE
+
+    ATF_SIZE = 512 * SIZE_1K
+    OPENSBI_SIZE = 512 * SIZE_1K
+    OPENSBI_FDT_ADDR = MONITOR_ADDR + OPENSBI_SIZE
+
+    # =========================
+    # memory@DRAM_BASE in .dts.
+    # =========================
+    # Ignore the area of FreeRTOS in u-boot and kernel
+    KERNEL_MEMORY_ADDR = DRAM_BASE
+    KERNEL_MEMORY_SIZE = DRAM_SIZE - FREERTOS_SIZE
+
+    # =================
+    # Multimedia buffer. Used by u-boot/kernel/FreeRTOS
+    # =================
+    ION_SIZE = 70 * SIZE_1M
+    H26X_BITSTREAM_SIZE = 2 * SIZE_1M
+    H26X_ENC_BUFF_SIZE = 0
+    ISP_MEM_BASE_SIZE = 20 * SIZE_1M
+    FREERTOS_RESERVED_ION_SIZE = H26X_BITSTREAM_SIZE + H26X_ENC_BUFF_SIZE + ISP_MEM_BASE_SIZE
+
+    # ION after FreeRTOS
+    ION_ADDR = FREERTOS_ADDR - ION_SIZE
+
+    # Buffers of the fast image are inside the ION buffer
+    H26X_BITSTREAM_ADDR = ION_ADDR
+    H26X_ENC_BUFF_ADDR = H26X_BITSTREAM_ADDR + H26X_BITSTREAM_SIZE
+    ISP_MEM_BASE_ADDR = H26X_ENC_BUFF_ADDR + H26X_ENC_BUFF_SIZE
+
+    assert ISP_MEM_BASE_ADDR + ISP_MEM_BASE_SIZE <= ION_ADDR + ION_SIZE
+
+    # Boot logo is after the ION buffer
+    # Framebuffer uses boot logo's reserved memory
+    BOOTLOGO_SIZE = 8000 * SIZE_1K
+    BOOTLOGO_ADDR = ION_ADDR - BOOTLOGO_SIZE
+    FRAMEBUFFER_SIZE = BOOTLOGO_SIZE
+    FRAMEBUFFER_ADDR = BOOTLOGO_ADDR
+
+    # ===================
+    # FSBL and u-boot-2021
+    # ===================
+    CVI_UPDATE_HEADER_SIZE = SIZE_1K
+    UIMAG_SIZE = 16 * SIZE_1M
+
+    # kernel image loading buffer
+    UIMAG_ADDR = DRAM_BASE + 24 * SIZE_1M
+    CVI_UPDATE_HEADER_ADDR = UIMAG_ADDR - CVI_UPDATE_HEADER_SIZE
+
+    # FSBL decompress buffer
+    FSBL_UNZIP_ADDR = UIMAG_ADDR
+    FSBL_UNZIP_SIZE = UIMAG_SIZE
+
+    assert UIMAG_ADDR + UIMAG_SIZE <= BOOTLOGO_ADDR
+
+    # u-boot's run address and entry point
+    CONFIG_SYS_TEXT_BASE = DRAM_BASE + 2 * SIZE_1M
+    # u-boot's init stack point is only used before board_init_f()
+    CONFIG_SYS_INIT_SP_ADDR = UIMAG_ADDR + UIMAG_SIZE

build/boards/sg200x/sg2002_licheea53nano_sd/sg2002_licheea53nano_sd_defconfig

@@ -0,0 +1,23 @@
+CONFIG_CHIP_sg2002=y
+CONFIG_BOARD_licheea53nano_sd=y
+CONFIG_DDR_CFG_ddr3_1866_x16=y
+CONFIG_ARCH="arm"
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_KERNEL_ENTRY_HACK=y
+CONFIG_KERNEL_ENTRY_HACK_ADDR="0x80108000"
+CONFIG_TOOLCHAIN_GLIBC_ARM=y
+# CONFIG_FLASH_SIZE_SHRINK is not set
+CONFIG_CP_EXT_WIRELESS=y
+CONFIG_BOOT_IMAGE_SINGLE_DTB=y
+CONFIG_STORAGE_TYPE_sd=y
+CONFIG_SENSOR_GCORE_GC4653=y
+CONFIG_UBOOT_2021_10=y
+CONFIG_KERNEL_SRC_5.10=y
+CONFIG_KERNEL_SRC="linux_5.10"
+CONFIG_KERNEL_LZMA=y
+CONFIG_SKIP_RAMDISK=y
+CONFIG_SENSOR_TUNING_PARAM_cv181x_src_gcore_gc4653=y
+# CONFIG_ROOTFS_OVERLAYFS is not set
+# CONFIG_TARGET_PACKAGE_RSYSLOG is not set
+# CONFIG_TARGET_PACKAGE_GATORD is not set
+CONFIG_ENABLE_FREERTOS=y

build/boards/sg200x/sg2002_licheea53nano_sd/u-boot/cvi_board_init.c

@@ -0,0 +1,137 @@
+__attribute__((optimize("O0")))
+// 1.26ms
+void suck_loop(uint64_t loop) {
+        loop = loop * 50 * 100;
+        uint64_t a;
+        while (loop > 0) {
+                a = loop / (uint64_t)99;
+                a = loop / (uint64_t)77;
+                a = loop / (uint64_t)55;
+                a = loop / (uint64_t)33;
+                a = loop / (uint64_t)11;
+                a = loop / (uint64_t)999;
+                a = loop / (uint64_t)777;
+                a = loop / (uint64_t)555;
+                a = loop / (uint64_t)333;
+                a = loop / (uint64_t)111;
+                a = loop / (uint64_t)9999;
+                a = loop / (uint64_t)7777;
+                a = loop / (uint64_t)5555;
+                a = loop / (uint64_t)3333;
+                a = loop / (uint64_t)1111;
+                a = loop / (uint64_t)99999;
+                a = loop / (uint64_t)77777;
+                a = loop / (uint64_t)55555;
+                a = loop / (uint64_t)33333;
+                a = loop / (uint64_t)11111;
+                loop--;
+        }
+}
+
+static inline void user_led_on(void) {
+	uint32_t val;
+
+        val = mmio_read_32(0x03020000);
+        val |= (1 << 14);
+        mmio_write_32(0x03020000, val);
+}
+
+static inline void user_led_off(void) {
+	uint32_t val;
+
+        val = mmio_read_32(0x03020000);
+        val &= ~(1 << 14);
+        mmio_write_32(0x03020000, val);
+}
+
+static inline void user_led_toggle(void) {
+	uint32_t val;
+
+        val = mmio_read_32(0x03020000);
+        val ^= (1 << 14);
+        mmio_write_32(0x03020000, val);
+}
+
+int cvi_board_init(void)
+{
+        uint32_t val;
+
+	// user led
+	mmio_write_32(0x03001038, 0x3); // GPIOA 14 GPIO_MODE
+	val = mmio_read_32(0x03020004); // GPIOA DIR
+        val |= (1 << 14); // output
+        mmio_write_32(0x03020004, val);
+	user_led_toggle();
+
+        // wifi power reset
+        mmio_write_32(0x0300104C, 0x3); // GPIOA 26
+        val = mmio_read_32(0x03020004); // GPIOA DIR
+        val |= (1 << 26); // output
+        mmio_write_32(0x03020004, val);
+
+        val = mmio_read_32(0x03020000); // signal level
+        val &= ~(1 << 26); // set level to low
+        mmio_write_32(0x03020000, val);
+
+        suck_loop(50);
+	user_led_toggle();
+
+        val = mmio_read_32(0x03020000); // signal level
+        val |= (1 << 26); // set level to high
+        mmio_write_32(0x03020000, val);
+
+        // wifi sdio pinmux
+        mmio_write_32(0x030010D0, 0x0); // D3
+        mmio_write_32(0x030010D4, 0x0); // D2
+        mmio_write_32(0x030010D8, 0x0); // D1
+        mmio_write_32(0x030010DC, 0x0); // D0
+        mmio_write_32(0x030010E0, 0x0); // CMD
+        mmio_write_32(0x030010E4, 0x0); // CLK
+
+        // uart bluetooth
+        mmio_write_32(0x03001070, 0x1); // GPIOA 28 UART1 TX
+        mmio_write_32(0x03001074, 0x1); // GPIOA 29 UART1 RX
+        mmio_write_32(0x03001068, 0x4); // GPIOA 18 UART1 CTS
+        mmio_write_32(0x03001064, 0x4); // GPIOA 19 UART1 RTS
+
+        // PWM
+        //mmio_write_32(0x03001068, 0x2); // GPIOA 18 PWM 6
+
+        // lcd reset
+        mmio_write_32(0x030010A4, 0x0); // PWRGPIO 0 GPIO_MODE
+
+	user_led_toggle();
+        // lcd backlight
+        //mmio_write_32(0x030010EC, 0x0); // GPIOB 0 PWM0_BUCK
+	// for licheervnano alpha
+	val = mmio_read_32(0x03021000); // signal level
+        val |= (1 << 0); // set level to high
+        mmio_write_32(0x03021000, val);
+        val = mmio_read_32(0x03021004); // GPIOB DIR
+        val |= (1 << 0); // output
+        mmio_write_32(0x03021004, val);
+        mmio_write_32(0x030010EC, 0x3); // GPIOB 0 GPIO_MODE
+
+	// for licheervnano beta
+	//mmio_write_32(0x030010ac, 0x4); // PWRGPIO 2 PWM 10
+	mmio_write_32(0x030010ac, 0x0); // PWRGPIO 2 GPIO_MODE
+
+        // camera function
+        //mmio_write_32(0x0300116C, 0x5); // RX4N CAM_MCLK0 for alpha
+        mmio_write_32(0x0300118C, 0x5); // RX0N CAM_MCLK1 for beta
+
+        // camera/tp i2c
+        mmio_write_32(0x03001090, 0x5); // PWR_GPIO6 IIC4_SCL
+        mmio_write_32(0x03001098, 0x5); // PWR_GPIO8 IIC4_SDA
+
+        // tp function
+        mmio_write_32(0x03001084, 0x3); // PWR_SEQ1 PWR_GPIO[3]
+        mmio_write_32(0x03001088, 0x3); // PWR_SEQ2 PWR_GPIO[4]
+        mmio_write_32(0x05027078, 0x11);// Unlock PWR_GPIO[3]
+        mmio_write_32(0x0502707c, 0x11);// Unlock PWR_GPIO[4]
+
+        // wait hardware bootup
+        suck_loop(50);
+	user_led_off();
+        return 0;
+}

build/boards/sg200x/sg2002_licheea53nano_sd/u-boot/cvitek.h

@@ -0,0 +1,13 @@
+/*
+ *VO control GPIOs
+ */
+#define VO_GPIO_RESET_PORT		portb
+#define VO_GPIO_RESET_INDEX		5
+#define VO_GPIO_RESET_ACTIVE	GPIO_ACTIVE_LOW
+#define VO_GPIO_PWM_PORT		portb
+#define VO_GPIO_PWM_INDEX		4
+#define VO_GPIO_PWM_ACTIVE		GPIO_ACTIVE_HIGH
+#define VO_GPIO_POWER_CT_PORT	portb
+#define VO_GPIO_POWER_CT_INDEX	3
+#define VO_GPIO_POWER_CT_ACTIVE	GPIO_ACTIVE_HIGH
+

build/boards/sg200x/sg2002_licheea53nano_sd/u-boot/sg2002_licheea53nano_sd_defconfig

@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="soph_asic"
+CONFIG_IDENT_STRING=" soph"
+CONFIG_ARMV8_SET_SMPEN=y
+CONFIG_TARGET_CVITEK_CV181X=y
+#CONFIG_CVITEK_SPI_FLASH=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_BOOTDELAY=0
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="soph# "
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNLZ4 is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_ITEST is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CVI_SD_UPDATE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_CVITEK=y
+CONFIG_MTD=y
+# CONFIG_PHY_SMSC is not set
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_CVITEK=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_LZ4=y
+CONFIG_LZMA=y
+# CONFIG_TOOLS_LIBCRYPTO is not set
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_ENV_IS_NOWHERE=y
+
+# for licheervnano
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_BUF_ADDR=0x81800000
+CONFIG_FASTBOOT_BUF_SIZE=0x1000000
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_DISPLAY=y
+CONFIG_DM_VIDEO=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_CMD_VIDCONSOLE=y
+CONFIG_VIDEO_BPP16=y
+CONFIG_VIDEO_BPP32=y
+CONFIG_VIDEO_CVITEK=y
+CONFIG_DISPLAY_CVITEK_MIPI=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_BOOTLOGO=y
+CONFIG_CMD_CVI_VO=y
+CONFIG_CMD_GPIO=y

build/boards/sg200x/sg2002_licheearmnano_sd/config.json

@@ -1,9 +0,0 @@
-{
-    "ddr_cfg_list": [
-        "",
-        "ddr3_1866_x16",
-        "ddr3_2133_x16",
-        "ddr_auto_x16"
-    ],
-    "board_information": "CA53 + DDR 256MB"
-}

build/boards/sg200x/sg2002_licheearmnano_sd/dts_arm/sg2002_licheearmnano_sd.dts

@@ -1,177 +0,0 @@
-/dts-v1/;
-#include "soph_base_arm.dtsi"
-#include "soph_asic_qfn.dtsi"
-#include "soph_asic_sd.dtsi"
-#include "soph_default_memmap.dtsi"
-
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/gpio/gpio.h>
-
-&i2c0 {
-        status = "disabled";
-        /delete-property/ scl-pinmux;
-        /delete-property/ sda-pinmux;
-        /delete-property/ scl-gpios;
-        /delete-property/ sda-gpios;
-};
-
-&i2c1 {
-        status = "disabled";
-        /delete-property/ scl-pinmux;
-        /delete-property/ sda-pinmux;
-        /delete-property/ scl-gpios;
-        /delete-property/ sda-gpios;
-};
-
-&sd {
-        min-frequency = <400000>; // 400Khz
-        //max-frequency = <50000000>; // 50Mhz
-        max-frequency = <25000000>; // 25Mhz
-        //max-frequency = <10000000>; // 10Mhz
-        //max-frequency = <5000000>; // 5Mhz
-};
-
-&cvi_vo {
-#ifndef __UBOOT__
-	/delete-property/ reset-gpio;
-#else
-	// for uboot
-        reset-gpio = <&porte 0 1>;
-#endif
-        /delete-property/ pwm-gpio;
-        /delete-property/ power-ct-gpio;
-
-};
-
-&mipi_tx {
-        /delete-property/ pwm-gpio;
-#ifndef __UBOOT__
-	// for linux kernel
-        reset-gpio = <&porte 0 1>;
-#else
-        /delete-property/ reset-gpio;
-#endif
-        /delete-property/ power-ct-gpio;
-        status = "okay";
-};
-
-&uart1 {
-        status = "okay";
-};
-
-&pwm0 {
-        status = "okay";
-};
-
-&pwm1 {
-      status = "okay";
-};
-
-&pwm2 {
-      status = "okay";
-};
-
-&i2c2 {
-        status = "disabled";
-        /delete-property/ scl-pinmux;
-        /delete-property/ sda-pinmux;
-        /delete-property/ scl-gpios;
-        /delete-property/ sda-gpios;
-};
-
-&i2c3 {
-        status = "disabled";
-        /delete-property/ scl-pinmux;
-        /delete-property/ sda-pinmux;
-        /delete-property/ scl-gpios;
-        /delete-property/ sda-gpios;
-};
-
-&i2c4 {
-        statuc = "okay";
-        gt9xx: gt9xx@14 {
-                compatible = "goodix,gt9xx";
-                reg = <0x14>;
-                goodix,irq-gpio = <&porte 3 0>;
-                goodix,rst-gpio = <&porte 4 0>;
-                status = "okay";
-        };
-	hytr: hynitron@5a {
-		compatible = "hynitron,hyn_ts";
-		reg = <0x5a>;
-		hynitron,irq-gpio = <&porte 3 0>;
-		hynitron,reset-gpio = <&porte 4 0>;
-		hynitron,max-touch-number = <5>;
-		hynitron,display-coords = <368 552>;
-                status = "okay";
-	};
-};
-
-&dac {
-        status = "okay";
-        /delete-property/ mute-gpio-r;
-};
-
-&fb_reserved {
-        status = "okay";
-};
-
-&cvi_fb {
-        status = "okay";
-};
-
-&mipi_rx {
-        snsr-reset = <&porte 1 GPIO_ACTIVE_LOW>;
-};
-
-/ {
-        model = "LicheeRv Nano";
-
-        gpio-keys {
-                compatible = "gpio-keys";
-                key-user {
-                        label = "User Key";
-                        linux,code = <KEY_DISPLAYTOGGLE>;
-                        debounce-interval = <1>;
-                        gpios = <&porta 30 1>;
-                };
-        };
-
-	leds {
-		compatible = "gpio-leds";
-
-		led-user {
-			gpios = <&porta 14 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "activity";
-		};
-	};
-
-        wifisd:wifi-sd@4320000 {
-                compatible = "cvitek,cv181x-sdio";
-                bus-width = <4>;
-                reg = <0x0 0x4320000 0x0 0x1000>;
-                reg_names = "core_mem";
-                src-frequency = <375000000>;
-                min-frequency = <400000>; // 400Khz
-                //max-frequency = <50000000>; // 50Mhz
-                //max-frequency = <45000000>; // 45Mhz
-                //max-frequency = <40000000>; // 40Mhz
-                //max-frequency = <35000000>; // 35Mhz
-                //max-frequency = <30000000>; // 30Mhz
-                max-frequency = <25000000>; // 25Mhz
-                //max-frequency = <20000000>; // 20Mhz
-                //max-frequency = <15000000>; // 15Mhz
-                //max-frequency = <10000000>; // 10Mhz
-                //max-frequency = <5000000>; // 5Mhz
-                64_addressing;
-                reset_tx_rx_phy;
-                non-removable;
-                pll_index = <0x7>;
-                pll_reg = <0x300207C>;
-                no-mmc;
-                no-sd;
-                status = "okay";
-                interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-parent = <&plic0>;
-        };
-};

build/boards/sg200x/sg2002_licheearmnano_sd/linux/sg2002_licheearmnano_sd_defconfig

@@ -1,570 +0,0 @@
-CONFIG_ARM_LPAE=y
-CONFIG_SWP_EMULATE=y
-CONFIG_HAVE_ARM_ARCH_TIMER=y
-CONFIG_ARM_PSCI=y
-CONFIG_THUMB2_KERNEL=y
-CONFIG_FORCE_MAX_ZONEORDER=10
-# CONFIG_ATAGS is not set
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=15
-CONFIG_BLK_DEV_INITRD=n
-# CONFIG_SYSFS_SYSCALL is not set
-# CONFIG_FHANDLE is not set
-# CONFIG_BASE_FULL is not set
-# CONFIG_AIO is not set
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_FORCE_MAX_ZONEORDER=10
-CONFIG_ARCH_CVITEK=y
-CONFIG_SOC_THEAD=y
-# CONFIG_COMPAT is not set
-CONFIG_ARCH_CVITEK_CHIP="mars"
-CONFIG_ARCH_CV181X_ASIC=y
-CONFIG_POWER_RESET=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_STRICT_KERNEL_RWX=n
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_MQ_IOSCHED_DEADLINE is not set
-# CONFIG_MQ_IOSCHED_KYBER is not set
-CONFIG_ELF_CORE=y
-CONFIG_COREDUMP=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_CMA=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_CFG80211=m
-CONFIG_RFKILL=y
-CONFIG_UEVENT_HELPER=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_ALLOW_DEV_COREDUMP is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_OF_PARTS is not set
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_CORE is not set
-# CONFIG_NET_VENDOR_ALACRITECH is not set
-# CONFIG_NET_VENDOR_AMAZON is not set
-# CONFIG_NET_VENDOR_AQUANTIA is not set
-# CONFIG_NET_VENDOR_ARC is not set
-# CONFIG_NET_VENDOR_AURORA is not set
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CADENCE is not set
-# CONFIG_NET_VENDOR_CAVIUM is not set
-# CONFIG_NET_VENDOR_CORTINA is not set
-# CONFIG_NET_VENDOR_EZCHIP is not set
-# CONFIG_NET_VENDOR_HUAWEI is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_MICROSEMI is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_NETRONOME is not set
-# CONFIG_NET_VENDOR_NI is not set
-# CONFIG_NET_VENDOR_QUALCOMM is not set
-# CONFIG_NET_VENDOR_RENESAS is not set
-# CONFIG_NET_VENDOR_ROCKER is not set
-# CONFIG_NET_VENDOR_SAMSUNG is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SOLARFLARE is not set
-# CONFIG_NET_VENDOR_SOCIONEXT is not set
-CONFIG_STMMAC_ETH=y
-# CONFIG_DWMAC_GENERIC is not set
-# CONFIG_NET_VENDOR_SYNOPSYS is not set
-# CONFIG_NET_VENDOR_VIA is not set
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_CVITEK_PHY=y
-# CONFIG_USB_NET_DRIVERS is not set
-# CONFIG_WLAN_VENDOR_ADMTEK is not set
-# CONFIG_WLAN_VENDOR_ATH is not set
-# CONFIG_WLAN_VENDOR_ATMEL is not set
-# CONFIG_WLAN_VENDOR_BROADCOM is not set
-# CONFIG_WLAN_VENDOR_CISCO is not set
-# CONFIG_WLAN_VENDOR_INTEL is not set
-# CONFIG_WLAN_VENDOR_INTERSIL is not set
-# CONFIG_WLAN_VENDOR_MARVELL is not set
-# CONFIG_WLAN_VENDOR_MEDIATEK is not set
-# CONFIG_WLAN_VENDOR_RALINK is not set
-# CONFIG_RTL8188FU is not set
-# CONFIG_WLAN_VENDOR_RSI is not set
-# CONFIG_WLAN_VENDOR_ST is not set
-# CONFIG_WLAN_VENDOR_TI is not set
-# CONFIG_WLAN_VENDOR_ZYDAS is not set
-CONFIG_INPUT=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_EVDEV=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=5
-CONFIG_SERIAL_8250_RUNTIME_UARTS=5
-CONFIG_SERIAL_8250_DW=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_DESIGNWARE_PLATFORM=y
-# CONFIG_PTP_1588_CLOCK is not set
-CONFIG_PINCTRL=y
-CONFIG_CVITEK_PINCTRL_CV1835=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_DWAPB=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_NETLINK=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THERMAL_EMULATION=y
-CONFIG_WATCHDOG=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_V4L2_SUBDEV_API=y
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_V4L_MEM2MEM_DRIVERS=y
-CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
-CONFIG_VIDEO_CVITEK=m
-CONFIG_VIDEO_CVITEK_CIF=m
-CONFIG_VIDEO_CVITEK_SNS_I2C=m
-CONFIG_VIDEO_CVITEK_MIPI_TX=m
-#
-# Media SPI Adapters
-#
-# CONFIG_CXD2880_SPI_DRV is not set
-# end of Media SPI Adapters
-#
-# Customize TV tuners
-#
-# CONFIG_MEDIA_TUNER_SIMPLE is not set
-# CONFIG_MEDIA_TUNER_TDA18250 is not set
-# CONFIG_MEDIA_TUNER_TDA8290 is not set
-# CONFIG_MEDIA_TUNER_TDA827X is not set
-# CONFIG_MEDIA_TUNER_TDA18271 is not set
-# CONFIG_MEDIA_TUNER_TDA9887 is not set
-# CONFIG_MEDIA_TUNER_TEA5761 is not set
-# CONFIG_MEDIA_TUNER_TEA5767 is not set
-# CONFIG_MEDIA_TUNER_MSI001 is not set
-# CONFIG_MEDIA_TUNER_MT20XX is not set
-# CONFIG_MEDIA_TUNER_MT2060 is not set
-# CONFIG_MEDIA_TUNER_MT2063 is not set
-# CONFIG_MEDIA_TUNER_MT2266 is not set
-# CONFIG_MEDIA_TUNER_MT2131 is not set
-# CONFIG_MEDIA_TUNER_QT1010 is not set
-# CONFIG_MEDIA_TUNER_XC2028 is not set
-# CONFIG_MEDIA_TUNER_XC5000 is not set
-# CONFIG_MEDIA_TUNER_XC4000 is not set
-# CONFIG_MEDIA_TUNER_MXL5005S is not set
-# CONFIG_MEDIA_TUNER_MXL5007T is not set
-# CONFIG_MEDIA_TUNER_MC44S803 is not set
-# CONFIG_MEDIA_TUNER_MAX2165 is not set
-# CONFIG_MEDIA_TUNER_TDA18218 is not set
-# CONFIG_MEDIA_TUNER_FC0011 is not set
-# CONFIG_MEDIA_TUNER_FC0012 is not set
-# CONFIG_MEDIA_TUNER_FC0013 is not set
-# CONFIG_MEDIA_TUNER_TDA18212 is not set
-# CONFIG_MEDIA_TUNER_E4000 is not set
-# CONFIG_MEDIA_TUNER_FC2580 is not set
-# CONFIG_MEDIA_TUNER_M88RS6000T is not set
-# CONFIG_MEDIA_TUNER_TUA9001 is not set
-# CONFIG_MEDIA_TUNER_SI2157 is not set
-# CONFIG_MEDIA_TUNER_IT913X is not set
-# CONFIG_MEDIA_TUNER_R820T is not set
-# CONFIG_MEDIA_TUNER_MXL301RF is not set
-# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
-# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
-# end of Customize TV tuners
-#
-# Customise DVB Frontends
-#
-
-#
-# Multistandard (satellite) frontends
-#
-# CONFIG_DVB_STB0899 is not set
-# CONFIG_DVB_STB6100 is not set
-# CONFIG_DVB_STV090x is not set
-# CONFIG_DVB_STV0910 is not set
-# CONFIG_DVB_STV6110x is not set
-# CONFIG_DVB_STV6111 is not set
-# CONFIG_DVB_MXL5XX is not set
-# CONFIG_DVB_M88DS3103 is not set
-
-#
-# Multistandard (cable + terrestrial) frontends
-#
-# CONFIG_DVB_DRXK is not set
-# CONFIG_DVB_TDA18271C2DD is not set
-# CONFIG_DVB_SI2165 is not set
-# CONFIG_DVB_MN88472 is not set
-# CONFIG_DVB_MN88473 is not set
-
-#
-# DVB-S (satellite) frontends
-#
-# CONFIG_DVB_CX24110 is not set
-# CONFIG_DVB_CX24123 is not set
-# CONFIG_DVB_MT312 is not set
-# CONFIG_DVB_ZL10036 is not set
-# CONFIG_DVB_ZL10039 is not set
-# CONFIG_DVB_S5H1420 is not set
-# CONFIG_DVB_STV0288 is not set
-# CONFIG_DVB_STB6000 is not set
-# CONFIG_DVB_STV0299 is not set
-# CONFIG_DVB_STV6110 is not set
-# CONFIG_DVB_STV0900 is not set
-# CONFIG_DVB_TDA8083 is not set
-# CONFIG_DVB_TDA10086 is not set
-# CONFIG_DVB_TDA8261 is not set
-# CONFIG_DVB_VES1X93 is not set
-# CONFIG_DVB_TUNER_ITD1000 is not set
-# CONFIG_DVB_TUNER_CX24113 is not set
-# CONFIG_DVB_TDA826X is not set
-# CONFIG_DVB_TUA6100 is not set
-# CONFIG_DVB_CX24116 is not set
-# CONFIG_DVB_CX24117 is not set
-# CONFIG_DVB_CX24120 is not set
-# CONFIG_DVB_SI21XX is not set
-# CONFIG_DVB_TS2020 is not set
-# CONFIG_DVB_DS3000 is not set
-# CONFIG_DVB_MB86A16 is not set
-# CONFIG_DVB_TDA10071 is not set
-
-#
-# DVB-T (terrestrial) frontends
-#
-# CONFIG_DVB_SP8870 is not set
-# CONFIG_DVB_SP887X is not set
-# CONFIG_DVB_CX22700 is not set
-# CONFIG_DVB_CX22702 is not set
-# CONFIG_DVB_S5H1432 is not set
-# CONFIG_DVB_DRXD is not set
-# CONFIG_DVB_L64781 is not set
-# CONFIG_DVB_TDA1004X is not set
-# CONFIG_DVB_NXT6000 is not set
-# CONFIG_DVB_MT352 is not set
-# CONFIG_DVB_ZL10353 is not set
-# CONFIG_DVB_DIB3000MB is not set
-# CONFIG_DVB_DIB3000MC is not set
-# CONFIG_DVB_DIB7000M is not set
-# CONFIG_DVB_DIB7000P is not set
-# CONFIG_DVB_DIB9000 is not set
-# CONFIG_DVB_TDA10048 is not set
-# CONFIG_DVB_AF9013 is not set
-# CONFIG_DVB_EC100 is not set
-# CONFIG_DVB_STV0367 is not set
-# CONFIG_DVB_CXD2820R is not set
-# CONFIG_DVB_CXD2841ER is not set
-# CONFIG_DVB_RTL2830 is not set
-# CONFIG_DVB_RTL2832 is not set
-# CONFIG_DVB_RTL2832_SDR is not set
-# CONFIG_DVB_SI2168 is not set
-# CONFIG_DVB_ZD1301_DEMOD is not set
-# CONFIG_DVB_CXD2880 is not set
-
-#
-# DVB-C (cable) frontends
-#
-# CONFIG_DVB_VES1820 is not set
-# CONFIG_DVB_TDA10021 is not set
-# CONFIG_DVB_TDA10023 is not set
-# CONFIG_DVB_STV0297 is not set
-
-#
-# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
-#
-# CONFIG_DVB_NXT200X is not set
-# CONFIG_DVB_OR51211 is not set
-# CONFIG_DVB_OR51132 is not set
-# CONFIG_DVB_BCM3510 is not set
-# CONFIG_DVB_LGDT330X is not set
-# CONFIG_DVB_LGDT3305 is not set
-# CONFIG_DVB_LGDT3306A is not set
-# CONFIG_DVB_LG2160 is not set
-# CONFIG_DVB_S5H1409 is not set
-# CONFIG_DVB_AU8522_DTV is not set
-# CONFIG_DVB_AU8522_V4L is not set
-# CONFIG_DVB_S5H1411 is not set
-
-#
-# ISDB-T (terrestrial) frontends
-#
-# CONFIG_DVB_S921 is not set
-# CONFIG_DVB_DIB8000 is not set
-# CONFIG_DVB_MB86A20S is not set
-
-#
-# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
-#
-# CONFIG_DVB_TC90522 is not set
-# CONFIG_DVB_MN88443X is not set
-
-#
-# Digital terrestrial only tuners/PLL
-#
-# CONFIG_DVB_PLL is not set
-# CONFIG_DVB_TUNER_DIB0070 is not set
-# CONFIG_DVB_TUNER_DIB0090 is not set
-#
-# SEC control devices for DVB-S
-#
-# CONFIG_DVB_DRX39XYJ is not set
-# CONFIG_DVB_LNBH25 is not set
-# CONFIG_DVB_LNBH29 is not set
-# CONFIG_DVB_LNBP21 is not set
-# CONFIG_DVB_LNBP22 is not set
-# CONFIG_DVB_ISL6405 is not set
-# CONFIG_DVB_ISL6421 is not set
-# CONFIG_DVB_ISL6423 is not set
-# CONFIG_DVB_A8293 is not set
-# CONFIG_DVB_LGS8GL5 is not set
-# CONFIG_DVB_LGS8GXX is not set
-# CONFIG_DVB_ATBM8830 is not set
-# CONFIG_DVB_TDA665x is not set
-# CONFIG_DVB_IX2505V is not set
-# CONFIG_DVB_M88RS2000 is not set
-# CONFIG_DVB_AF9033 is not set
-# CONFIG_DVB_HORUS3A is not set
-# CONFIG_DVB_ASCOT2E is not set
-# CONFIG_DVB_HELENE is not set
-#
-# Common Interface (EN50221) controller drivers
-#
-# CONFIG_DVB_CXD2099 is not set
-# CONFIG_DVB_SP2 is not set
-# end of Customise DVB Frontends
-#
-# Digital TV options
-#
-# CONFIG_DVB_NET is not set
-# CONFIG_DVB_DYNAMIC_MINORS is not set
-# end of Digital TV options
-
-CONFIG_FB=y
-CONFIG_FB_CVITEK=m
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_PROC_FS is not set
-# CONFIG_SND_DRIVERS is not set
-CONFIG_SND_HDA_PREALLOC_SIZE=1
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_CV182XA_CV182XAADC=y
-CONFIG_SND_SOC_CV182XA_CV182XADAC=y
-CONFIG_SND_CV1835_I2S=y
-CONFIG_SND_SOC_CV182XAADC=y
-CONFIG_SND_SOC_CV182XADAC=y
-CONFIG_SND_SOC_CV1835_USE_AUDIO_PLL=y
-CONFIG_CV1835_I2S_SUBSYS=y
-CONFIG_USB=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_GADGET=y
-CONFIG_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_CVI=y
-CONFIG_BLK_CMDLINE_PARSER=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_CMDLINE_PARTITION=y
-CONFIG_EFI_PARTITION=n
-CONFIG_DYNAMIC_DEBUG=y
-CONFIG_EXT4_FS=y
-CONFIG_DMADEVICES=y
-CONFIG_DW_DMAC_CVITEK=y
-CONFIG_RTC_CLASS=y
-# CONFIG_VIRTIO_MENU is not set
-CONFIG_STAGING=y
-CONFIG_ION=y
-CONFIG_ION_SYSTEM_HEAP=y
-CONFIG_ION_CARVEOUT_HEAP=y
-CONFIG_ION_CMA_HEAP=y
-# CONFIG_IOMMU_SUPPORT is not set
-CONFIG_CV1835_SYSDMA_REMAP=y
-CONFIG_PWM=y
-CONFIG_SIFIVE_PLIC=y
-CONFIG_ANDROID=y
-# CONFIG_MANDATORY_FILE_LOCKING is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-CONFIG_UBIFS_FS=y
-CONFIG_SQUASHFS=y
-# CONFIG_SQUASHFS_ZLIB is not set
-CONFIG_SQUASHFS_LZ4=y
-CONFIG_SQUASHFS_XZ=y
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V2=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=y
-CONFIG_NLS_ISO8859_3=y
-CONFIG_CRYPTO_SHA256=y
-# CONFIG_CRYPTO_HW is not set
-# CONFIG_XZ_DEC_X86 is not set
-# CONFIG_XZ_DEC_POWERPC is not set
-# CONFIG_XZ_DEC_IA64 is not set
-# CONFIG_XZ_DEC_ARMTHUMB is not set
-# CONFIG_XZ_DEC_SPARC is not set
-CONFIG_DMA_CMA=y
-CONFIG_CMA_SIZE_MBYTES=0
-CONFIG_PRINTK_TIME=y
-CONFIG_DYNAMIC_DEBUG=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=n
-CONFIG_DEBUG_INFO_DWARF4=n
-CONFIG_GDB_SCRIPTS=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_DEBUG_FS=y
-CONFIG_KALLSYMS=y
-CONFIG_FRAME_POINTER=n
-CONFIG_DEBUG_MISC=n
-CONFIG_RCU_TRACE=n
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_LIBCOMPOSITE=y
-CONFIG_USB_F_ACM=y
-CONFIG_USB_U_SERIAL=y
-CONFIG_USB_U_ETHER=y
-CONFIG_USB_U_AUDIO=y
-CONFIG_USB_F_SERIAL=y
-CONFIG_USB_F_ECM=y
-CONFIG_USB_F_EEM=y
-CONFIG_USB_F_RNDIS=y
-CONFIG_USB_F_MASS_STORAGE=y
-CONFIG_USB_F_FS=y
-CONFIG_USB_F_UAC1=y
-# buggy driver, need fix
-# CONFIG_USB_F_UVC is not set
-CONFIG_USB_CONFIGFS=y
-CONFIG_USB_CONFIGFS_SERIAL=y
-CONFIG_USB_CONFIGFS_ACM=y
-# CONFIG_USB_CONFIGFS_OBEX is not set
-# CONFIG_USB_CONFIGFS_NCM is not set
-CONFIG_USB_CONFIGFS_ECM=y
-# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
-CONFIG_USB_CONFIGFS_RNDIS=y
-CONFIG_USB_CONFIGFS_EEM=y
-CONFIG_USB_CONFIGFS_MASS_STORAGE=y
-# CONFIG_USB_CONFIGFS_F_LB_SS is not set
-CONFIG_USB_CONFIGFS_F_FS=y
-CONFIG_USB_CONFIGFS_UEVENT=y
-CONFIG_USB_CONFIGFS_F_UAC1=y
-# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
-# CONFIG_USB_CONFIGFS_F_UAC2 is not set
-# CONFIG_USB_CONFIGFS_F_MIDI is not set
-# CONFIG_USB_CONFIGFS_F_HID is not set
-CONFIG_USB_CONFIGFS_F_UVC=y
-CONFIG_BUG=n
-CONFIG_ADVISE_SYSCALLS=n
-CONFIG_TIMERFD=n
-
-# for licheervnano
-CONFIG_FB_SIMPLE=y
-CONFIG_IP_MULTICAST=y
-CONFIG_SND_PROC_FS=y
-CONFIG_BT=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BREDR=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HS=y
-CONFIG_BT_LE=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SWAP=y
-CONFIG_USB_LIBCOMPOSITE=y
-CONFIG_USB_CONFIGFS=y
-CONFIG_USB_CONFIGFS_EEM=y
-CONFIG_USB_CONFIGFS_ACM=y
-CONFIG_USB_F_ACM=y
-CONFIG_USB_F_EEM=y
-CONFIG_USB_GADGET_VBUS_DRAW=500
-CONFIG_IPV6=y
-# CONFIG_IPV6_SIT is not set
-CONFIG_PACKET_DIAG=y
-CONFIG_UNIX_DIAG=y
-CONFIG_NETLINK_DIAG=y
-CONFIG_AIC_WLAN_SUPPORT=y
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_HYNITRON_TS=y
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_MAGIC_SYSRQ_SERIAL is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_CLASS_FLASH=y
-CONFIG_LEDS_USER=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_CAMERA=y
-CONFIG_LEDS_TRIGGER_ACTIVITY=y
-CONFIG_LEDS_TRIGGER_NETDEV=y
-CONFIG_LEDS_TRIGGER_PANIC=y
-CONFIG_V4L2_FLASH_LED_CLASS=y
-CONFIG_MEDIA_USB_SUPPORT=y
-CONFIG_USB_VIDEO_CLASS=y
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-
-# these driver may broken codec driver
-# CONFIG_FUSE_FS is not set
-# CONFIG_CUSE is not set
-# CONFIG_OVERLAY_FS is not set
-# CONFIG_NAMESPACES is not set
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-# CONFIG_NET_NS is not set
-# CONFIG_CGROUPS is not set
-# CONFIG_MEMCG is not set
-# CONFIG_BLK_CGROUP is not set
-# CONFIG_CGROUP_SCHED is not set
-# CONFIG_FAIR_GROUP_SCHED is not set
-# CONFIG_CFS_BANDWIDTH is not set
-# CONFIG_RT_GROUP_SCHED is not set
-# CONFIG_CGROUP_PIDS is not set
-# CONFIG_CGROUP_DEVICE is not set
-# CONFIG_CHECKPOINT_RESTORE is not set
-CONFIG_EPOLL=y
-CONFIG_IO_URING=y
-CONFIG_SIGNALFD=y

build/boards/sg200x/sg2002_licheearmnano_sd/sg2002_licheearmnano_sd_defconfig

@@ -1,25 +0,0 @@
-CONFIG_CHIP_sg2002=y
-CONFIG_BOARD_licheearmnano_sd=y
-CONFIG_DDR_CFG_ddr3_1866_x16=y
-CONFIG_ARCH="arm64"
-CONFIG_CROSS_COMPILE="aarch64-linux-gnu-"
-CONFIG_CROSS_COMPILE_KERNEL="aarch64-linux-gnu-"
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_KERNEL_ENTRY_HACK=y
-CONFIG_KERNEL_ENTRY_HACK_ADDR="0x80200000"
-CONFIG_TOOLCHAIN_GLIBC_ARM64=y
-CONFIG_FLASH_SIZE_SHRINK=y
-CONFIG_BOOT_IMAGE_SINGLE_DTB=y
-# CONFIG_FLASH_SIZE_SHRINK is not set
-CONFIG_CP_EXT_WIRELESS=y
-CONFIG_STORAGE_TYPE_sd=y
-CONFIG_MIPI_PANEL_ZCT2133V1=y
-CONFIG_SENSOR_GCORE_GC4653=y
-CONFIG_UBOOT_2021_10=y
-CONFIG_KERNEL_SRC_5.10=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SKIP_RAMDISK=y
-CONFIG_SENSOR_TUNING_PARAM_cv181x_src_gcore_gc4653=y
-# CONFIG_ROOTFS_OVERLAYFS is not set
-# CONFIG_ENABLE_FREERTOS is not set
-# CONFIG_TARGET_PACKAGE_GATORD is not set

build/boards/sg200x/sg2002_licheearmnano_sd/u-boot/cvi_board_init.c

@@ -1,136 +0,0 @@
-__attribute__((optimize("O0")))
-// 1.26ms
-void suck_loop(uint64_t loop) {
-        loop = loop * 50 * 100;
-        uint64_t a;
-        while (loop > 0) {
-                a = loop / (uint64_t)99;
-                a = loop / (uint64_t)77;
-                a = loop / (uint64_t)55;
-                a = loop / (uint64_t)33;
-                a = loop / (uint64_t)11;
-                a = loop / (uint64_t)999;
-                a = loop / (uint64_t)777;
-                a = loop / (uint64_t)555;
-                a = loop / (uint64_t)333;
-                a = loop / (uint64_t)111;
-                a = loop / (uint64_t)9999;
-                a = loop / (uint64_t)7777;
-                a = loop / (uint64_t)5555;
-                a = loop / (uint64_t)3333;
-                a = loop / (uint64_t)1111;
-                a = loop / (uint64_t)99999;
-                a = loop / (uint64_t)77777;
-                a = loop / (uint64_t)55555;
-                a = loop / (uint64_t)33333;
-                a = loop / (uint64_t)11111;
-                loop--;
-        }
-}
-
-static inline void user_led_on(void) {
-	uint32_t val;
-
-        val = mmio_read_32(0x03020000);
-        val |= (1 << 14);
-        mmio_write_32(0x03020000, val);
-}
-
-static inline void user_led_off(void) {
-	uint32_t val;
-
-        val = mmio_read_32(0x03020000);
-        val &= ~(1 << 14);
-        mmio_write_32(0x03020000, val);
-}
-
-static inline void user_led_toggle(void) {
-	uint32_t val;
-
-        val = mmio_read_32(0x03020000);
-        val ^= (1 << 14);
-        mmio_write_32(0x03020000, val);
-}
-
-int cvi_board_init(void)
-{
-        uint32_t val;
-
-	// user led
-	mmio_write_32(0x03001038, 0x3); // GPIOA 14 GPIO_MODE
-	val = mmio_read_32(0x03020004); // GPIOA DIR
-        val |= (1 << 14); // output
-        mmio_write_32(0x03020004, val);
-	user_led_toggle();
-
-        // wifi power reset
-        mmio_write_32(0x0300104C, 0x3); // GPIOA 26
-        val = mmio_read_32(0x03020004); // GPIOA DIR
-        val |= (1 << 26); // output
-        mmio_write_32(0x03020004, val);
-
-        val = mmio_read_32(0x03020000); // signal level
-        val &= ~(1 << 26); // set level to low
-        mmio_write_32(0x03020000, val);
-
-        suck_loop(200);
-	user_led_toggle();
-
-        val = mmio_read_32(0x03020000); // signal level
-        val |= (1 << 26); // set level to high
-        mmio_write_32(0x03020000, val);
-
-        // wifi sdio pinmux
-        mmio_write_32(0x030010D0, 0x0); // D3
-        mmio_write_32(0x030010D4, 0x0); // D2
-        mmio_write_32(0x030010D8, 0x0); // D1
-        mmio_write_32(0x030010DC, 0x0); // D0
-        mmio_write_32(0x030010E0, 0x0); // CMD
-        mmio_write_32(0x030010E4, 0x0); // CLK
-
-        // uart bluetooth
-        mmio_write_32(0x03001070, 0x1); // GPIOA 28 UART1 TX
-        mmio_write_32(0x03001074, 0x1); // GPIOA 29 UART1 RX
-        mmio_write_32(0x03001068, 0x4); // GPIOA 18 UART1 CTS
-        mmio_write_32(0x03001064, 0x4); // GPIOA 19 UART1 RTS
-
-        // PWM
-        //mmio_write_32(0x03001068, 0x2); // GPIOA 18 PWM 6
-
-        // lcd reset
-        mmio_write_32(0x030010A4, 0x0); // PWRGPIO 0 GPIO_MODE
-
-	user_led_toggle();
-        // lcd backlight
-        //mmio_write_32(0x030010EC, 0x0); // GPIOB 0 PWM0_BUCK
-	// for licheervnano alpha
-	val = mmio_read_32(0x03021000); // signal level
-        val |= (1 << 0); // set level to high
-        mmio_write_32(0x03021000, val);
-        val = mmio_read_32(0x03021004); // GPIOB DIR
-        val |= (1 << 0); // output
-        mmio_write_32(0x03021004, val);
-        mmio_write_32(0x030010EC, 0x3); // GPIOB 0 GPIO_MODE
-
-	// for licheervnano beta
-	mmio_write_32(0x030010ac, 0x4); // PWRGPIO 2 PWM 10
-
-        // camera function
-        //mmio_write_32(0x0300116C, 0x5); // RX4N CAM_MCLK0 for inside preview board
-        mmio_write_32(0x0300118C, 0x5); // RX0N CAM_MCLK1
-
-        // camera/tp i2c
-        mmio_write_32(0x03001090, 0x5); // PWR_GPIO6 IIC4_SCL
-        mmio_write_32(0x03001098, 0x5); // PWR_GPIO8 IIC4_SDA
-
-        // tp function
-        mmio_write_32(0x03001084, 0x3); // PWR_SEQ1 PWR_GPIO[3]
-        mmio_write_32(0x03001088, 0x3); // PWR_SEQ2 PWR_GPIO[4]
-        mmio_write_32(0x05027078, 0x11);// Unlock PWR_GPIO[3]
-        mmio_write_32(0x0502707c, 0x11);// Unlock PWR_GPIO[4]
-
-        // wait hardware bootup
-        suck_loop(100);
-	user_led_off();
-        return 0;
-}

build/boards/sg200x/sg2002_licheearmnano_sd/u-boot/sg2002_licheearmnano_sd_defconfig

@@ -1,66 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="soph_asic"
-CONFIG_IDENT_STRING=" soph"
-CONFIG_TARGET_CVITEK_CV181X=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_BOOTDELAY=1
-CONFIG_SYS_PROMPT="soph# "
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_LZMADEC is not set
-# CONFIG_CMD_UNLZ4 is not set
-# CONFIG_CMD_UNZIP is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_ITEST is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_CVI_SD_UPDATE=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_MMC_SDHCI_CVITEK=y
-CONFIG_MTD=y
-# CONFIG_PHY_SMSC is not set
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_PHY_CVITEK=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_LZ4=y
-CONFIG_LZMA=y
-# CONFIG_TOOLS_LIBCRYPTO is not set
-CONFIG_ENV_IS_NOWHERE=y
-
-# for licheervnano
-CONFIG_UDP_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_BUF_ADDR=0x81800000
-CONFIG_FASTBOOT_BUF_SIZE=0x1000000
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_DISPLAY=y
-CONFIG_DM_VIDEO=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_CMD_VIDCONSOLE=y
-CONFIG_VIDEO_BPP16=y
-CONFIG_VIDEO_BPP32=y
-CONFIG_VIDEO_CVITEK=y
-CONFIG_DISPLAY_CVITEK_MIPI=y
-CONFIG_BMP_16BPP=y
-CONFIG_BMP_24BPP=y
-CONFIG_BMP_32BPP=y
-CONFIG_BOOTLOGO=y
-CONFIG_CMD_CVI_VO=y
-CONFIG_CMD_GPIO=y
-
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y

build/boards/sg200x/sg2002_licheervnano_sd/dts_riscv/sg2002_licheervnano_sd.dts

@@ -8,7 +8,7 @@
 #include <dt-bindings/gpio/gpio.h>
 
 &i2c0 {
-        status = "disabled";
+        status = "okay";
         /delete-property/ scl-pinmux;
         /delete-property/ sda-pinmux;
         /delete-property/ scl-gpios;
@@ -16,7 +16,7 @@
 };
 
 &i2c1 {
-        status = "disabled";
+        status = "okay";
         /delete-property/ scl-pinmux;
         /delete-property/ sda-pinmux;
         /delete-property/ scl-gpios;
@@ -34,31 +34,52 @@
 &cvi_vo {
 #ifndef __UBOOT__
 	/delete-property/ reset-gpio;
+	/delete-property/ pwm-gpio;
 #else
 	// for uboot
         reset-gpio = <&porte 0 1>;
+        pwm-gpio = <&porte 2 1>;
 #endif
-        /delete-property/ pwm-gpio;
         /delete-property/ power-ct-gpio;
 
 };
 
 &mipi_tx {
-        /delete-property/ pwm-gpio;
 #ifndef __UBOOT__
 	// for linux kernel
         reset-gpio = <&porte 0 1>;
+        pwm-gpio = <&porte 2 1>;
 #else
         /delete-property/ reset-gpio;
+        /delete-property/ pwm-gpio;
 #endif
         /delete-property/ power-ct-gpio;
         status = "okay";
 };
 
+&uart0 {
+	clocks = <&clk CV181X_CLK_UART0>;
+	/delete-property/ clock-frequency;
+};
+
 &uart1 {
+        clocks = <&clk CV181X_CLK_UART1>;
+        /delete-property/ clock-frequency;
         status = "okay";
 };
 
+&uart2 {
+        clocks = <&clk CV181X_CLK_UART2>;
+        /delete-property/ clock-frequency;
+        status = "okay";
+};
+
+&uart3 {
+        clocks = <&clk CV181X_CLK_UART3>;
+        /delete-property/ clock-frequency;
+	status = "okay";
+};
+
 &pwm0 {
         status = "okay";
 };
@@ -80,7 +101,7 @@
 };
 
 &i2c3 {
-        status = "disabled";
+        status = "okay";
         /delete-property/ scl-pinmux;
         /delete-property/ sda-pinmux;
         /delete-property/ scl-gpios;
@@ -88,7 +109,7 @@
 };
 
 &i2c4 {
-        statuc = "okay";
+        status = "okay";
         gt9xx: gt9xx@14 {
                 compatible = "goodix,gt9xx";
                 reg = <0x14>;
@@ -96,22 +117,63 @@
                 goodix,rst-gpio = <&porte 4 0>;
                 status = "okay";
         };
-	hytr: hynitron@5a {
-		compatible = "hynitron,hyn_ts";
-		reg = <0x5a>;
-		hynitron,irq-gpio = <&porte 3 0>;
-		hynitron,reset-gpio = <&porte 4 0>;
-		hynitron,max-touch-number = <5>;
-		hynitron,display-coords = <368 552>;
+        hynitron: hynitron@5a {
+                compatible = "hynitron,hyn_ts", "hyn,7xx";
+                reg = <0x5a>;
+                irq-gpio = <&porte 3 0>;
+                hynitron,irq-gpio = <&porte 3 0>;
+                reset-gpio = <&porte 4 0>;
+                hynitron,reset-gpio = <&porte 4 0>;
+                max-touch-number = <5>;
+                hynitron,max-touch-number = <5>;
+                display-coords = <0 0 480 640>;
+                hynitron,display-coords = <368 552>;
+                pos-swap = <0>;
+                posx-reverse = <1>;
+                posy-reverse = <1>;
                 status = "okay";
+        };
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+
+        // /delete-node/ spidev@0;
+        st7789: st7789@0{
+		compatible = "sitronix,st7789";
+		reg = <0>;
+		status = "disabled";
+		spi-max-frequency = <80000000>;
+		spi-cpol;
+		spi-cpha;
+		rotate = <0>;
+		fps = <60>;
+		rgb;
+		buswidth = <8>;
+		dc = <&porte 20 GPIO_ACTIVE_HIGH>;
+		reset = <&porta 14 GPIO_ACTIVE_LOW>;
+		debug = <0>;
 	};
 };
 
+&spi3 {
+	status = "okay";
+};
+
 &dac {
         status = "okay";
         /delete-property/ mute-gpio-r;
 };
 
+#if (CVIMMAP_FRAMEBUFFER_SIZE > 0)
 &fb_reserved {
         status = "okay";
 };
@@ -119,6 +181,7 @@
 &cvi_fb {
         status = "okay";
 };
+#endif
 
 &mipi_rx {
         snsr-reset = <&porte 1 GPIO_ACTIVE_LOW>;
@@ -127,6 +190,29 @@
 / {
         model = "LicheeRv Nano";
 
+	spi4: spi4@gpio {
+		compatible = "spi-gpio";
+		sck-gpio = <&porta 22 0>;
+		miso-gpio = <&porta 23 0>;
+		mosi-gpio = <&porta 25 0>;
+		cs-gpio = <&porta 24 GPIO_ACTIVE_LOW>;
+		num-chipselects = <1>;
+		status = "okay";
+
+		spidev@0 {
+			compatible = "spidev";
+			reg = <0>;
+		};
+	};
+
+	i2c5: i2c5@gpio {
+		compatible = "i2c-gpio";
+                scl-gpios = <&porta 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                sda-gpios = <&porta 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                i2c-gpio,delay-us = <5>;
+                status = "okay";
+	};
+
         gpio-keys {
                 compatible = "gpio-keys";
                 key-user {
@@ -146,6 +232,17 @@
 		};
 	};
 
+	// buggy pwm driver, not working, please use userspace pwm api
+	/*
+	lcd0_backlight: pwm-backlight@0 {
+		compatible = "pwm-backlight";
+		pwm-names = "backlight";
+		pwms = <&pwm2 2 50000000>; // 20Khz
+		brightness-levels = <0 2 4 8 16 32 64 128 255>;
+		default-brightness-level = <4>;
+	};
+	*/
+
         wifisd:wifi-sd@4320000 {
                 compatible = "cvitek,cv181x-sdio";
                 bus-width = <4>;

build/boards/sg200x/sg2002_licheervnano_sd/linux/sg2002_licheervnano_sd_defconfig

@@ -8,7 +8,7 @@ CONFIG_PREEMPT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=15
-CONFIG_BLK_DEV_INITRD=n
+CONFIG_BLK_DEV_INITRD=y
 # CONFIG_SYSFS_SYSCALL is not set
 # CONFIG_FHANDLE is not set
 # CONFIG_BASE_FULL is not set
@@ -42,7 +42,7 @@ CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 # CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
+CONFIG_IPV6=y
 CONFIG_CFG80211=m
 CONFIG_RFKILL=y
 CONFIG_UEVENT_HELPER=y
@@ -107,14 +107,8 @@ CONFIG_CVITEK_PHY=y
 # CONFIG_WLAN_VENDOR_TI is not set
 # CONFIG_WLAN_VENDOR_ZYDAS is not set
 CONFIG_INPUT=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 CONFIG_INPUT_EVDEV=y
 # CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=5
@@ -123,9 +117,13 @@ CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
 CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
+CONFIG_I2C_SLAVE=y
+CONFIG_I2C_SLAVE_EEPROM=y
+CONFIG_I2C_DESIGNWARE_SLAVE=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MUX=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_GPIO=m
 # CONFIG_PTP_1588_CLOCK is not set
 CONFIG_PINCTRL=y
 CONFIG_CVITEK_PINCTRL_CV1835=y
@@ -359,6 +357,8 @@ CONFIG_VIDEO_CVITEK_MIPI_TX=m
 # end of Digital TV options
 
 CONFIG_FB=y
+# CONFIG_FB_TFT is not set
+# CONFIG_FB_TFT_ST7789 is not set
 CONFIG_FB_CVITEK=m
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -450,7 +450,17 @@ CONFIG_RCU_TRACE=n
 # CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_FTRACE is not set
 # CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_USB_ROLE_SWITCH=y
+
+CONFIG_RTC_CLASS=y
+
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_USB=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=y
+CONFIG_USB_STORAGE=y
 CONFIG_USB_LIBCOMPOSITE=y
 CONFIG_USB_F_ACM=y
 CONFIG_USB_U_SERIAL=y
@@ -463,13 +473,14 @@ CONFIG_USB_F_RNDIS=y
 CONFIG_USB_F_MASS_STORAGE=y
 CONFIG_USB_F_FS=y
 CONFIG_USB_F_UAC1=y
+CONFIG_USB_ROLE_SWITCH=y
 # buggy driver, need fix
 # CONFIG_USB_F_UVC is not set
 CONFIG_USB_CONFIGFS=y
 CONFIG_USB_CONFIGFS_SERIAL=y
 CONFIG_USB_CONFIGFS_ACM=y
 # CONFIG_USB_CONFIGFS_OBEX is not set
-# CONFIG_USB_CONFIGFS_NCM is not set
+CONFIG_USB_CONFIGFS_NCM=y
 CONFIG_USB_CONFIGFS_ECM=y
 # CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
 CONFIG_USB_CONFIGFS_RNDIS=y
@@ -482,11 +493,11 @@ CONFIG_USB_CONFIGFS_F_UAC1=y
 # CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
 # CONFIG_USB_CONFIGFS_F_UAC2 is not set
 # CONFIG_USB_CONFIGFS_F_MIDI is not set
-# CONFIG_USB_CONFIGFS_F_HID is not set
+CONFIG_USB_CONFIGFS_F_HID=y
 CONFIG_USB_CONFIGFS_F_UVC=y
 CONFIG_BUG=n
 CONFIG_ADVISE_SYSCALLS=n
-CONFIG_TIMERFD=n
+CONFIG_TIMERFD=y
 
 # for licheervnano
 CONFIG_FB_SIMPLE=y
@@ -502,6 +513,9 @@ CONFIG_BT_HS=y
 CONFIG_BT_LE=y
 CONFIG_BT_HCIUART=y
 CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIUART_RTL=y
 CONFIG_SERIAL_DEV_BUS=y
 CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
 CONFIG_SWAP=y
@@ -522,6 +536,8 @@ CONFIG_KEYBOARD_GPIO=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_HYNITRON_TS=y
 CONFIG_MAGIC_SYSRQ=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
 # CONFIG_MAGIC_SYSRQ_SERIAL is not set
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
@@ -539,17 +555,27 @@ CONFIG_V4L2_FLASH_LED_CLASS=y
 CONFIG_MEDIA_USB_SUPPORT=y
 CONFIG_USB_VIDEO_CLASS=y
 CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_VT=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=m
+CONFIG_BACKLIGHT_PWM=m
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_DESIGNWARE=y
+CONFIG_SPI_DW_MMIO=y
+CONFIG_SPI_GPIO=m
+CONFIG_SPI_SPIDEV=y
 
 # these driver may broken codec driver
 # CONFIG_FUSE_FS is not set
 # CONFIG_CUSE is not set
 # CONFIG_OVERLAY_FS is not set
-# CONFIG_NAMESPACES is not set
+CONFIG_NAMESPACES=y
 # CONFIG_UTS_NS is not set
 # CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
+CONFIG_USER_NS=y
 # CONFIG_PID_NS is not set
-# CONFIG_NET_NS is not set
+CONFIG_NET_NS=y
 # CONFIG_CGROUPS is not set
 # CONFIG_MEMCG is not set
 # CONFIG_BLK_CGROUP is not set
@@ -563,3 +589,422 @@ CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
 CONFIG_EPOLL=y
 CONFIG_IO_URING=y
 CONFIG_SIGNALFD=y
+CONFIG_EXFAT_FS=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=y
+CONFIG_UNIX=y
+CONFIG_UNIX_SCM=y
+CONFIG_UNIX_DIAG=y
+# CONFIG_TLS is not set
+# CONFIG_XFRM_USER is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_ROUTE_CLASSID=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+CONFIG_NET_IPGRE=y
+# CONFIG_NET_IPGRE_DEMUX is not set
+CONFIG_IP_MULTIPLE_TABLES=y
+# CONFIG_IP_MROUTE is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_NET_IPVTI is not set
+# CONFIG_NET_FOU is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_BBR=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_IPV6_ILA is not set
+# CONFIG_IPV6_VTI is not set
+# CONFIG_IPV6_SIT is not set
+CONFIG_IPV6_TUNNEL=y
+CONFIG_IPV6_GRE=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_IPV6_SEG6_LWTUNNEL is not set
+# CONFIG_IPV6_SEG6_HMAC is not set
+# CONFIG_IPV6_RPL_LWTUNNEL is not set
+# CONFIG_MPTCP is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_INGRESS=y
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_FAMILY_ARP=y
+CONFIG_NETFILTER_NETLINK_ACCT=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NETFILTER_NETLINK_OSF=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_LOG_COMMON=y
+CONFIG_NF_LOG_NETDEV=y
+CONFIG_NETFILTER_CONNCOUNT=y
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_ZONES=y
+CONFIG_NF_CONNTRACK_PROCFS=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+CONFIG_NF_CONNTRACK_TIMESTAMP=y
+CONFIG_NF_CONNTRACK_LABELS=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_BROADCAST=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_SNMP=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NF_CT_NETLINK_TIMEOUT=y
+CONFIG_NF_CT_NETLINK_HELPER=y
+CONFIG_NETFILTER_NETLINK_GLUE_CT=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_REDIRECT=y
+CONFIG_NF_NAT_MASQUERADE=y
+CONFIG_NETFILTER_SYNPROXY=y
+CONFIG_NF_TABLES=y
+CONFIG_NF_TABLES_INET=y
+CONFIG_NF_TABLES_NETDEV=y
+CONFIG_NFT_NUMGEN=y
+CONFIG_NFT_CT=y
+# CONFIG_NFT_FLOW_OFFLOAD is not set
+CONFIG_NFT_COUNTER=y
+CONFIG_NFT_CONNLIMIT=y
+CONFIG_NFT_LOG=y
+CONFIG_NFT_LIMIT=y
+CONFIG_NFT_MASQ=y
+CONFIG_NFT_REDIR=y
+CONFIG_NFT_NAT=y
+CONFIG_NFT_TUNNEL=y
+CONFIG_NFT_OBJREF=y
+CONFIG_NFT_QUEUE=y
+CONFIG_NFT_QUOTA=y
+CONFIG_NFT_REJECT=y
+CONFIG_NFT_REJECT_INET=y
+CONFIG_NFT_COMPAT=y
+CONFIG_NFT_HASH=y
+CONFIG_NFT_FIB=y
+# CONFIG_NFT_FIB_INET is not set
+CONFIG_NFT_SOCKET=y
+CONFIG_NFT_OSF=y
+CONFIG_NFT_TPROXY=y
+CONFIG_NFT_SYNPROXY=y
+CONFIG_NF_DUP_NETDEV=y
+CONFIG_NFT_DUP_NETDEV=y
+CONFIG_NFT_FWD_NETDEV=y
+# CONFIG_NFT_FIB_NETDEV is not set
+CONFIG_NF_FLOW_TABLE_INET=y
+CONFIG_NF_FLOW_TABLE=y
+CONFIG_NETFILTER_XTABLES=y
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=y
+CONFIG_NETFILTER_XT_CONNMARK=y
+CONFIG_NETFILTER_XT_SET=y
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+# CONFIG_NETFILTER_XT_TARGET_CT is not set
+# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
+CONFIG_NETFILTER_XT_TARGET_HL=y
+CONFIG_NETFILTER_XT_TARGET_HMARK=y
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_LED=y
+CONFIG_NETFILTER_XT_TARGET_LOG=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_NAT=y
+CONFIG_NETFILTER_XT_TARGET_NETMAP=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_REDIRECT=y
+CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y
+CONFIG_NETFILTER_XT_TARGET_TEE=y
+# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set
+# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
+CONFIG_NETFILTER_XT_MATCH_BPF=y
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_CPU=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ECN=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_HL=y
+CONFIG_NETFILTER_XT_MATCH_IPCOMP=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_IPVS=y
+CONFIG_NETFILTER_XT_MATCH_L2TP=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_NFACCT=y
+CONFIG_NETFILTER_XT_MATCH_OSF=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_RECENT=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_SOCKET=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+# end of Core Netfilter Configuration
+
+CONFIG_IP_SET=y
+CONFIG_IP_SET_MAX=256
+# CONFIG_IP_SET_BITMAP_IP is not set
+# CONFIG_IP_SET_BITMAP_IPMAC is not set
+# CONFIG_IP_SET_BITMAP_PORT is not set
+# CONFIG_IP_SET_HASH_IP is not set
+# CONFIG_IP_SET_HASH_IPMARK is not set
+# CONFIG_IP_SET_HASH_IPPORT is not set
+# CONFIG_IP_SET_HASH_IPPORTIP is not set
+# CONFIG_IP_SET_HASH_IPPORTNET is not set
+# CONFIG_IP_SET_HASH_IPMAC is not set
+# CONFIG_IP_SET_HASH_MAC is not set
+# CONFIG_IP_SET_HASH_NETPORTNET is not set
+# CONFIG_IP_SET_HASH_NET is not set
+# CONFIG_IP_SET_HASH_NETNET is not set
+# CONFIG_IP_SET_HASH_NETPORT is not set
+# CONFIG_IP_SET_HASH_NETIFACE is not set
+# CONFIG_IP_SET_LIST_SET is not set
+CONFIG_IP_VS=y
+# CONFIG_IP_VS_IPV6 is not set
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+# CONFIG_IP_VS_PROTO_TCP is not set
+# CONFIG_IP_VS_PROTO_UDP is not set
+# CONFIG_IP_VS_PROTO_ESP is not set
+# CONFIG_IP_VS_PROTO_AH is not set
+# CONFIG_IP_VS_PROTO_SCTP is not set
+
+#
+# IPVS scheduler
+#
+# CONFIG_IP_VS_RR is not set
+# CONFIG_IP_VS_WRR is not set
+# CONFIG_IP_VS_LC is not set
+# CONFIG_IP_VS_WLC is not set
+# CONFIG_IP_VS_FO is not set
+# CONFIG_IP_VS_OVF is not set
+# CONFIG_IP_VS_LBLC is not set
+# CONFIG_IP_VS_LBLCR is not set
+# CONFIG_IP_VS_DH is not set
+# CONFIG_IP_VS_SH is not set
+# CONFIG_IP_VS_MH is not set
+# CONFIG_IP_VS_SED is not set
+# CONFIG_IP_VS_NQ is not set
+
+#
+# IPVS SH scheduler
+#
+CONFIG_IP_VS_SH_TAB_BITS=8
+
+#
+# IPVS MH scheduler
+#
+CONFIG_IP_VS_MH_TAB_INDEX=12
+
+#
+# IPVS application helper
+#
+# CONFIG_IP_VS_NFCT is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=y
+CONFIG_NF_SOCKET_IPV4=y
+CONFIG_NF_TPROXY_IPV4=y
+CONFIG_NF_TABLES_IPV4=y
+CONFIG_NFT_REJECT_IPV4=y
+CONFIG_NFT_DUP_IPV4=y
+CONFIG_NFT_FIB_IPV4=y
+CONFIG_NF_TABLES_ARP=y
+CONFIG_NF_FLOW_TABLE_IPV4=y
+CONFIG_NF_DUP_IPV4=y
+CONFIG_NF_LOG_ARP=y
+CONFIG_NF_LOG_IPV4=y
+CONFIG_NF_REJECT_IPV4=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+# CONFIG_IP_NF_MATCH_RPFILTER is not set
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_SYNPROXY=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+# end of IP: Netfilter Configuration
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_SOCKET_IPV6=y
+CONFIG_NF_TPROXY_IPV6=y
+CONFIG_NF_TABLES_IPV6=y
+CONFIG_NFT_REJECT_IPV6=y
+CONFIG_NFT_DUP_IPV6=y
+CONFIG_NFT_FIB_IPV6=y
+CONFIG_NF_FLOW_TABLE_IPV6=y
+CONFIG_NF_DUP_IPV6=y
+CONFIG_NF_REJECT_IPV6=y
+CONFIG_NF_LOG_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_AH=y
+CONFIG_IP6_NF_MATCH_EUI64=y
+CONFIG_IP6_NF_MATCH_FRAG=y
+CONFIG_IP6_NF_MATCH_OPTS=y
+CONFIG_IP6_NF_MATCH_HL=y
+CONFIG_IP6_NF_MATCH_IPV6HEADER=y
+CONFIG_IP6_NF_MATCH_MH=y
+# CONFIG_IP6_NF_MATCH_RPFILTER is not set
+CONFIG_IP6_NF_MATCH_RT=y
+CONFIG_IP6_NF_MATCH_SRH=y
+# CONFIG_IP6_NF_TARGET_HL is not set
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_TARGET_SYNPROXY=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_IP6_NF_NAT=y
+CONFIG_IP6_NF_TARGET_MASQUERADE=y
+CONFIG_IP6_NF_TARGET_NPT=y
+# end of IPv6: Netfilter Configuration
+
+CONFIG_NF_DEFRAG_IPV6=y
+CONFIG_NF_CONNTRACK_BRIDGE=y
+# CONFIG_BPFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+CONFIG_HAVE_NET_DSA=y
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+# CONFIG_6LOWPAN is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+# CONFIG_DNS_RESOLVER is not set
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_VSOCKETS is not set
+CONFIG_NETLINK_DIAG=y
+# CONFIG_MPLS is not set
+# CONFIG_NET_NSH is not set
+# CONFIG_HSR is not set
+# CONFIG_NET_SWITCHDEV is not set
+# CONFIG_NET_L3_MASTER_DEV is not set
+# CONFIG_QRTR is not set
+# CONFIG_NET_NCSI is not set
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+# CONFIG_BPF_JIT is not set
+
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_NET_CORE=y
+CONFIG_WIREGUARD=y
+CONFIG_TUN=y
+
+CONFIG_NET_IP_TUNNEL=y
+CONFIG_NET_UDP_TUNNEL=y
+CONFIG_VXLAN=y
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_OPTION=y
+CONFIG_USB_ACM=y
+
+CONFIG_VETH=y

build/boards/sg200x/sg2002_licheervnano_sd/memmap.py

@@ -56,9 +56,9 @@ class MemoryMap:
 
     assert ISP_MEM_BASE_ADDR + ISP_MEM_BASE_SIZE <= ION_ADDR + ION_SIZE
 
-    # Boot logo is after the ION buffer
-    # Framebuffer uses boot logo's reserved memory
-    BOOTLOGO_SIZE = 8000 * SIZE_1K
+    # NanoKVM has no display output, so do not reserve framebuffer/bootlogo
+    # memory.  Keeping this at zero returns the region to Linux.
+    BOOTLOGO_SIZE = 0
     BOOTLOGO_ADDR = ION_ADDR - BOOTLOGO_SIZE
     FRAMEBUFFER_SIZE = BOOTLOGO_SIZE
     FRAMEBUFFER_ADDR = BOOTLOGO_ADDR

build/boards/sg200x/sg2002_licheervnano_sd/partition/partition_sd.xml

@@ -1,4 +1,4 @@
 <physical_partition type="sd">
     <partition label="BOOT" size_in_kb="80960" readonly="false" file="boot.sd"/>
-    <partition label="ROOTFS" size_in_kb="1048576" readonly="false" file="rootfs.sd" />
+    <partition label="ROOTFS" size_in_kb="1581056" readonly="false" file="rootfs.sd" />
 </physical_partition>

build/boards/sg200x/sg2002_licheervnano_sd/sg2002_licheervnano_sd_defconfig

@@ -14,11 +14,16 @@ CONFIG_CP_EXT_WIRELESS=y
 CONFIG_STORAGE_TYPE_sd=y
 CONFIG_MIPI_PANEL_ZCT2133V1=y
 CONFIG_SENSOR_GCORE_GC4653=y
+CONFIG_SENSOR_OV_OV2685=y
+CONFIG_SENSOR_OV_OS04A10=y
+CONFIG_SENSOR_LONTIUM_LT6911=y
+CONFIG_SENSOR_SMS_SC035GS=y
 CONFIG_UBOOT_2021_10=y
 CONFIG_KERNEL_SRC_5.10=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SKIP_RAMDISK=y
+CONFIG_KERNEL_UNCOMPRESSED=y
+# CONFIG_SKIP_RAMDISK is not set
 CONFIG_SENSOR_TUNING_PARAM_cv181x_src_gcore_gc4653=y
+# CONFIG_SENSOR_TUNING_PARAM_sg200x_src_ov_os04a10=y
 # CONFIG_ROOTFS_OVERLAYFS is not set
-CONFIG_ENABLE_FREERTOS=y
+# CONFIG_ENABLE_FREERTOS=y
 # CONFIG_TARGET_PACKAGE_GATORD is not set

build/boards/sg200x/sg2002_licheervnano_sd/u-boot/cvi_board_init.c

@@ -73,7 +73,7 @@ int cvi_board_init(void)
         val &= ~(1 << 26); // set level to low
         mmio_write_32(0x03020000, val);
 
-        suck_loop(200);
+        suck_loop(50);
 	user_led_toggle();
 
         val = mmio_read_32(0x03020000); // signal level
@@ -88,6 +88,14 @@ int cvi_board_init(void)
         mmio_write_32(0x030010E0, 0x0); // CMD
         mmio_write_32(0x030010E4, 0x0); // CLK
 
+        // spi2 pinmux
+        // mmio_write_32(0x030010D0, 0x1); // CS
+        // mmio_write_32(0x030010DC, 0x1); // MISO
+        // mmio_write_32(0x030010E0, 0x1); // MOSI
+        // mmio_write_32(0x030010E4, 0x1); // SCK
+        // mmio_write_32(0x030010D8, 0x3); // DC
+        // mmio_write_32(0x03001038, 0x3); // RESET
+
         // uart bluetooth
         mmio_write_32(0x03001070, 0x1); // GPIOA 28 UART1 TX
         mmio_write_32(0x03001074, 0x1); // GPIOA 29 UART1 RX
@@ -113,11 +121,21 @@ int cvi_board_init(void)
         mmio_write_32(0x030010EC, 0x3); // GPIOB 0 GPIO_MODE
 
 	// for licheervnano beta
-	mmio_write_32(0x030010ac, 0x4); // PWRGPIO 2 PWM 10
+	//mmio_write_32(0x030010ac, 0x4); // PWRGPIO 2 PWM 10
+	mmio_write_32(0x030010ac, 0x0); // PWRGPIO 2 GPIO_MODE
 
         // camera function
-        //mmio_write_32(0x0300116C, 0x5); // RX4N CAM_MCLK0 for inside preview board
-        mmio_write_32(0x0300118C, 0x5); // RX0N CAM_MCLK1
+        //mmio_write_32(0x0300116C, 0x5); // RX4N CAM_MCLK0 for alpha
+        mmio_write_32(0x0300118C, 0x5); // RX0N CAM_MCLK1 for beta
+
+	// spi1 on mipi csi 
+	/*
+	mmio_write_32(0x0300116C, 0x7); // spi1 clk   GPIOC2 MIPI_RX4N
+	mmio_write_32(0x03001170, 0x7); // spi1 cs    GPIOC3 MIPI_RX4P
+	mmio_write_32(0x03001174, 0x7); // spi1 miso  GPIOC4 MIPI_RX3N
+	mmio_write_32(0x03001178, 0x7); // spi1 mosi  GPIOC5 MIPI_RX3P
+	*/
+	
 
         // camera/tp i2c
         mmio_write_32(0x03001090, 0x5); // PWR_GPIO6 IIC4_SCL
@@ -129,8 +147,18 @@ int cvi_board_init(void)
         mmio_write_32(0x05027078, 0x11);// Unlock PWR_GPIO[3]
         mmio_write_32(0x0502707c, 0x11);// Unlock PWR_GPIO[4]
 
+	// bitbang i2c
+        mmio_write_32(0x0300103C, 0x03); // GPIOA 15 GPIO_MODE
+	mmio_write_32(0x03001058, 0x03); // GPIOA 27 GPIO_MODE
+
+	// bitbang spi
+	mmio_write_32(0x03001060, 0x03); // GPIOA 24 GPIO_MODE
+	mmio_write_32(0x0300105C, 0x03); // GPIOA 23 GPIO_MODE
+	mmio_write_32(0x03001054, 0x03); // GPIOA 25 GPIO_MODE
+	mmio_write_32(0x03001050, 0x03); // GPIOA 22 GPIO_MODE
+
         // wait hardware bootup
-        suck_loop(100);
+        suck_loop(50);
 	user_led_off();
         return 0;
 }

build/boards/sg200x/sg2002_licheervnano_sd/u-boot/sg2002_licheervnano_sd_defconfig

@@ -9,7 +9,7 @@ CONFIG_TARGET_CVITEK_CV181X=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_BOOTDELAY=1
+CONFIG_BOOTDELAY=0
 CONFIG_SYS_PROMPT="soph# "
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_XIMG is not set
@@ -63,3 +63,4 @@ CONFIG_BMP_32BPP=y
 CONFIG_BOOTLOGO=y
 CONFIG_CMD_CVI_VO=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_MBR=y

build/boards/sg200x/sg2002_licheervnano_sd_minimal/buildroot.config

@@ -0,0 +1,79 @@
+BR2_riscv=y
+BR2_RISCV_ISA_RVC=y
+BR2_TOOLCHAIN_EXTERNAL=y
+BR2_TOOLCHAIN_EXTERNAL_CUSTOM=y
+BR2_TOOLCHAIN_EXTERNAL_CUSTOM_PREFIX="riscv64-unknown-linux-musl"
+BR2_TOOLCHAIN_EXTERNAL_GCC_10=y
+BR2_TOOLCHAIN_EXTERNAL_HEADERS_5_10=y
+BR2_TOOLCHAIN_EXTERNAL_CUSTOM_MUSL=y
+BR2_TOOLCHAIN_EXTERNAL_CXX=y
+BR2_TOOLCHAIN_EXTERNAL_OPENMP=y
+BR2_TARGET_LDFLAGS="-mcpu=c906fdv -march=rv64imafdcv0p7xthead -mcmodel=medany -mabi=lp64d"
+BR2_CCACHE=y
+BR2_OPTIMIZE_S=y
+BR2_REPRODUCIBLE=y
+BR2_PER_PACKAGE_DIRECTORIES=y
+BR2_TARGET_GENERIC_HOSTNAME="licheervnano"
+BR2_TARGET_GENERIC_ISSUE="Welcome to NanoKVM"
+BR2_INIT_SYSV=y
+BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_EUDEV=y
+# The fixed NanoKVM device set does not need the full udev hardware database.
+# BR2_PACKAGE_EUDEV_ENABLE_HWDB is not set
+BR2_ROOTFS_MERGED_USR=y
+BR2_TARGET_ENABLE_ROOT_LOGIN=y
+BR2_TARGET_GENERIC_ROOT_PASSWD="root"
+BR2_ENABLE_LOCALE_WHITELIST="C en_US en_US.utf8"
+BR2_ROOTFS_OVERLAY="$(TOPDIR)/board/cvitek/SG200X/overlay"
+BR2_ROOTFS_POST_BUILD_SCRIPT="$(TOPDIR)/../build/boards/sg200x/sg2002_licheervnano_sd_minimal/post-build.sh"
+BR2_PACKAGE_BUSYBOX_CONFIG_FRAGMENT_FILES="$(TOPDIR)/board/cvitek/SG200X/busybox-extra.config"
+
+# Filesystem management used by first-boot expansion and virtual media.
+BR2_PACKAGE_E2FSPROGS=y
+BR2_PACKAGE_E2FSPROGS_RESIZE2FS=y
+BR2_PACKAGE_EXFATPROGS=y
+BR2_PACKAGE_PARTED=y
+
+# NanoKVM runtime and network services.
+BR2_PACKAGE_AVAHI=y
+# BR2_PACKAGE_AVAHI_AUTOIPD is not set
+BR2_PACKAGE_AVAHI_DAEMON=y
+BR2_PACKAGE_BASH=y
+BR2_PACKAGE_CA_CERTIFICATES=y
+BR2_PACKAGE_LIBCURL=y
+BR2_PACKAGE_LIBCURL_CURL=y
+BR2_PACKAGE_ETHTOOL=y
+BR2_PACKAGE_HOSTAPD=y
+BR2_PACKAGE_HOSTAPD_WPA3=y
+BR2_PACKAGE_IPROUTE2=y
+BR2_PACKAGE_IPTABLES=y
+BR2_PACKAGE_IPUTILS=y
+BR2_PACKAGE_IW=y
+BR2_PACKAGE_NTP=y
+BR2_PACKAGE_NTP_NTPD=y
+BR2_PACKAGE_NTP_NTPDATE=y
+BR2_PACKAGE_OPENSSH=y
+# BR2_PACKAGE_OPENSSH_CLIENT is not set
+BR2_PACKAGE_OPENSSH_SERVER=y
+BR2_PACKAGE_OPENSSH_KEY_UTILS=y
+# Python is intentionally excluded from the minimal image.
+# BR2_PACKAGE_PYTHON3 is not set
+BR2_PACKAGE_WIRELESS_REGDB=y
+BR2_PACKAGE_WIRELESS_TOOLS=y
+BR2_PACKAGE_WIRELESS_TOOLS_LIB=y
+BR2_PACKAGE_WPA_SUPPLICANT=y
+BR2_PACKAGE_WPA_SUPPLICANT_WEXT=y
+BR2_PACKAGE_WPA_SUPPLICANT_AP_SUPPORT=y
+BR2_PACKAGE_WPA_SUPPLICANT_AUTOSCAN=y
+BR2_PACKAGE_WPA_SUPPLICANT_HOTSPOT=y
+BR2_PACKAGE_WPA_SUPPLICANT_WPA3=y
+BR2_PACKAGE_WPA_SUPPLICANT_CLI=y
+BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y
+BR2_PACKAGE_UTIL_LINUX_RFKILL=y
+
+# Board runtime, Wi-Fi firmware and video codec firmware.
+BR2_PACKAGE_AIC8800_SDIO_FIRMWARE=y
+BR2_PACKAGE_CVITEK_RISCV64_MUSL_SYSROOT=y
+BR2_PACKAGE_SG2002_CODEC_FIRMWARE=y
+BR2_TARGET_ROOTFS_EXT2=y
+BR2_TARGET_ROOTFS_EXT2_4=y
+BR2_TARGET_ROOTFS_EXT2_SIZE="112M"

build/boards/sg200x/sg2002_licheervnano_sd_minimal/config.json

@@ -0,0 +1,9 @@
+{
+    "ddr_cfg_list": [
+        "",
+        "ddr3_1866_x16",
+        "ddr3_2133_x16",
+        "ddr_auto_x16"
+    ],
+    "board_information": "NanoKVM, C906B + DDR 256MB"
+}

build/boards/sg200x/sg2002_licheervnano_sd_minimal/dts_riscv/sg2002_licheervnano_sd_minimal.dts

@@ -0,0 +1,272 @@
+/dts-v1/;
+#include "soph_base_riscv.dtsi"
+#include "soph_asic_qfn.dtsi"
+#include "soph_asic_sd.dtsi"
+#include "soph_default_memmap.dtsi"
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/gpio.h>
+
+&i2c0 {
+        status = "okay";
+        /delete-property/ scl-pinmux;
+        /delete-property/ sda-pinmux;
+        /delete-property/ scl-gpios;
+        /delete-property/ sda-gpios;
+};
+
+&i2c1 {
+        status = "okay";
+        /delete-property/ scl-pinmux;
+        /delete-property/ sda-pinmux;
+        /delete-property/ scl-gpios;
+        /delete-property/ sda-gpios;
+};
+
+&sd {
+        min-frequency = <400000>; // 400Khz
+        //max-frequency = <50000000>; // 50Mhz
+        max-frequency = <25000000>; // 25Mhz
+        //max-frequency = <10000000>; // 10Mhz
+        //max-frequency = <5000000>; // 5Mhz
+};
+
+&cvi_vo {
+#ifndef __UBOOT__
+	/delete-property/ reset-gpio;
+	/delete-property/ pwm-gpio;
+#else
+	// for uboot
+        reset-gpio = <&porte 0 1>;
+        pwm-gpio = <&porte 2 1>;
+#endif
+        /delete-property/ power-ct-gpio;
+
+};
+
+&mipi_tx {
+#ifndef __UBOOT__
+	// for linux kernel
+        reset-gpio = <&porte 0 1>;
+        pwm-gpio = <&porte 2 1>;
+#else
+        /delete-property/ reset-gpio;
+        /delete-property/ pwm-gpio;
+#endif
+        /delete-property/ power-ct-gpio;
+        status = "okay";
+};
+
+&uart0 {
+	clocks = <&clk CV181X_CLK_UART0>;
+	/delete-property/ clock-frequency;
+};
+
+&uart1 {
+        clocks = <&clk CV181X_CLK_UART1>;
+        /delete-property/ clock-frequency;
+        status = "okay";
+};
+
+&uart2 {
+        clocks = <&clk CV181X_CLK_UART2>;
+        /delete-property/ clock-frequency;
+        status = "okay";
+};
+
+&uart3 {
+        clocks = <&clk CV181X_CLK_UART3>;
+        /delete-property/ clock-frequency;
+	status = "okay";
+};
+
+&pwm0 {
+        status = "okay";
+};
+
+&pwm1 {
+      status = "okay";
+};
+
+&pwm2 {
+      status = "okay";
+};
+
+&i2c2 {
+        status = "disabled";
+        /delete-property/ scl-pinmux;
+        /delete-property/ sda-pinmux;
+        /delete-property/ scl-gpios;
+        /delete-property/ sda-gpios;
+};
+
+&i2c3 {
+        status = "okay";
+        /delete-property/ scl-pinmux;
+        /delete-property/ sda-pinmux;
+        /delete-property/ scl-gpios;
+        /delete-property/ sda-gpios;
+};
+
+&i2c4 {
+        status = "okay";
+        gt9xx: gt9xx@14 {
+                compatible = "goodix,gt9xx";
+                reg = <0x14>;
+                goodix,irq-gpio = <&porte 3 0>;
+                goodix,rst-gpio = <&porte 4 0>;
+                status = "okay";
+        };
+        hynitron: hynitron@5a {
+                compatible = "hynitron,hyn_ts", "hyn,7xx";
+                reg = <0x5a>;
+                irq-gpio = <&porte 3 0>;
+                hynitron,irq-gpio = <&porte 3 0>;
+                reset-gpio = <&porte 4 0>;
+                hynitron,reset-gpio = <&porte 4 0>;
+                max-touch-number = <5>;
+                hynitron,max-touch-number = <5>;
+                display-coords = <0 0 480 640>;
+                hynitron,display-coords = <368 552>;
+                pos-swap = <0>;
+                posx-reverse = <1>;
+                posy-reverse = <1>;
+                status = "okay";
+        };
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+
+        // /delete-node/ spidev@0;
+        st7789: st7789@0{
+		compatible = "sitronix,st7789";
+		reg = <0>;
+		status = "disabled";
+		spi-max-frequency = <80000000>;
+		spi-cpol;
+		spi-cpha;
+		rotate = <0>;
+		fps = <60>;
+		rgb;
+		buswidth = <8>;
+		dc = <&porte 20 GPIO_ACTIVE_HIGH>;
+		reset = <&porta 14 GPIO_ACTIVE_LOW>;
+		debug = <0>;
+	};
+};
+
+&spi3 {
+	status = "okay";
+};
+
+&dac {
+        status = "okay";
+        /delete-property/ mute-gpio-r;
+};
+
+&fb_reserved {
+        status = "okay";
+};
+
+&cvi_fb {
+        status = "okay";
+};
+
+&mipi_rx {
+        snsr-reset = <&porte 1 GPIO_ACTIVE_LOW>;
+};
+
+/ {
+        model = "LicheeRv Nano";
+
+	spi4: spi4@gpio {
+		compatible = "spi-gpio";
+		sck-gpio = <&porta 22 0>;
+		miso-gpio = <&porta 23 0>;
+		mosi-gpio = <&porta 25 0>;
+		cs-gpio = <&porta 24 GPIO_ACTIVE_LOW>;
+		num-chipselects = <1>;
+		status = "okay";
+
+		spidev@0 {
+			compatible = "spidev";
+			reg = <0>;
+		};
+	};
+
+	i2c5: i2c5@gpio {
+		compatible = "i2c-gpio";
+                scl-gpios = <&porta 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                sda-gpios = <&porta 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                i2c-gpio,delay-us = <5>;
+                status = "okay";
+	};
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                key-user {
+                        label = "User Key";
+                        linux,code = <KEY_DISPLAYTOGGLE>;
+                        debounce-interval = <1>;
+                        gpios = <&porta 30 1>;
+                };
+        };
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-user {
+			gpios = <&porta 14 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "activity";
+		};
+	};
+
+	// buggy pwm driver, not working, please use userspace pwm api
+	/*
+	lcd0_backlight: pwm-backlight@0 {
+		compatible = "pwm-backlight";
+		pwm-names = "backlight";
+		pwms = <&pwm2 2 50000000>; // 20Khz
+		brightness-levels = <0 2 4 8 16 32 64 128 255>;
+		default-brightness-level = <4>;
+	};
+	*/
+
+        wifisd:wifi-sd@4320000 {
+                compatible = "cvitek,cv181x-sdio";
+                bus-width = <4>;
+                reg = <0x0 0x4320000 0x0 0x1000>;
+                reg_names = "core_mem";
+                src-frequency = <375000000>;
+                min-frequency = <400000>; // 400Khz
+                //max-frequency = <50000000>; // 50Mhz
+                //max-frequency = <45000000>; // 45Mhz
+                //max-frequency = <40000000>; // 40Mhz
+                //max-frequency = <35000000>; // 35Mhz
+                //max-frequency = <30000000>; // 30Mhz
+                max-frequency = <25000000>; // 25Mhz
+                //max-frequency = <20000000>; // 20Mhz
+                //max-frequency = <15000000>; // 15Mhz
+                //max-frequency = <10000000>; // 10Mhz
+                //max-frequency = <5000000>; // 5Mhz
+                64_addressing;
+                reset_tx_rx_phy;
+                non-removable;
+                pll_index = <0x7>;
+                pll_reg = <0x300207C>;
+                no-mmc;
+                no-sd;
+                status = "okay";
+                interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-parent = <&plic0>;
+        };
+};

build/boards/sg200x/sg2002_licheervnano_sd_minimal/partition/partition_sd.xml

@@ -0,0 +1,4 @@
+<physical_partition type="sd">
+    <partition label="BOOT" size_in_kb="80960" readonly="false" file="boot.sd"/>
+    <partition label="ROOTFS" size_in_kb="1581056" readonly="false" file="rootfs.sd" />
+</physical_partition>

build/boards/sg200x/sg2002_licheervnano_sd_minimal/post-build.sh

@@ -0,0 +1,43 @@
+#!/bin/sh
+
+set -eu
+
+target_dir=$1
+
+# Production NanoKVM uses its own server and multimedia libraries. SDK sample
+# programs and development metadata are not needed at runtime.
+find "$target_dir/mnt/system/usr/bin" -type f \
+	\( -name 'sample_*' -o -name '*_test' -o -name 'test_*' -o -name 'ive_stress' -o -name 'sensor_test' \) \
+	-delete 2>/dev/null || true
+
+touch "$target_dir/etc/nanokvm-minimal"
+
+# The minimal board uses AIC8800; do not ship or load the unused 8733bs driver.
+rm -f "$target_dir/mnt/system/ko/3rd/8733bs.ko"
+if [ -f "$target_dir/etc/init.d/S25wifimod" ]; then
+	sed -i '/insmod 3rd\/8733bs\.ko/d' "$target_dir/etc/init.d/S25wifimod"
+fi
+
+# Do not retain stale hardware database files in an incremental build.
+rm -rf "$target_dir/etc/udev/hwdb.bin" "$target_dir/etc/udev/hwdb.d"
+
+# Keep only the sensor selected by the minimal board configuration.
+rm -f \
+	"$target_dir/mnt/system/usr/lib/libsns_gc4653.so" \
+	"$target_dir/mnt/system/usr/lib/libov_ov2685.so" \
+	"$target_dir/mnt/system/usr/lib/libsns_os04a10.so" \
+	"$target_dir/mnt/system/usr/lib/libsns_sc035gs.so"
+
+# LT6911 has no matching SDK ISP tuning blob; remove stale blobs from reuse builds.
+find "$target_dir/mnt/cfg/param" "$target_dir/mnt/cfg/tmp_secure" \
+	-type f -delete 2>/dev/null || true
+
+find "$target_dir" -type f \( -name '*.a' -o -name '*.la' \) -delete
+rm -rf \
+	"$target_dir/usr/include" \
+	"$target_dir/usr/share/doc" \
+	"$target_dir/usr/share/info" \
+	"$target_dir/usr/share/man" \
+	"$target_dir/usr/share/pkgconfig" \
+	"$target_dir/usr/lib/pkgconfig" \
+	"$target_dir/usr/lib/cmake"

build/boards/sg200x/sg2002_licheervnano_sd_minimal/sg2002_licheervnano_sd_minimal_defconfig

@@ -0,0 +1,23 @@
+CONFIG_CHIP_sg2002=y
+CONFIG_BOARD_licheervnano_sd_minimal=y
+CONFIG_DDR_CFG_ddr3_1866_x16=y
+CONFIG_ARCH="riscv"
+CONFIG_CROSS_COMPILE="riscv64-unknown-linux-musl-"
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_KERNEL_ENTRY_HACK=y
+CONFIG_KERNEL_ENTRY_HACK_ADDR="0x80200000"
+CONFIG_TOOLCHAIN_MUSL_RISCV64=y
+CONFIG_BOOT_IMAGE_SINGLE_DTB=y
+# CONFIG_FLASH_SIZE_SHRINK is not set
+CONFIG_CP_EXT_WIRELESS=y
+CONFIG_STORAGE_TYPE_sd=y
+CONFIG_MIPI_PANEL_ZCT2133V1=y
+CONFIG_SENSOR_LONTIUM_LT6911=y
+CONFIG_UBOOT_2021_10=y
+CONFIG_KERNEL_SRC_5.10=y
+CONFIG_KERNEL_UNCOMPRESSED=y
+# CONFIG_SKIP_RAMDISK is not set
+# CONFIG_SENSOR_TUNING_PARAM_sg200x_src_ov_os04a10=y
+# CONFIG_ROOTFS_OVERLAYFS is not set
+# CONFIG_ENABLE_FREERTOS=y
+# CONFIG_TARGET_PACKAGE_GATORD is not set

build/boards/sg200x/sg2002_licheervnano_sd_minimal/u-boot/cvi_board_init.c

@@ -0,0 +1,164 @@
+__attribute__((optimize("O0")))
+// 1.26ms
+void suck_loop(uint64_t loop) {
+        loop = loop * 50 * 100;
+        uint64_t a;
+        while (loop > 0) {
+                a = loop / (uint64_t)99;
+                a = loop / (uint64_t)77;
+                a = loop / (uint64_t)55;
+                a = loop / (uint64_t)33;
+                a = loop / (uint64_t)11;
+                a = loop / (uint64_t)999;
+                a = loop / (uint64_t)777;
+                a = loop / (uint64_t)555;
+                a = loop / (uint64_t)333;
+                a = loop / (uint64_t)111;
+                a = loop / (uint64_t)9999;
+                a = loop / (uint64_t)7777;
+                a = loop / (uint64_t)5555;
+                a = loop / (uint64_t)3333;
+                a = loop / (uint64_t)1111;
+                a = loop / (uint64_t)99999;
+                a = loop / (uint64_t)77777;
+                a = loop / (uint64_t)55555;
+                a = loop / (uint64_t)33333;
+                a = loop / (uint64_t)11111;
+                loop--;
+        }
+}
+
+static inline void user_led_on(void) {
+	uint32_t val;
+
+        val = mmio_read_32(0x03020000);
+        val |= (1 << 14);
+        mmio_write_32(0x03020000, val);
+}
+
+static inline void user_led_off(void) {
+	uint32_t val;
+
+        val = mmio_read_32(0x03020000);
+        val &= ~(1 << 14);
+        mmio_write_32(0x03020000, val);
+}
+
+static inline void user_led_toggle(void) {
+	uint32_t val;
+
+        val = mmio_read_32(0x03020000);
+        val ^= (1 << 14);
+        mmio_write_32(0x03020000, val);
+}
+
+int cvi_board_init(void)
+{
+        uint32_t val;
+
+	// user led
+	mmio_write_32(0x03001038, 0x3); // GPIOA 14 GPIO_MODE
+	val = mmio_read_32(0x03020004); // GPIOA DIR
+        val |= (1 << 14); // output
+        mmio_write_32(0x03020004, val);
+	user_led_toggle();
+
+        // wifi power reset
+        mmio_write_32(0x0300104C, 0x3); // GPIOA 26
+        val = mmio_read_32(0x03020004); // GPIOA DIR
+        val |= (1 << 26); // output
+        mmio_write_32(0x03020004, val);
+
+        val = mmio_read_32(0x03020000); // signal level
+        val &= ~(1 << 26); // set level to low
+        mmio_write_32(0x03020000, val);
+
+        suck_loop(50);
+	user_led_toggle();
+
+        val = mmio_read_32(0x03020000); // signal level
+        val |= (1 << 26); // set level to high
+        mmio_write_32(0x03020000, val);
+
+        // wifi sdio pinmux
+        mmio_write_32(0x030010D0, 0x0); // D3
+        mmio_write_32(0x030010D4, 0x0); // D2
+        mmio_write_32(0x030010D8, 0x0); // D1
+        mmio_write_32(0x030010DC, 0x0); // D0
+        mmio_write_32(0x030010E0, 0x0); // CMD
+        mmio_write_32(0x030010E4, 0x0); // CLK
+
+        // spi2 pinmux
+        // mmio_write_32(0x030010D0, 0x1); // CS
+        // mmio_write_32(0x030010DC, 0x1); // MISO
+        // mmio_write_32(0x030010E0, 0x1); // MOSI
+        // mmio_write_32(0x030010E4, 0x1); // SCK
+        // mmio_write_32(0x030010D8, 0x3); // DC
+        // mmio_write_32(0x03001038, 0x3); // RESET
+
+        // uart bluetooth
+        mmio_write_32(0x03001070, 0x1); // GPIOA 28 UART1 TX
+        mmio_write_32(0x03001074, 0x1); // GPIOA 29 UART1 RX
+        mmio_write_32(0x03001068, 0x4); // GPIOA 18 UART1 CTS
+        mmio_write_32(0x03001064, 0x4); // GPIOA 19 UART1 RTS
+
+        // PWM
+        //mmio_write_32(0x03001068, 0x2); // GPIOA 18 PWM 6
+
+        // lcd reset
+        mmio_write_32(0x030010A4, 0x0); // PWRGPIO 0 GPIO_MODE
+
+	user_led_toggle();
+        // lcd backlight
+        //mmio_write_32(0x030010EC, 0x0); // GPIOB 0 PWM0_BUCK
+	// for licheervnano alpha
+	val = mmio_read_32(0x03021000); // signal level
+        val |= (1 << 0); // set level to high
+        mmio_write_32(0x03021000, val);
+        val = mmio_read_32(0x03021004); // GPIOB DIR
+        val |= (1 << 0); // output
+        mmio_write_32(0x03021004, val);
+        mmio_write_32(0x030010EC, 0x3); // GPIOB 0 GPIO_MODE
+
+	// for licheervnano beta
+	//mmio_write_32(0x030010ac, 0x4); // PWRGPIO 2 PWM 10
+	mmio_write_32(0x030010ac, 0x0); // PWRGPIO 2 GPIO_MODE
+
+        // camera function
+        //mmio_write_32(0x0300116C, 0x5); // RX4N CAM_MCLK0 for alpha
+        mmio_write_32(0x0300118C, 0x5); // RX0N CAM_MCLK1 for beta
+
+	// spi1 on mipi csi
+	/*
+	mmio_write_32(0x0300116C, 0x7); // spi1 clk   GPIOC2 MIPI_RX4N
+	mmio_write_32(0x03001170, 0x7); // spi1 cs    GPIOC3 MIPI_RX4P
+	mmio_write_32(0x03001174, 0x7); // spi1 miso  GPIOC4 MIPI_RX3N
+	mmio_write_32(0x03001178, 0x7); // spi1 mosi  GPIOC5 MIPI_RX3P
+	*/
+
+
+        // camera/tp i2c
+        mmio_write_32(0x03001090, 0x5); // PWR_GPIO6 IIC4_SCL
+        mmio_write_32(0x03001098, 0x5); // PWR_GPIO8 IIC4_SDA
+
+        // tp function
+        mmio_write_32(0x03001084, 0x3); // PWR_SEQ1 PWR_GPIO[3]
+        mmio_write_32(0x03001088, 0x3); // PWR_SEQ2 PWR_GPIO[4]
+        mmio_write_32(0x05027078, 0x11);// Unlock PWR_GPIO[3]
+        mmio_write_32(0x0502707c, 0x11);// Unlock PWR_GPIO[4]
+
+	// bitbang i2c
+        mmio_write_32(0x0300103C, 0x03); // GPIOA 15 GPIO_MODE
+	mmio_write_32(0x03001058, 0x03); // GPIOA 27 GPIO_MODE
+
+	// bitbang spi
+	mmio_write_32(0x03001060, 0x03); // GPIOA 24 GPIO_MODE
+	mmio_write_32(0x0300105C, 0x03); // GPIOA 23 GPIO_MODE
+	mmio_write_32(0x03001054, 0x03); // GPIOA 25 GPIO_MODE
+	mmio_write_32(0x03001050, 0x03); // GPIOA 22 GPIO_MODE
+
+        // wait hardware bootup
+        suck_loop(50);
+	user_led_off();
+        return 0;
+}

build/boards/sg200x/sg2002_licheervnano_sd_minimal/u-boot/sg2002_licheervnano_sd_minimal_defconfig

@@ -0,0 +1,66 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="soph_asic"
+CONFIG_IDENT_STRING=" soph"
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_TARGET_CVITEK_CV181X=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_PROMPT="soph# "
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNLZ4 is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_ITEST is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CVI_SD_UPDATE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_CVITEK=y
+CONFIG_MTD=y
+# CONFIG_PHY_SMSC is not set
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_CVITEK=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_LZ4=y
+CONFIG_LZMA=y
+# CONFIG_TOOLS_LIBCRYPTO is not set
+CONFIG_ENV_IS_NOWHERE=y
+
+# for licheervnano
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_BUF_ADDR=0x81800000
+CONFIG_FASTBOOT_BUF_SIZE=0x1000000
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_DISPLAY=y
+CONFIG_DM_VIDEO=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_CMD_VIDCONSOLE=y
+CONFIG_VIDEO_BPP16=y
+CONFIG_VIDEO_BPP32=y
+CONFIG_VIDEO_CVITEK=y
+CONFIG_DISPLAY_CVITEK_MIPI=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_BOOTLOGO=y
+CONFIG_CMD_CVI_VO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MBR=y

build/common_functions.sh

@@ -242,6 +242,28 @@ function pack_burn_image
   popd
 )}
 
+function pack_usbdl_image
+{(
+  pushd "$OUTPUT_DIR"
+  [ -d tmp ] && rm -rf tmp
+  set -eux
+  cp -rf $TOOLS_PATH/cv181x/usb_dl $OUTPUT_DIR
+  cd usb_dl
+  unzip -o $OUTPUT_DIR/upgrade.zip
+  cp $OUTPUT_DIR/fip.bin ./
+  set +eux
+  echo "========================================="
+  echo ""
+  echo "usb flash command:"
+  echo ""
+  echo "cd $OUTPUT_DIR/usb_dl && python3 cv181x_dl.py"
+  echo ""
+  echo ""
+  echo "========================================="
+
+  popd
+)}
+
 function pack_prog_img
 {(
   local tmp_dir

build/envsetup_soc.sh

@@ -525,6 +525,7 @@ function clean_ramdisk()
   rm -rf "${RAMDISK_PATH:?}"/"$RAMDISK_OUTPUT_BASE"
   rm -rf "$SYSTEM_OUT_DIR"
   rm -rf "$ROOTFS_DIR"
+  rm -rf "${BR_OUTPUT_DIR:?}"
 }
 
 function build_access_guard_turnkey_app()
@@ -621,6 +622,7 @@ function build_all()
   pack_data || return $?
   pack_system || return $?
   pack_upgrade || return $?
+  pack_usbdl_image || return $?
   pack_burn_image || return $?
 )}
 
@@ -733,6 +735,11 @@ function cvi_setup_env()
 
   PROJECT_FULLNAME="$CHIP"_"$BOARD"
 
+  # NanoKVM has no display output; do not build or load the vendor bootlogo.
+  if [[ "$PROJECT_FULLNAME" == "sg2002_licheervnano_sd" ]]; then
+    ENABLE_BOOTLOGO=0
+  fi
+
   # output folder path
   INSTALL_PATH="$TOP_DIR"/install
   OUTPUT_DIR="$INSTALL_PATH"/soc_"$PROJECT_FULLNAME"
@@ -875,9 +882,16 @@ function cvi_setup_env()
   # buildroot config
   export BR_DIR="$TOP_DIR"/buildroot
   export BR_BOARD=cvitek_${CHIP_ARCH}_${SDK_VER}
-  export BR_OVERLAY_DIR=${BR_DIR}/board/cvitek/${CHIP_ARCH}/overlay
-  export BR_DEFCONFIG=${BR_BOARD}_defconfig
-  echo "BR2_DEFCONFIG:  ${BRDEFCONFIG}"
+  export BR_OUTPUT_DIR=${BR_DIR}/output/${PROJECT_FULLNAME}
+  export BR_BASE_OVERLAY_DIR=${BR_DIR}/board/cvitek/${CHIP_ARCH}/overlay
+  export BR_OVERLAY_DIR=${BR_OUTPUT_DIR}/overlay
+  export BR_DEFCONFIG=defconfig
+  export BR2_DEFCONFIG=${BR_DIR}/configs/${BR_BOARD}_defconfig
+  board_br_defconfig="$BUILD_PATH/boards/${CHIP_ARCH,,}/$PROJECT_FULLNAME/buildroot.config"
+  if [ -f "$board_br_defconfig" ]; then
+    export BR2_DEFCONFIG=$board_br_defconfig
+  fi
+  echo "BR2_DEFCONFIG:  ${BR2_DEFCONFIG}"
 }
 
 cvi_print_env()

build/scripts/fip_v2.mk

@@ -25,6 +25,7 @@ fsbl%: export FSBL_SECURE_BOOT_SUPPORT=${CONFIG_FSBL_SECURE_BOOT_SUPPORT}
 fsbl%: export ARCH=$(call qstrip,${CONFIG_ARCH})
 fsbl%: export OD_CLK_SEL=${CONFIG_OD_CLK_SEL}
 fsbl%: export VC_CLK_OVERDRIVE=${CONFIG_VC_CLK_OVERDRIVE}
+fsbl%: export TPU_PERF_MODE=$(shell if [ "${CONFIG_CHIP_cv1812cp}" = "y" ] || [ "${CONFIG_CHIP_sg2002}" = "y" ]; then echo "y";else echo "n";fi)
 fsbl-build: u-boot-build memory-map
 	$(call print_target)
 	${Q}mkdir -p ${FSBL_PATH}/build

build/sensors/sensor_list.json

@@ -31,6 +31,7 @@
 		"OV_OS04C10_SLAVE",
 		"OV_OS08A20",
 		"OV_OS08A20_SLAVE",
+		"OV_OV2685",
 		"OV_OV4689",
 		"OV_OV5647",
 		"OV_OV6211",

build/tools/common/sd_tools/genimage_rootless.cfg

@@ -5,9 +5,12 @@ image boot.vfat {
                         "fip.bin",
                         "rawimages/boot.sd",
 			"usb.dev",
-			"usb.rndis0",
-			"fb",
+			"usb.disk0",
+                        "usb.rndis0",
 			"wifi.sta",
+			"gt9xx",
+			"logo.jpeg",
+			"ver",
                 }
         }
         size = 16M 

build/tools/common/sd_tools/sd_gen_burn_image_rootless.sh

@@ -16,7 +16,8 @@ fi
 output_dir=$1
 echo ${output_dir}
 set -eu
-image=`LC_ALL=C date +%F-%R | sed -e 's/:/-/g' | tr -d '( ):'`.img
+git_id=$(git rev-parse HEAD | head -c 6)
+image=$(LC_ALL=C date +%F-%R | sed -e 's/:/-/g' | tr -d '( ):')-${git_id}.img
 THISDIR=$(dirname $(realpath $0))
 mkdir -pv ${output_dir}/tmp/
 mkdir -pv ${output_dir}/root/
@@ -26,11 +27,14 @@ cp -fv ${output_dir}/fip.bin ${output_dir}/input/
 cp -fv ${output_dir}/rawimages/boot.sd ${output_dir}/input/rawimages/
 cp -fv ${output_dir}/rawimages/rootfs.sd ${output_dir}/input/
 touch ${output_dir}/input/usb.dev
+touch ${output_dir}/input/usb.disk0
 touch ${output_dir}/input/usb.rndis0
-touch ${output_dir}/input/fb
 touch ${output_dir}/input/wifi.sta
 touch ${output_dir}/input/gt9xx
+touch ${output_dir}/input/fb
+echo ${image} > ${output_dir}/input/ver
 cp -fv ${THISDIR}/genimage_rootless.cfg ${output_dir}/genimage.cfg
+cp -fv ${THISDIR}/logo.jpeg ${output_dir}/input/logo.jpeg
 sed -i -e "s/duo.img/${image}/g" ${output_dir}/genimage.cfg
 cd ${output_dir}/
 ${THISDIR}/genimage

build/tools/cv181x/usb_dl/rom_usb_dl/XmlParser.py

@@ -83,6 +83,8 @@ class XmlParser:
 
         if self.storage == "emmc":
             self.__calEmmcOffset(parts)
+        if self.storage == "sd":
+            self.__calEmmcOffset(parts)
         elif self.storage == "spinor":
             self.__calNorOffset(parts)
         elif self.storage == "spinand":

build/tools/cv181x/usb_dl/rom_usb_dl/cv181x_uboot_usb_download.py

@@ -41,8 +41,8 @@ def parse_Args():
         type=str)
     parser.add_argument(
         '--pid',
-        metavar='1001',
-        default='1001',
+        metavar='1000',
+        default='1000',
         type=str)
     parser.add_argument(
         "-v",

buildroot/board/cvitek/SG200X/overlay/etc/avahi/avahi-daemon.conf

@@ -0,0 +1,69 @@
+# This file is part of avahi.
+#
+# avahi is free software; you can redistribute it and/or modify it
+# under the terms of the GNU Lesser General Public License as
+# published by the Free Software Foundation; either version 2 of the
+# License, or (at your option) any later version.
+#
+# avahi is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with avahi; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+# USA.
+
+# See avahi-daemon.conf(5) for more information on this configuration
+# file!
+
+[server]
+#host-name=foo
+#domain-name=local
+#browse-domains=0pointer.de, zeroconf.org
+use-ipv4=yes
+use-ipv6=yes
+#allow-interfaces=eth0
+#deny-interfaces=eth1
+#check-response-ttl=no
+#use-iff-running=no
+#enable-dbus=yes
+#disallow-other-stacks=no
+#allow-point-to-point=no
+#cache-entries-max=4096
+#clients-max=4096
+#objects-per-client-max=1024
+#entries-per-entry-group-max=32
+ratelimit-interval-usec=1000000
+ratelimit-burst=1000
+
+[wide-area]
+enable-wide-area=yes
+
+[publish]
+#disable-publishing=no
+#disable-user-service-publishing=no
+#add-service-cookie=no
+publish-addresses=yes
+publish-hinfo=yes
+publish-workstation=yes
+#publish-domain=yes
+#publish-dns-servers=192.168.50.1, 192.168.50.2
+#publish-resolv-conf-dns-servers=yes
+#publish-aaaa-on-ipv4=yes
+#publish-a-on-ipv6=no
+
+[reflector]
+#enable-reflector=no
+#reflect-ipv=no
+#reflect-filters=_airplay._tcp.local,_raop._tcp.local
+
+[rlimits]
+#rlimit-as=
+#rlimit-core=0
+#rlimit-data=8388608
+#rlimit-fsize=0
+#rlimit-nofile=768
+#rlimit-stack=8388608
+#rlimit-nproc=3

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S00kmod

@@ -1,37 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = "start" ]
-then
-	. /etc/profile
-	printf "load kernel module: "
-	cd /mnt/system/ko/
-	insmod soph_sys.ko
-	insmod soph_base.ko
-	insmod soph_rtos_cmdqu.ko
-	insmod soph_fast_image.ko
-	insmod soph_mipi_rx.ko
-	insmod soph_snsr_i2c.ko
-	insmod soph_vi.ko
-	insmod soph_vpss.ko
-	insmod soph_dwa.ko
-	insmod soph_vo.ko
-	insmod soph_mipi_tx.ko
-	insmod soph_rgn.ko
-	insmod soph_wdt.ko
-	insmod soph_clock_cooling.ko
-	insmod soph_tpu.ko
-	insmod soph_vcodec.ko
-	insmod soph_jpeg.ko
-	insmod soph_vc_driver.ko MaxVencChnNum=9 MaxVdecChnNum=9
-	insmod soph_rtc.ko
-	insmod soph_ive.ko
-	insmod soph_mon.ko
-	insmod soph_pwm.ko
-	insmod soph_saradc.ko
-	insmod soph_wiegand.ko
-	insmod cfg80211.ko
-	insmod 3rd/aic8800_bsp.ko
-	insmod 3rd/aic8800_fdrv.ko
-	echo "OK"
-	exit 0
-fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S00pmu

@@ -0,0 +1,31 @@
+#!/bin/sh
+
+if ! command -v i2cget &> /dev/null
+then
+    echo "i2cdetect not find, please install i2c-tools"
+    exit 1
+fi
+
+pmu_version=$(i2cget -y 4 0x34 0x03)
+pmu_version=$((pmu_version & 0xCF))
+
+chip_id_1=$(printf "%d" 0x47)
+chip_id_2=$(printf "%d" 0x4a)
+
+if [ "$pmu_version" -eq "$chip_id_1" ] || [ "$pmu_version" -eq "$chip_id_2" ]; then
+    case "$1" in
+    start)
+        exec /usr/bin/axp2101
+        echo "Starting PMU: OK\n"
+    ;;
+    stop)
+        runlevel=$(cat /run/runlevel | awk '{ print $1 }')
+        if [ "$runlevel" = "0" ]; then
+            printf "Stopping PMU\n"
+            value=$(i2cget -y 4 0x34 0x10)
+            value=$((value | 0x01))
+            i2cset -y 4 0x34 0x10 $value
+        fi
+    ;;
+    esac
+fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S01fs

@@ -1,12 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = "start" ]
-then
-	. /etc/profile
-	printf "mounting filesystem : "
-	mkdir -p /boot
-	mount -t vfat /dev/mmcblk0p1 /boot
-	mount -t configfs configfs /sys/kernel/config
-	mount -t debugfs debugfs /sys/kernel/debug
-	echo "OK"
-fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S02config

@@ -8,11 +8,23 @@ then
 	then
 		cp -vf /boot/sshd_config /etc/ssh/sshd_config
 	fi
+	if [ -e /boot/resolv.conf ]
+	then
+		rm -rf /etc/resolv.conf
+		cp -vf /boot/resolv.conf /etc/resolv.conf
+	fi
 	if [ -e /boot/input-event-daemon ]
 	then
-		chmod 0644 /etc/input-event-daemon.conf
+		if [ ! -e /etc/input-event-daemon.conf ]
+		then
+			cp /etc/input-event-daemon.conf.bak /etc/input-event-daemon.conf
+		fi
 	else
-		chmod 0000 /etc/input-event-daemon.conf
+		if [ -e /etc/input-event-daemon.conf ]
+		then
+			cp /etc/input-event-daemon.conf /etc/input-event-daemon.conf.bak
+			rm /etc/input-event-daemon.conf
+		fi
 	fi
 	if [ -e /boot/rc.local ]
 	then
@@ -24,7 +36,41 @@ then
 	fi
 	if [ -e /boot/console_handler.sh ]
 	then
-		cp /boot/ttyGS0_handler.sh /etc/ttyGS0_handler.sh
+		cp /boot/console_handler.sh /etc/console_handler.sh
+	fi
+	if [ -e /boot/alpha ]
+	then
+		if [ ! -e /mnt/data/sensor_cfg.ini ]
+		then
+			cp /mnt/data/sensor_cfg.ini.alpha /mnt/data/sensor_cfg.ini
+		fi
+		if [ $(cat /mnt/data/sensor_cfg.ini | wc -l) -eq 0 ]
+		then
+			cp /mnt/data/sensor_cfg.ini.beta /mnt/data/sensor_cfg.ini
+		fi
+		# MIPI RX 4N PINMUX MCLK0
+		devmem 0x0300116C 32 0x5
+		# MIPI RX 0N PINMUX MIPIP RX 0N
+		devmem 0x0300118C 32 0x3
+		echo " alpha "
+	else
+		if [ ! -e /mnt/data/sensor_cfg.ini ]
+		then
+			cp /mnt/data/sensor_cfg.ini.beta /mnt/data/sensor_cfg.ini
+		fi
+		if [ $(cat /mnt/data/sensor_cfg.ini | wc -l) -eq 0 ]
+		then
+			cp /mnt/data/sensor_cfg.ini.beta /mnt/data/sensor_cfg.ini
+		fi
+		# MIPI RX 4N PINMUX MIPI RX 4N
+		devmem 0x0300116C 32 0x3
+		# MIPI RX 0N PINMUX MCLK1
+		devmem 0x0300118C 32 0x5
+		echo -n " beta "
+	fi
+	if [ -e /boot/kvmtest ]
+	then
+		cp /mnt/data/sensor_cfg.ini.LT /mnt/data/sensor_cfg.ini
 	fi
 	echo "OK"
 fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S03usbdev

@@ -1,90 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = "start" ]
-then
-	. /etc/profile
-	if [ -e /boot/usb.host ]
-	then
-		echo "usb mode: host"
-		echo host > /proc/cviusb/otg_role
-	elif [ -e /boot/usb.dev ]
-	then
-		echo "usb mode: device"
-		cd /sys/kernel/config/usb_gadget
-		mkdir g0
-		cd g0
-		if [ -e /boot/usb.idVendor ]
-		then
-			cat /boot/usb.idVendor > idVendor
-		else
-			echo 0x3346 > idVendor
-		fi
-		if [ -e /boot/usb.idProduct ]
-		then
-			cat /boot/usb.idProduct > idProduct
-		else
-			echo 0x1009 > idProduct
-		fi
-		mkdir strings/0x409
-		if [ -e /boot/usb.serialnumber ]
-		then
-			cat /boot/usb.serialnumber > strings/0x409/serialnumber
-		else
-			echo '0123456789ABCDEF' > strings/0x409/serialnumber
-		fi
-		if [ -e /boot/usb.manufacturer ]
-		then
-			cat /boot/usb.manufacturer > strings/0x409/manufacturer
-		else
-			echo 'sipeed' > strings/0x409/manufacturer
-		fi
-		if [ -e /boot/usb.product ]
-		then
-			cat /boot/usb.product > strings/0x409/product
-		else
-			echo 'licheervnano' > strings/0x409/product
-		fi
-		mkdir configs/c.1
-		if [ -e /boot/usb.GS0 ]
-		then
-			mkdir functions/acm.GS0
-			ln -s functions/acm.GS0 configs/c.1/
-		fi
-		if [ -e /boot/usb.rndis0 ]
-		then
-			mkdir functions/rndis.usb0
-			ln -s functions/rndis.usb0 configs/c.1/
-		fi
-		if [ -e /boot/usb.disk0 ]
-		then
-			mkdir functions/mass_storage.disk0
-			ln -s functions/mass_storage.disk0 configs/c.1/
-			echo 1 > functions/mass_storage.disk0/lun.0/removable
-			if [ -e /boot/usb.disk0.ro ]
-			then
-				echo 1 > functions/mass_storage.disk0/lun.0/ro
-				echo 1 > functions/mass_storage.disk0/lun.0/cdrom
-			fi
-			disk=$(cat /boot/usb.disk0)
-			if [ -z "${disk}" ]
-			then
-				if [ ! -e /mnt/usbdisk.img ]
-				then
-					dd if=/dev/zero of=/mnt/usbdisk.img bs=1M count=16
-					mkfs.vfat /mnt/usbdisk.img
-				fi
-				echo /mnt/usbdisk.img > functions/mass_storage.disk0/lun.0/file
-			else
-				cat /boot/usb.disk0 > functions/mass_storage.disk0/lun.0/file
-			fi
-		fi
-		ls /sys/class/udc/ | cat > UDC
-		echo device > /proc/cviusb/otg_role
-	fi
-fi
-
-if [ "$1" = "stop" ]
-then
-	echo '' > /sys/kernel/config/usb_gadget/g0/UDC
-	echo host > /proc/cviusb/otg_role
-fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S05tp

@@ -1,12 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = "start" ]
-then
-	. /etc/profile
-	if [ -e /boot/gt9xx ]
-	then
-		echo "load gt9xx touchscreen driver"
-		insmod /mnt/system/ko/3rd/gt9xx.ko
-	fi
-	exit 0
-fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S10uuid

@@ -13,7 +13,7 @@ hex2mac() {
 
 if [ "${1}" = start ]
 then
-	prefix=licheervnano
+	prefix=kvm
 	if [ -e /boot/hostname.prefix ]
 	then
 		prefix=$(cat /boot/hostname.prefix)

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S25wifimod

@@ -0,0 +1,14 @@
+#!/bin/sh
+
+if [ "$1" = "start" ]
+then
+	. /etc/profile
+	printf "load wifi kernel module: "
+	cd /mnt/system/ko/
+	insmod cfg80211.ko
+	insmod 3rd/aic8800_bsp.ko
+	insmod 3rd/aic8800_fdrv.ko
+	insmod 3rd/8733bs.ko
+	echo "OK"
+	exit 0
+fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S30eth

@@ -1,33 +0,0 @@
-#!/bin/sh
-
-. /etc/profile
-
-start() {
-	printf "start ethernet: "
-	if [ ! -e /boot/eth.nodhcp ]
-	then
-		(udhcpc -i eth0 -t 10 -T 1 -A 5 -b -p /run/udhcpc.eth0.pid) &
-	fi
-	echo "OK"
-}
-
-stop() {
-	kill `cat /run/udhcpc.eth0.pid`
-	rm /run/udhcpc.eth0.pid
-}
-
-restart() {
-	start
-	stop
-}
-
-if [ "${1}" = "start" ]
-then
-	start
-elif [ "${1}" = "stop" ]
-then
-	stop
-elif [ "${1}" = "restart" ]
-then
-	restart
-fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S30wifi

@@ -1,147 +0,0 @@
-#!/bin/sh
-
-. /etc/profile
-
-gen_hostapd_conf() {
-	ssid="${1}"
-	pass="${2}"
-	echo "ctrl_interface=/var/run/hostapd"
-	echo "ctrl_interface_group=0"
-	echo "ssid=${ssid}"
-	echo "hw_mode=g"
-	echo "channel=1"
-	echo "beacon_int=100"
-	echo "dtim_period=2"
-	echo "max_num_sta=255"
-	echo "rts_threshold=-1"
-	echo "fragm_threshold=-1"
-	echo "macaddr_acl=0"
-	echo "auth_algs=3"
-	echo "wpa=2"
-	echo "wpa_passphrase=${pass}"
-	echo "ieee80211n=1"
-}
-
-
-
-gen_udhcpd_conf() {
-        interface=${1}
-        ipv4_prefix=${2}
-        echo "start ${ipv4_prefix}.100"
-        echo "end ${ipv4_prefix}.200"
-        echo "interface ${interface}"
-        echo "pidfile /var/run/udhcpd.${interface}.pid"
-        echo "lease_file /var/lib/misc/udhcpd.${interface}.leases"
-        echo "option subnet 255.255.255.0"
-        echo "option lease 864000"
-}
-
-start() {
-	if [ -e /boot/wifi.sta ]
-	then
-		if [ -e /boot/wpa_supplicant.conf ]
-		then
-			cp /boot/wpa_supplicant.conf /etc/wpa_supplicant.conf
-		else
-			echo "wifi mode: sta"
-			ssid="licheervnano"
-			pass="licheervnano"
-			if [ -e /boot/wifi.ssid ]
-			then
-				echo -n "ssid: "
-				cat /boot/wifi.ssid
-				ssid=`cat /boot/wifi.ssid`
-			fi
-			if [ -e /boot/wifi.pass ]
-			then
-				echo -n "wifi.pass: "
-				cat /boot/wifi.pass
-				pass=`cat /boot/wifi.pass`
-			fi
-			echo "ctrl_interface=/var/run/wpa_supplicant" > /etc/wpa_supplicant.conf
-			wpa_passphrase "$ssid" "$pass" >> /etc/wpa_supplicant.conf
-		fi
-		wpa_supplicant -B -i wlan0 -c /etc/wpa_supplicant.conf
-		if [ -e /boot/wifi.dhcp ]
-		then
-			(udhcpc -i wlan0 -t 10 -T 1 -A 5 -b -p /run/udhcpc.wlan0.pid) &
-		fi
-	elif [ -e /boot/wifi.ap ]
-	then
-		if [ -e /boot/hostapd.conf ]
-		then
-			cp /boot/hostapd.conf /etc/hostapd.conf
-		else
-			echo "wifi mode: ap"
-			id2=$(printf "%d" 0x$(sha512sum /sys/class/cvi-base/base_uid | head -c 2))
-			id3=$(printf "%d" 0x$(sha512sum /sys/class/cvi-base/base_uid | head -c 4 | tail -c 2))
-			if [ "$id2" = "$id3" ]
-			then
-				id2=$((id2 + 1))
-			fi
-			if [ "$id2" -ge 255 ]
-			then
-				id2=253
-			fi
-			if [ "$id3" -ge 255 ]
-			then
-				id3=254
-			fi
-			ssid="licheervnano-${id2}${id3}"
-                        pass="licheervnano"
-                        if [ -e /boot/wifi.ssid ]
-                        then
-                                echo -n "ssid: "
-                                cat /boot/wifi.ssid
-                                ssid=`cat /boot/wifi.ssid`
-                        fi
-                        if [ -e /boot/wifi.pass ]
-                        then
-                                echo -n "wifi.pass: "
-                                cat /boot/wifi.pass
-                                pass=`cat /boot/wifi.pass`
-                        fi
-			gen_hostapd_conf "$ssid" "$pass" > /etc/hostapd.conf
-			if [ -e /boot/wifi.ipv4_prefix ]
-			then
-				ipv4_prefix=`cat /boot/rndis.ipv4_prefix`
-			else
-				ipv4_prefix=10.$id3.$id2
-			fi
-			gen_udhcpd_conf wlan0 "${ipv4_prefix}"  > /etc/udhcpd.wlan0.conf
-			ifconfig wlan0 up
-			ip addr add $ipv4_prefix.1/24 dev wlan0
-		fi
-		hostapd -B -i wlan0 /etc/hostapd.conf
-		udhcpd -S /etc/udhcpd.wlan0.conf
-	elif [ -e /boot/wifi.mon ]
-	then
-		echo "wifi mode: mon"
-		airmon-ng start wlan0
-	fi
-}
-
-stop() {
-	killall wpa_supplicant
-	kill `cat /run/udhcpc.wlan0.pid`
-	rm /run/udhcpc.wlan0.pid
-	kill `cat /var/run/udhcpd.wlan0.pid`
-	rm /var/run/udhcpd.wlan0.pid
-	airmon-ng stop wlan0mon
-}
-
-restart() {
-	start
-	stop
-}
-
-if [ "${1}" = "start" ]
-then
-	start
-elif [ "${1}" = "stop" ]
-then
-	stop
-elif [ "${1}" = "restart" ]
-then
-	restart
-fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S99audtest

@@ -1,42 +0,0 @@
-#!/bin/sh
-
-case "$1" in
-  start)
-    printf "Starting audtest: "
-    if [ -e /boot/audtest ]
-    then
-	    touch /tmp/audtest
-    fi
-    (
-    if [ -e /tmp/audtest ]
-    then
-	    sleep 20
-    fi
-    while true
-    do
-	    if [ ! -e /tmp/audtest ]
-	    then
-		break
-	    fi
-	    . /etc/profile
-	    export HOME=/root
-	    rm /tmp/rec.wav
-	    arecord -f S16_LE -d 1 /tmp/rec.wav
-	    aplay -f S16_LE -Dhw:1,0 /tmp/rec.wav
-	    sleep 0.5
-    done
-    ) &
-    [ $? = 0 ] && echo "OK" || echo "FAIL"
-  ;;
-  stop)
-    printf "Stopping audtest: "
-    rm /tmp/audtest
-    echo "OK"
-  ;;
-  restart)
-    printf "Restart audtest: "
-    $(realpath ${0}) stop
-    $(realpath ${0}) start
-    echo "OK"
-  ;;
-esac

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S99camtest

@@ -1,31 +0,0 @@
-#!/bin/sh
-
-case "$1" in
-  start)
-    printf "Starting camtest: "
-    if [ -e /boot/camtest ]
-    then
-	    touch /tmp/camtest
-    fi
-    if [ ! -e /tmp/camtest ]
-    then
-	exit 0
-else
-	sleep 1
-    fi
-    (nice -n 17 /mnt/system/usr/bin/sample_vio 6 &> /dev/null) &
-    [ $? = 0 ] && echo "OK" || echo "FAIL"
-  ;;
-  stop)
-    printf "Stopping camtest: "
-    rm /tmp/camtest
-    killall sample_vio
-    echo "OK"
-  ;;
-  restart)
-    printf "Restart camtest: "
-    $(realpath ${0}) stop
-    $(realpath ${0}) start
-    echo "OK"
-  ;;
-esac

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S99ivetest

@@ -1,38 +0,0 @@
-#!/bin/sh
-
-case "$1" in
-  start)
-    printf "Starting ivetest: "
-    if [ -e /boot/ivetest ]
-    then
-	    touch /tmp/ivetest
-    fi
-    . /etc/profile
-    (
-    while true
-    do
-	    if [ ! -e /tmp/ivetest ]
-	    then
-		break
-	    fi
-	    if [ ! -e /tmp/rand2MiB ]
-	    then
-	    	dd if=/dev/urandom of=/tmp/rand2MiB bs=1M count=2
-	    fi
-	    /mnt/system/usr/bin/ive_stress 1920 1080 /tmp/rand2MiB 1000
-    done
-    ) &
-    [ $? = 0 ] && echo "OK" || echo "FAIL"
-  ;;
-  stop)
-    printf "Stopping ivetest: "
-    rm /tmp/ivetest
-    echo "OK"
-  ;;
-  restart)
-    printf "Restart ivetest: "
-    $(realpath ${0}) stop
-    $(realpath ${0}) start
-    echo "OK"
-  ;;
-esac

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S99lcdtest

@@ -1,39 +0,0 @@
-#!/bin/sh
-
-case "$1" in
-  start)
-    printf "Starting lcdtest: "
-    if [ -e /boot/lcdtest ]
-    then
-	    touch /tmp/lcdtest
-    fi
-    if [ -e /tmp/lcdtest ]
-    then
-	    sleep 2
-        fbpattern
-    fi
-    (
-    while true
-    do
-	    if [ ! -e /tmp/lcdtest ]
-	    then
-		break
-	    fi
-	date | fbbar 0 0xFFFFFFFF 0xFF000000
-	sleep 1
-    done
-    ) &
-    [ $? = 0 ] && echo "OK" || echo "FAIL"
-  ;;
-  stop)
-    printf "Stopping lcdtest: "
-    rm /tmp/lcdtest
-    echo "OK"
-  ;;
-  restart)
-    printf "Restart lcdtest: "
-    $(realpath ${0}) stop
-    $(realpath ${0}) start
-    echo "OK"
-  ;;
-esac

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S99loadtest

@@ -1,36 +0,0 @@
-#!/bin/sh
-
-case "$1" in
-  start)
-    printf "Starting loadtest: "
-    if [ -e /boot/loadtest ]
-    then
-	    touch /tmp/loadtest
-    fi
-    (
-    while true
-    do
-	    if [ ! -e /tmp/loadtest ]
-	    then
-		break
-	    fi
-	    colorbg=0xFF000000
-	    colorfg=0xFFFFFFFF
-	    echo "tpu_clk: $(cat /sys/kernel/debug/clk/clk_tpu/clk_rate)" | fbbar 16 $colorfg $colorbg
-            sleep 1
-    done
-    ) &
-    [ $? = 0 ] && echo "OK" || echo "FAIL"
-  ;;
-  stop)
-    printf "Stopping loadtest: "
-    rm /tmp/loadtest
-    echo "OK"
-  ;;
-  restart)
-    printf "Restart loadtest: "
-    $(realpath ${0}) stop
-    $(realpath ${0}) start
-    echo "OK"
-  ;;
-esac

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S99local

@@ -1,9 +0,0 @@
-#!/bin/sh
-
-if [ "${1}" = "start" ]
-then
-	if [ ! -e /boot/rclocal.disable ]
-	then
-		sh /etc/rc.local &
-	fi
-fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S99nettest

@@ -1,109 +0,0 @@
-#!/bin/sh
-
-GREEN=0xFF00FF00
-RED=0xFFFF0000
-
-WLAN0_TIMEOUT=15
-ETH0_TIMEOUT=8
-
-case "$1" in
-  start)
-    printf "Starting nettest: "
-    if [ -e /boot/nettest ]
-    then
-	    touch /tmp/nettest
-    fi
-    if [ -e /boot/nettest_url ]
-    then
-	    url=$(cat /boot/nettest_url)
-    fi
-    if [ -z "${url}" ]
-    then
-	    url=http://192.168.0.104:8000/rand10MiB
-    fi
-    (
-    while true
-    do
-	    if [ ! -e /tmp/nettest ]
-	    then
-		break
-	    fi
-	    colorbg=0xFF000000
-	    colorfg=0xFFFFFFFF
-	    wlan0_stat=$(ip link show wlan0 | head -n 1)
-	    wlan0_addr=$(ip link show wlan0 | tail -n 1)
-	    if [ -z "${wlan0_stat}" ]
-	    then
-		    wlan0_stat="wlan0 not found"
-		    colorfg=$RED
-	    fi
-	    echo "$wlan0_stat" | fbbar 64 $colorfg $colorbg
-	    echo "$wlan0_addr" | fbbar 80 $colorfg $colorbg
-	    colorfg=0xFFFFFFFF
-	    eth0_stat=$(ip link show eth0 | head -n 1)
-	    eth0_addr=$(ip link show eth0 | tail -n 1)
-	    if [ -z "${eth0_stat}" ]
-	    then
-		    eth0_stat="eth0 not found"
-		    colorfg=$RED
-	    fi
-	    echo "$eth0_stat" | fbbar 96 $colorfg $colorbg
-	    echo "$eth0_addr" | fbbar 112 $colorfg $colorbg
-	    wlan0_dl_start=$(cat /proc/uptime | awk -F. '{print $1}')
-	    curl --interface wlan0 --max-time ${WLAN0_TIMEOUT} ${url} > /dev/null
-	    if [ $? -ne 0 ]
-	    then
-		    wlan0_dl_time=-1
-		    udhcpc -i wlan0 -t 1 -T 1 -A 1 -v -n
-	    else
-		    wlan0_dl_end=$(cat /proc/uptime | awk -F. '{print $1}')
-		    wlan0_dl_time=$((wlan0_dl_end - wlan0_dl_start))
-	    fi
-	    if [ "${wlan0_dl_time}" -ge $((WLAN0_TIMEOUT - 3)) ]
-	    then
-		    colorfg=$RED
-	    elif [ "${wlan0_dl_time}" = -1 ]
-	    then
-		    colorfg=$RED
-	    else
-		    colorfg=$GREEN
-	    fi
-	    echo "wlan0 download test: ${wlan0_dl_time}" | fbbar 128 $colorfg $colorbg
-	    eth0_dl_start=$(cat /proc/uptime | awk -F. '{print $1}')
-	    curl --interface eth0 --max-time ${ETH0_TIMEOUT} ${url} > /dev/null
-	    if [ $? -ne 0 ]
-	    then
-		    eth0_dl_time=-1
-		    udhcpc -i eth0 -t 1 -T 1 -A 1 -v -n
-            else
-		    eth0_dl_end=$(cat /proc/uptime | awk -F. '{print $1}')
-		    eth0_dl_time=$((eth0_dl_end - eth0_dl_start))
-	    fi
-	    if [ "${eth0_dl_time}" -ge $((ETH0_TIMEOUT - 3)) ]
-	    then
-		    colorfg=$RED
-	    elif [ "${eth0_dl_time}" = -1 ]
-	    then
-		    colorfg=$RED
-	    else
-		    colorfg=$GREEN
-	    fi
-	    echo "eth0 download test: ${eth0_dl_time}" | fbbar 144 $colorfg $colorbg
-            sleep 0.5
-    done
-    ) &
-    [ $? = 0 ] && echo "OK" || echo "FAIL"
-  ;;
-  stop)
-    printf "Stopping nettest: "
-    rm /tmp/nettest
-    echo "OK"
-    sleep 1
-  ;;
-  restart)
-    printf "Restart nettest: "
-    $(realpath ${0}) stop
-    $(realpath ${0}) start
-    echo "OK"
-  ;;
-esac

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S99nntest

@@ -1,35 +0,0 @@
-#!/bin/sh
-
-case "$1" in
-  start)
-    printf "Starting nntest: "
-    if [ -e /boot/nntest ]
-    then
-	    touch /tmp/nntest
-    fi
-    (
-    while true
-    do
-	    if [ ! -e /tmp/nntest ]
-	    then
-		break
-	    fi
-	    cd /usr/bin/
-	nice -n 19 nn_runner_test 1000
-    done
-    ) &
-    [ $? = 0 ] && echo "OK" || echo "FAIL"
-  ;;
-  stop)
-    printf "Stopping nntest: "
-    rm /tmp/nntest
-    killall nn_runner_test
-    echo "OK"
-  ;;
-  restart)
-    printf "Restart nntest: "
-    $(realpath ${0}) stop
-    $(realpath ${0}) start
-    echo "OK"
-  ;;
-esac

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S99resizefs

@@ -1,14 +0,0 @@
-#!/bin/sh
-
-. /etc/profile
-
-if [ "${1}" = start ]
-then
-	# use all sdcard free space for data
-	parted -s /dev/mmcblk0 "resizepart 2 -0"
-	echo "yes
-	100%
-	" | parted ---pretend-input-tty /dev/mmcblk0 "resizepart 2 100%"
-	# resize data filesystem
-	(resize2fs /dev/mmcblk0p2 &> /dev/console) &
-fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S99temptest

@@ -1,47 +0,0 @@
-#!/bin/sh
-
-GREEN=0xFF00FF00
-RED=0xFFFF0000
-
-case "$1" in
-  start)
-    printf "Starting temptest: "
-    if [ -e /boot/temptest ]
-    then
-	    touch /tmp/temptest
-    fi
-    (
-    while true
-    do
-	    if [ ! -e /tmp/temptest ]
-	    then
-		break
-	    fi
-	    colorbg=0xFF000000
-	    soc_temp=$(cat /sys/class/thermal/thermal_zone0/temp)
-	    if [ "${soc_temp}" -le 75000 ]
-	    then
-		    colorfg=$GREEN
-	    else
-		    colorfg=$RED
-	    fi
-	    echo "soc temp: $soc_temp" | fbbar 32 $colorfg $colorbg
-	    colorfg=0xFFFFFFFF
-            echo "soc id: $(cat /sys/class/cvi-base/base_uid)" | fbbar 48 $colorfg $colorbg
-            sleep 1
-    done
-    ) &
-    [ $? = 0 ] && echo "OK" || echo "FAIL"
-  ;;
-  stop)
-    printf "Stopping temptest: "
-    rm /tmp/temptest
-    echo "OK"
-  ;;
-  restart)
-    printf "Restart temptest: "
-    $(realpath ${0}) stop
-    $(realpath ${0}) start
-    echo "OK"
-  ;;
-esac

buildroot/board/cvitek/SG200X/overlay/etc/rc.local

@@ -2,7 +2,7 @@
 
 echo "HELLO WORLD"
 
-if [ -e /boot/maxicam ]
+if [ -e /boot/maixcam ]
 then
 	/maixapp/apps/launcher/launcher &
 fi

buildroot/board/cvitek/SG200X/overlay/etc/ssh/sshd_config

@@ -15,9 +15,10 @@
 #ListenAddress 0.0.0.0
 #ListenAddress ::
 
-#HostKey /etc/ssh/ssh_host_rsa_key
-#HostKey /etc/ssh/ssh_host_ecdsa_key
-#HostKey /etc/ssh/ssh_host_ed25519_key
+# some old ssh utils need rsa & ecdsa
+HostKey /etc/ssh/ssh_host_rsa_key
+HostKey /etc/ssh/ssh_host_ecdsa_key
+HostKey /etc/ssh/ssh_host_ed25519_key
 
 # Ciphers and keying
 #RekeyLimit default none

buildroot/board/cvitek/SG200X/overlay/mnt/data/sensor_cfg.ini.alpha

@@ -0,0 +1,34 @@
+[source]
+
+;type = SOURCE_USER_FE
+
+dev_num = 1
+
+; section for sensor
+
+[sensor]
+
+; sensor name
+name = GCORE_GC4653_MIPI_4M_30FPS_10BIT 
+
+bus_id = 4
+
+sns_i2c_addr = 29
+
+mipi_dev = 0
+
+lane_id = 2, 1, 0, -1, -1
+
+pn_swap = 0, 0, 0, 0, 0
+
+mclk_en = 1
+
+mclk = 0
+
+;port = 0
+
+;pin = 2
+
+;pol = 1
+
+;fps = 30

buildroot/board/cvitek/SG200X/overlay/mnt/data/sensor_cfg.ini.beta

@@ -0,0 +1,34 @@
+[source]
+
+;type = SOURCE_USER_FE
+
+dev_num = 1
+
+; section for sensor
+
+[sensor]
+
+; sensor name
+name = GCORE_GC4653_MIPI_4M_30FPS_10BIT
+
+bus_id = 4
+
+sns_i2c_addr = 29
+
+mipi_dev = 0
+
+lane_id = 4, 3, 2, -1, -1
+
+pn_swap = 0, 0, 0, 0, 0
+
+mclk_en = 1
+
+mclk = 1
+
+;port = 0
+
+;pin = 2
+
+;pol = 1
+
+;fps = 30

buildroot/board/cvitek/SG200X/overlay/usr/share/udhcpc/default.script

@@ -4,7 +4,13 @@
 
 [ -z "$1" ] && echo "Error: should be called from udhcpc" && exit 1
 
+ACTION="$1"
+
 RESOLV_CONF="/etc/resolv.conf"
+if [ -e /boot/resolv.conf ]
+then
+	RESOLV_CONF="/etc/resolv.conf.dhcp"
+fi
 [ -e $RESOLV_CONF ] || touch $RESOLV_CONF
 [ -n "$broadcast" ] && BROADCAST="broadcast $broadcast"
 [ -n "$subnet" ] && NETMASK="netmask $subnet"
@@ -18,7 +24,7 @@ fi
 wait_for_ipv6_default_route() {
 	printf "Waiting for IPv6 default route to appear"
 	while [ $IF_WAIT_DELAY -gt 0 ]; do
-		if [ -z "$(ip -6 route list | grep default)" ]; then
+		if ip -6 route list | grep -q default; then
 			printf "\n"
 			return
 		fi
@@ -29,7 +35,7 @@ wait_for_ipv6_default_route() {
 	printf " timeout!\n"
 }
 
-case "$1" in
+case "$ACTION" in
 	deconfig)
 		/sbin/ifconfig $interface up
 		/sbin/ifconfig $interface 0.0.0.0
@@ -115,7 +121,7 @@ esac
 HOOK_DIR="$0.d"
 for hook in "${HOOK_DIR}/"*; do
     [ -f "${hook}" -a -x "${hook}" ] || continue
-    "${hook}" "${@}"
+    "${hook}" "$ACTION"
 done
 
 exit 0

buildroot/configs/cvitek_SG200X_32bit_defconfig

@@ -0,0 +1,409 @@
+BR2_arm=y
+BR2_cortex_a53=y
+BR2_ARM_EABIHF=y
+BR2_ARM_FPU_FP_ARMV8=y
+
+BR2_TOOLCHAIN_EXTERNAL=y
+BR2_TOOLCHAIN_EXTERNAL_ARM_ARM=y
+BR2_TOOLCHAIN_EXTERNAL_DOWNLOAD=y
+BR2_TOOLCHAIN_EXTERNAL_GDB_SERVER_COPY=y
+BR2_OPTIMIZE_2=y
+
+BR2_CCACHE=y
+BR2_REPRODUCIBLE=y
+BR2_PER_PACKAGE_DIRECTORIES=y
+
+BR2_TARGET_GENERIC_HOSTNAME="licheea53nano"
+BR2_TARGET_GENERIC_ISSUE="Welcome to Linux"
+BR2_TARGET_GENERIC_ROOT_PASSWD="root"
+
+BR2_PACKAGE_AIC8800_SDIO_FIRMWARE=y
+
+BR2_INIT_SYSV=y
+BR2_ROOTFS_MERGED_USR=y
+BR2_ENABLE_LOCALE_WHITELIST="C en_US en_US.utf8"
+BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_EUDEV=y
+BR2_PACKAGE_BUSYBOX_SHOW_OTHERS=y
+BR2_PACKAGE_KMOD=y
+# dont rename network card,
+# BR2_PACKAGE_EUDEV_RULES_GEN is not set
+BR2_PACKAGE_EUDEV_ENABLE_HWDB=y
+BR2_PACKAGE_BLUEZ5_UTILS=y
+BR2_PACKAGE_BLUEZ5_UTILS_CLIENT=y
+BR2_PACKAGE_BLUEZ5_UTILS_TOOLS=y
+BR2_PACKAGE_BLUEZ5_UTILS_DEPRECATED=y
+BR2_PACKAGE_BLUEZ5_UTILS_PLUGINS_HID=y
+BR2_PACKAGE_BLUEZ5_UTILS_PLUGINS_NETWORK=y
+BR2_PACKAGE_BLUEZ5_UTILS_TOOLS_HID2HCI=y
+BR2_PACKAGE_BLUEZ5_UTILS_MONITOR=y
+BR2_PACKAGE_BLUEZ_ALSA=y
+BR2_PACKAGE_BLUEZ_ALSA_RFCOMM=y
+BR2_PACKAGE_BLUEZ_ALSA_HCITOP=y
+BR2_PACKAGE_NTP=y
+BR2_PACKAGE_NTP_NTPD=y
+BR2_PACKAGE_NTP_NTPDATE=y
+BR2_PACKAGE_MACCHANGER=y
+BR2_PACKAGE_AVAHI=y
+BR2_PACKAGE_AVAHI_AUTOIPD=y
+# avahi mdns is buggy
+# BR2_PACKAGE_AVAHI_DAEMON is not set
+# BR2_PACKAGE_AVAHI_LIBDNSSD_COMPATIBILITY is not set
+# BR2_PACKAGE_AVAHI_DEFAULT_SERVICES is not set
+BR2_PACKAGE_MDNSD=y
+BR2_PACKAGE_MDNSD_MQUERY=y
+BR2_PACKAGE_MDNSD_HTTP_SERVICE=y
+BR2_PACKAGE_MDNSD_SSH_SERVICE=y
+BR2_PACKAGE_WIRELESS_TOOLS=y
+BR2_PACKAGE_WIRELESS_TOOLS_IFRENAME=y
+BR2_PACKAGE_WIRELESS_TOOLS_IWCONFIG=y
+BR2_PACKAGE_WIRELESS_TOOLS_LIB=y
+BR2_PACKAGE_AIRCRACK_NG=y
+BR2_PACKAGE_UTIL_LINUX_RFKILL=y
+BR2_PACKAGE_IPERF3=y
+BR2_PACKAGE_IPMITOOL=y
+BR2_PACKAGE_IPMITOOL_PEN_REG_URI=y
+BR2_PACKAGE_IPMITOOL_LANPLUS=y
+BR2_PACKAGE_IPMITOOL_USB=y
+BR2_PACKAGE_IPMITOOL_IPMIEVD=y
+BR2_PACKAGE_IPMITOOL_IPMISHELL=y
+BR2_PACKAGE_ETHTOOL=y
+BR2_PACKAGE_DNSMASQ=y
+BR2_PACKAGE_DNSMASQ_DHCP=y
+BR2_PACKAGE_RSYNC=y
+BR2_PACKAGE_SOCAT=y
+BR2_PACKAGE_TINC=y
+BR2_PACKAGE_WIRELESS_REGDB=y
+BR2_PACKAGE_MOSH=y
+BR2_PACKAGE_LRZSZ=y
+BR2_PACKAGE_IW=y
+# BR2_PACKAGE_WIREGUARD=y
+BR2_PACKAGE_WIREGUARD_TOOLS=y
+# BR2_PACKAGE_WIREGUARD_LINUX_COMPAT=y
+BR2_PACKAGE_WPA_SUPPLICANT=y
+BR2_PACKAGE_WPA_SUPPLICANT_NL80211=y
+BR2_PACKAGE_WPA_SUPPLICANT_WPA3=y
+BR2_PACKAGE_WPA_SUPPLICANT_AUTOSCAN=y
+BR2_PACKAGE_WPA_SUPPLICANT_AP_SUPPORT=y
+BR2_PACKAGE_WPA_SUPPLICANT_OVERRIDES=y
+BR2_PACKAGE_WPA_SUPPLICANT_WIFI_DISPLAY=y
+BR2_PACKAGE_WPA_SUPPLICANT_MESH_NETWORKING=y
+BR2_PACKAGE_WPA_SUPPLICANT_IBSS_RSN=y
+BR2_PACKAGE_WPA_SUPPLICANT_WEXT=y
+BR2_PACKAGE_WPA_SUPPLICANT_EAP=y
+BR2_PACKAGE_WPA_SUPPLICANT_HOTSPOT=y
+BR2_PACKAGE_WPA_SUPPLICANT_DEBUG_SYSLOG=y
+BR2_PACKAGE_WPA_SUPPLICANT_WPS=y
+BR2_PACKAGE_WPA_SUPPLICANT_CLI=y
+BR2_PACKAGE_WPA_SUPPLICANT_WPA_CLIENT_SO=y
+BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y
+BR2_PACKAGE_WPA_SUPPLICANT_CTRL_IFACE=y
+BR2_PACKAGE_WPA_SUPPLICANT_DBUS=y
+BR2_PACKAGE_HOSTAPD=y
+BR2_PACKAGE_HOSTAPD_DRIVER_HOSTAP=y
+BR2_PACKAGE_HOSTAPD_DRIVER_NL80211=y
+BR2_PACKAGE_HOSTAPD_ACS=y
+BR2_PACKAGE_HOSTAPD_EAP=y
+BR2_PACKAGE_HOSTAPD_WPS=y
+BR2_PACKAGE_HOSTAPD_WPA3=y
+# BR2_PACKAGE_HOSTAPD_VLAN is not set
+BR2_PACKAGE_OPENSSH=y
+BR2_PACKAGE_OPENSSH_CLIENT=y
+BR2_PACKAGE_OPENSSH_SERVER=y
+BR2_PACKAGE_OPENSSH_KEY_UTILS=y
+BR2_PACKAGE_HAVEGED=y
+BR2_PACKAGE_LIBOPENSSL_BIN=y
+BR2_PACKAGE_LIBOPENSSL_ENGINES=y
+BR2_PACKAGE_PARTED=y
+BR2_PACKAGE_MEMTESTER=y
+BR2_PACKAGE_CACHE_CALIBRATOR=y
+BR2_PACKAGE_DHRYSTONE=y
+BR2_PACKAGE_RAMSPEED=y
+BR2_PACKAGE_SPIDEV_TEST=y
+BR2_PACKAGE_STRESS_NG=y
+BR2_PACKAGE_STRACE=y
+BR2_PACKAGE_VMTOUCH=y
+BR2_PACKAGE_ALSA_UTILS=y
+BR2_PACKAGE_ALSA_UTILS_ALSACTL=y
+BR2_PACKAGE_ALSA_UTILS_ALSAMIXER=y
+BR2_PACKAGE_ALSA_UTILS_APLAY=y
+BR2_PACKAGE_MPG123=y
+BR2_PACKAGE_BZIP2=y
+BR2_PACKAGE_LRZIP=y
+BR2_PACKAGE_LZIP=y
+BR2_PACKAGE_P7ZIP=y
+BR2_PACKAGE_PIGZ=y
+BR2_PACKAGE_PIXZ=y
+BR2_PACKAGE_UNRAR=y
+BR2_PACKAGE_UNZIP=y
+BR2_PACKAGE_ZIP=y
+BR2_PACKAGE_ZSTD=y
+BR2_PACKAGE_LZOP=y
+BR2_PACKAGE_BROTLI=y
+BR2_PACKAGE_LIBZIP=y
+BR2_PACKAGE_LZ4_PROGS=y
+BR2_PACKAGE_SZIP=y
+BR2_PACKAGE_CA_CERTIFICATES=y
+BR2_PACKAGE_EVTEST=y
+BR2_PACKAGE_FILE=y
+BR2_PACKAGE_EMPTY=y
+BR2_PACKAGE_EXFATPROGS=y
+BR2_PACKAGE_E2FSPROGS=y
+BR2_PACKAGE_E2FSPROGS_RESIZE2FS=y
+BR2_PACKAGE_TMUX=y
+BR2_PACKAGE_HTOP=y
+BR2_PACKAGE_LIBCURL=y
+BR2_PACKAGE_LIBCURL_CURL=y
+BR2_PACKAGE_LIBCURL_VERBOSE=y
+BR2_PACKAGE_LIBCURL_PROXY_SUPPORT=y
+BR2_PACKAGE_LIBCURL_COOKIES_SUPPORT=y
+BR2_PACKAGE_LIBCURL_WEBSOCKETS_SUPPORT=y
+BR2_PACKAGE_LIBCURL_EXTRA_PROTOCOLS_FEATURES=y
+BR2_PACKAGE_LIBCURL_OPENSSL=y
+BR2_PACKAGE_LIBWEBSOCKETS=y
+BR2_PACKAGE_WATCHDOG=y
+BR2_PACKAGE_SQUASHFS=y
+BR2_PACKAGE_SQUASHFS_GZIP=y
+BR2_PACKAGE_SQUASHFS_LZ4=y
+BR2_PACKAGE_SQUASHFS_LZMA=y
+BR2_PACKAGE_SQUASHFS_LZO=y
+BR2_PACKAGE_SQUASHFS_XZ=y
+BR2_PACKAGE_SQUASHFS_ZSTD=y
+BR2_PACKAGE_LCDTEST=y
+BR2_PACKAGE_ASCII_INVADERS=y
+BR2_PACKAGE_GNUCHESS=y
+BR2_PACKAGE_SL=y
+BR2_PACKAGE_XORCURSES=y
+BR2_PACKAGE_INPUT_EVENT_DAEMON=y
+BR2_PACKAGE_BLUEZ_TOOLS=y
+BR2_PACKAGE_TPUDEMO_SG200X=y
+BR2_PACKAGE_SG2002_CODEC_FIRMWARE=y
+BR2_PACKAGE_TCPDUMP=y
+BR2_PACKAGE_SSDP_RESPONDER=y
+BR2_PACKAGE_PPPD=y
+BR2_PACKAGE_NFTABLES=y
+BR2_PACKAGE_BIND=y
+BR2_PACKAGE_SYSSTAT=y
+BR2_PACKAGE_TRACEROUTE=y
+BR2_PACKAGE_IPUTILS=y
+BR2_PACKAGE_IPROUTE2=y
+BR2_PACKAGE_IPTABLES=y
+BR2_PACKAGE_IPTABLES_NFTABLES=y
+BR2_PACKAGE_NCURSES_WCHAR=y
+BR2_PACKAGE_LIBEDIT=y
+# BR2_PACKAGE_NGINX=y
+# BR2_PACKAGE_NGINX_HTTP=y
+# BR2_PACKAGE_NGINX_HTTP_DAV_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_MP4_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_FLV_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_GUNZIP_MODULE=y
+# BR2_PACKAGE_NGINX_STREAM=y
+# BR2_PACKAGE_NGINX_SELECT_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_FASTCGI_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_UWSGI_MODULE=y
+# BR2_PACKAGE_NGINX_HTTP_SCGI_MODULE=y
+BR2_PACKAGE_RTC_TOOLS=y
+BR2_PACKAGE_PICOCOM=y
+BR2_PACKAGE_FBGRAB=y
+BR2_PACKAGE_MHZ=y
+BR2_PACKAGE_SETSERIAL=y
+BR2_PACKAGE_UBOOT_TOOLS=y
+BR2_PACKAGE_UBOOT_TOOLS_FIT_SUPPORT=y
+BR2_PACKAGE_UBOOT_TOOLS_MKIMAGE=y
+BR2_PACKAGE_UBOOT_TOOLS_DUMPIMAGE=y
+
+# if your sdnand is small, you can delete some package
+
+BR2_PACKAGE_IMAGEMAGICK=y
+BR2_PACKAGE_OCRAD=y
+BR2_PACKAGE_SDL=y
+BR2_PACKAGE_SDL_FBCON=y
+BR2_PACKAGE_SDL_GFX=y
+BR2_PACKAGE_SDL_IMAGE=y
+BR2_PACKAGE_SDL_IMAGE_BMP=y
+BR2_PACKAGE_SDL_IMAGE_GIF=y
+BR2_PACKAGE_SDL_IMAGE_JPEG=y
+BR2_PACKAGE_SDL_IMAGE_PNG=y
+BR2_PACKAGE_SDL_IMAGE_WEBP=y
+BR2_PACKAGE_SDL_MIXER=y
+BR2_PACKAGE_SDL_NET=y
+BR2_PACKAGE_SDL_SOUND=y
+BR2_PACKAGE_SDL_SOUND_PLAYSOUND=y
+BR2_PACKAGE_LBREAKOUT2=y
+BR2_PACKAGE_LBREAKOUT2_AUDIO=y
+BR2_PACKAGE_LBREAKOUT2_NET=y
+BR2_PACKAGE_LTRIS=y
+BR2_PACKAGE_LTRIS_AUDIO=y
+BR2_PACKAGE_PRBOOM=y
+BR2_PACKAGE_DOOM_WAD=y
+BR2_PACKAGE_TCL=y
+# BR2_PACKAGE_TCL_SHLIB_ONLY is not set
+# BR2_PACKAGE_TCL_DEL_ENCODINGS is not set
+BR2_PACKAGE_EXPECT=y
+BR2_PACKAGE_TCLLIB=y
+BR2_PACKAGE_OPENCV4=y
+BR2_PACKAGE_OPENCV4_LIB_CALIB3D=y
+BR2_PACKAGE_OPENCV4_LIB_DNN=y
+BR2_PACKAGE_OPENCV4_LIB_HIGHGUI=y
+BR2_PACKAGE_OPENCV4_LIB_OBJDETECT=y
+BR2_PACKAGE_OPENCV4_LIB_PHOTO=y
+BR2_PACKAGE_OPENCV4_LIB_SHAPE=y
+BR2_PACKAGE_OPENCV4_LIB_STITCHING=y
+BR2_PACKAGE_OPENCV4_LIB_SUPERRES=y
+BR2_PACKAGE_OPENCV4_LIB_TS=y
+BR2_PACKAGE_OPENCV4_LIB_VIDEOSTAB=y
+BR2_PACKAGE_OPENCV4_BUILD_TESTS=y
+BR2_PACKAGE_OPENCV4_BUILD_PERF_TESTS=y
+BR2_PACKAGE_OPENCV4_WITH_FFMPEG=y
+BR2_PACKAGE_OPENCV4_WITH_JPEG=y
+BR2_PACKAGE_OPENCV4_WITH_PNG=y
+BR2_PACKAGE_OPENCV4_WITH_TBB=y
+BR2_PACKAGE_OPENCV4_WITH_TIFF=y
+BR2_PACKAGE_OPENCV4_WITH_V4L=y
+BR2_PACKAGE_OPENCV4_WITH_WEBP=y
+BR2_PACKAGE_OPENCV4_INSTALL_DATA=y
+BR2_PACKAGE_LIBQRENCODE=y
+BR2_PACKAGE_LIBQRENCODE_TOOLS=y
+BR2_PACKAGE_FFMPEG=y
+BR2_PACKAGE_FFMPEG_FFMPEG=y
+BR2_PACKAGE_FFMPEG_FFPROBE=y
+BR2_PACKAGE_FFMPEG_GPL=y
+BR2_PACKAGE_FFMPEG_NONFREE=y
+BR2_PACKAGE_FFMPEG_POSTPROC=y
+BR2_PACKAGE_MULTICAT=y
+BR2_PACKAGE_WQY_ZENHEI=y
+BR2_PACKAGE_DEJAVU=y
+BR2_PACKAGE_GNUPLOT=y
+BR2_PACKAGE_TESSERACT_OCR=y
+BR2_PACKAGE_TESSERACT_OCR_LANG_ENG=y
+BR2_PACKAGE_TESSERACT_OCR_LANG_CHI_SIM=y
+BR2_PACKAGE_TESSERACT_OCR_LANG_CHI_TRA=y
+BR2_PACKAGE_QT5=y
+BR2_PACKAGE_QT5BASE_SQLITE_SYSTEM=y
+BR2_PACKAGE_QT5BASE_GUI=y
+BR2_PACKAGE_QT5BASE_LINUXFB=y
+BR2_PACKAGE_QT5BASE_WIDGETS=y
+BR2_PACKAGE_QT5BASE_DEFAULT_QPA="linuxfb"
+BR2_PACKAGE_QT5BASE_FONTCONFIG=y
+BR2_PACKAGE_QT5BASE_GIF=y
+BR2_PACKAGE_QT5BASE_PNG=y
+BR2_PACKAGE_QT5BASE_JPEG=y
+BR2_PACKAGE_QT5BASE_SYSLOG=y
+BR2_PACKAGE_QT5BASE_DBUS=y
+BR2_PACKAGE_QT5BASE_TSLIB=y
+BR2_PACKAGE_QT5BASE_EXAMPLES=y
+BR2_PACKAGE_QT5BASE_CONCURRENT=y
+BR2_PACKAGE_QT5CONNECTIVITY=y
+BR2_PACKAGE_QT5IMAGEFORMATS=y
+BR2_PACKAGE_QT5MULTIMEDIA=y
+BR2_PACKAGE_QT5SENSORS=y
+BR2_PACKAGE_QT5SERIALBUS=y
+BR2_PACKAGE_QT5CHARTS=y
+BR2_PACKAGE_QT5COAP=y
+BR2_PACKAGE_QT5ENGINIO=y
+BR2_PACKAGE_QT5KNX=y
+BR2_PACKAGE_QT5LOCATION=y
+BR2_PACKAGE_QT5MQTT=y
+BR2_PACKAGE_QT5OPCUA=y
+BR2_PACKAGE_QT5REMOTEOBJECTS=y
+BR2_PACKAGE_QT5SPEECH=y
+BR2_PACKAGE_QT5SVG=y
+BR2_PACKAGE_QT5WEBSOCKETS=y
+BR2_PACKAGE_QT5WEBCHANNEL=y
+BR2_PACKAGE_QEXTSERIALPORT=y
+BR2_PACKAGE_QT5X11EXTRAS=y
+BR2_PACKAGE_QT5XMLPATTERNS=y
+BR2_PACKAGE_QT5BASE_MYSQL=y
+BR2_PACKAGE_QJSON=y
+BR2_PACKAGE_QUAZIP=y
+BR2_PACKAGE_PYTHON3=y
+BR2_PACKAGE_PYTHON3_2TO3=y
+BR2_PACKAGE_PYTHON3_BZIP2=y
+BR2_PACKAGE_PYTHON3_CODECSCJK=y
+BR2_PACKAGE_PYTHON3_CURSES=y
+BR2_PACKAGE_PYTHON3_SSL=y
+BR2_PACKAGE_PYTHON3_UNICODEDATA=y
+BR2_PACKAGE_PYTHON3_SQLITE=y
+BR2_PACKAGE_PYTHON3_XZ=y
+BR2_PACKAGE_PYTHON3_ZLIB=y
+BR2_PACKAGE_PYTHON_NUMPY=y
+BR2_PACKAGE_OPENCV4_LIB_PYTHON=y
+BR2_PACKAGE_OPENCV4_WITH_QT5=y
+BR2_PACKAGE_PYTHON_BSDIFF4=y
+BR2_PACKAGE_PYTHON_BEAUTIFULSOUP4=y
+BR2_PACKAGE_PYTHON_CFFI=y
+BR2_PACKAGE_PYTHON_CRC16=y
+BR2_PACKAGE_PYTHON_DBUS_FAST=y
+BR2_PACKAGE_PYTHON_DATEUTIL=y
+BR2_PACKAGE_PYTHON_DBUS_NEXT=y
+BR2_PACKAGE_PYTHON_DJANGO=y
+BR2_PACKAGE_PYTHON_FLASK=y
+BR2_PACKAGE_PYTHON_EVDEV=y
+BR2_PACKAGE_PYTHON_FLASK_BABEL=y
+BR2_PACKAGE_PYTHON_FLASK_CORS=y
+BR2_PACKAGE_PYTHON_FLASK_JSONRPC=y
+BR2_PACKAGE_PYTHON_FLASK_LOGIN=y
+BR2_PACKAGE_PYTHON_FLASK_SMOREST=y
+BR2_PACKAGE_PYTHON_FLASK_SQLALCHEMY=y
+BR2_PACKAGE_PYTHON_FLASK_WTF=y
+BR2_PACKAGE_PYTHON_HWDATA=y
+BR2_PACKAGE_PYTHON_PIP=y
+BR2_PACKAGE_PYTHON_PEXPECT=y
+BR2_PACKAGE_PYTHON_PSUTIL=y
+BR2_PACKAGE_PYTHON_PYAES=y
+BR2_PACKAGE_PYTHON_PYALSA=y
+BR2_PACKAGE_PYTHON_PYDEVMEM=y
+BR2_PACKAGE_PYTHON_PYUSB=y
+BR2_PACKAGE_PYTHON_REQUESTS=y
+BR2_PACKAGE_PYTHON_REQUESTS_OAUTHLIB=y
+BR2_PACKAGE_PYTHON_REQUESTS_TOOLBELT=y
+BR2_PACKAGE_PYTHON_SERIAL=y
+BR2_PACKAGE_PYTHON_SERIAL_ASYNCIO=y
+BR2_PACKAGE_PYTHON_WEBSOCKETS=y
+BR2_PACKAGE_PYTHON_WEBSOCKET_CLIENT=y
+BR2_PACKAGE_PYTHON_XMODEM=y
+BR2_PACKAGE_PYTHON3_PY_PYC=y
+BR2_PACKAGE_PYTHON_PYQT5=y
+BR2_PACKAGE_PYTHON_PYQRCODE=y
+BR2_PACKAGE_PYTHON_PYLIBFDT=y
+BR2_PACKAGE_PYTHON3_READLINE=y
+BR2_PACKAGE_PYTHON_JEDI=y
+BR2_PACKAGE_PYTHON_LIBUSB1=y
+BR2_PACKAGE_PYTHON_LXML=y
+BR2_PACKAGE_PYTHON_MARKDOWN=y
+BR2_PACKAGE_PYTHON_MSGPACK=y
+BR2_PACKAGE_PYTHON_PERIPHERY=y
+BR2_PACKAGE_PYTHON_PILLOW=y
+BR2_PACKAGE_PYTHON_POSIX_IPC=y
+BR2_PACKAGE_PYTHON_PROTOBUF=y
+BR2_PACKAGE_PYTHON_PYGAME=y
+BR2_PACKAGE_PYTHON_PYGAME_IMAGE=y
+BR2_PACKAGE_PYTHON_PYGAME_EXAMPLES=y
+BR2_PACKAGE_PYTHON_PYGAME_FONT=y
+BR2_PACKAGE_PYTHON_PYGAME_MIXER=y
+BR2_PACKAGE_PYTHON_PYUDEV=y
+BR2_PACKAGE_PYTHON_PYYAML=y
+BR2_PACKAGE_PYTHON_QRCODE=y
+BR2_PACKAGE_PYTHON_QRCODE_PIL=y
+BR2_PACKAGE_PYTHON_INTELHEX=y
+
+BR2_PACKAGE_VIM=y
+BR2_PACKAGE_VIM_RUNTIME=y
+
+BR2_PACKAGE_AXP2101=y
+
+BR2_TARGET_ROOTFS_EXT2=y
+BR2_TARGET_ROOTFS_EXT2_4=y
+BR2_TARGET_ROOTFS_EXT2_SIZE="1100M"
+
+BR2_ROOTFS_OVERLAY="$(TOPDIR)/board/cvitek/SG200X/overlay"
+BR2_PACKAGE_BUSYBOX_CONFIG_FRAGMENT_FILES="$(TOPDIR)/board/cvitek/SG200X/busybox-extra.config"
+
+BR2_TARGET_TZ_INFO=y
+BR2_TARGET_TZ_ZONELIST="default"
+BR2_TARGET_LOCALTIME="Etc/UTC"
+
+BR2_PACKAGE_SER2NET=y
+
+BR2_PACKAGE_NANO=y
+
+BR2_PACKAGE_OPENIPMI=y

buildroot/configs/cvitek_SG200X_musl_riscv64_defconfig

@@ -1,259 +1,196 @@
 BR2_riscv=y
-BR2_riscv_g=y
 BR2_RISCV_ISA_RVC=y
-BR2_RISCV_ABI_LP64D=y
-
 BR2_TOOLCHAIN_EXTERNAL=y
 BR2_TOOLCHAIN_EXTERNAL_CUSTOM=y
-BR2_TOOLCHAIN_EXTERNAL_PREINSTALLED=y
-# cvitek vendor toolchain
 BR2_TOOLCHAIN_EXTERNAL_CUSTOM_PREFIX="riscv64-unknown-linux-musl"
-BR2_TOOLCHAIN_EXTERNAL_CUSTOM_MUSL=y
 BR2_TOOLCHAIN_EXTERNAL_GCC_10=y
 BR2_TOOLCHAIN_EXTERNAL_HEADERS_5_10=y
-BR2_TOOLCHAIN_EXTERNAL_HAS_SSP=y
-# BR2_TOOLCHAIN_EXTERNAL_INET_RPC is not set
+BR2_TOOLCHAIN_EXTERNAL_CUSTOM_MUSL=y
 BR2_TOOLCHAIN_EXTERNAL_CXX=y
-# BR2_TOOLCHAIN_EXTERNAL_FORTRAN is not set
 BR2_TOOLCHAIN_EXTERNAL_OPENMP=y
-BR2_OPTIMIZE_2=y
-BR2_TARGET_LDFLAGS="-mcpu=c906fdv -march=rv64imafdcv0p7xthead -mcmodel=medany -mabi=lp64d"
-BR2_PACKAGE_GDB=y
-BR2_PACKAGE_GDB_SERVER=y
-BR2_PACKAGE_GDB_DEBUGGER=y
-BR2_PACKAGE_GDB_PYTHON=y
-BR2_PACKAGE_GDB_TUI=y
 BR2_PACKAGE_HOST_GDB=y
+BR2_PACKAGE_HOST_GDB_TUI=y
 BR2_PACKAGE_HOST_GDB_PYTHON3=y
 BR2_PACKAGE_HOST_GDB_SIM=y
-BR2_PACKAGE_HOST_GDB_TUI=y
 BR2_GDB_VERSION_13=y
-
+BR2_TARGET_LDFLAGS="-mcpu=c906fdv -march=rv64imafdcv0p7xthead -mcmodel=medany -mabi=lp64d"
 BR2_CCACHE=y
+BR2_OPTIMIZE_2=y
 BR2_REPRODUCIBLE=y
 BR2_PER_PACKAGE_DIRECTORIES=y
-
 BR2_TARGET_GENERIC_HOSTNAME="licheervnano"
 BR2_TARGET_GENERIC_ISSUE="Welcome to Linux"
-BR2_TARGET_GENERIC_ROOT_PASSWD="root"
-
-BR2_PACKAGE_AIC8800_SDIO_FIRMWARE=y
-
-BR2_PACKAGE_CVITEK_RISCV64_MUSL_SYSROOT=y
-
 BR2_INIT_SYSV=y
-BR2_ROOTFS_MERGED_USR=y
-BR2_ENABLE_LOCALE_WHITELIST="C en_US en_US.utf8"
 BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_EUDEV=y
-BR2_PACKAGE_BUSYBOX_SHOW_OTHERS=y
-BR2_PACKAGE_KMOD=y
-# dont rename network card,
-# BR2_PACKAGE_EUDEV_RULES_GEN is not set
-BR2_PACKAGE_EUDEV_ENABLE_HWDB=y
-BR2_PACKAGE_BLUEZ5_UTILS=y
-BR2_PACKAGE_BLUEZ5_UTILS_CLIENT=y
-BR2_PACKAGE_BLUEZ5_UTILS_TOOLS=y
-BR2_PACKAGE_BLUEZ5_UTILS_DEPRECATED=y
-BR2_PACKAGE_BLUEZ5_UTILS_PLUGINS_HID=y
-BR2_PACKAGE_BLUEZ5_UTILS_PLUGINS_NETWORK=y
-BR2_PACKAGE_BLUEZ5_UTILS_TOOLS_HID2HCI=y
-BR2_PACKAGE_BLUEZ5_UTILS_MONITOR=y
-BR2_PACKAGE_BLUEZ_ALSA=y
-BR2_PACKAGE_BLUEZ_ALSA_RFCOMM=y
-BR2_PACKAGE_BLUEZ_ALSA_HCITOP=y
-BR2_PACKAGE_NTP=y
-BR2_PACKAGE_NTP_NTPD=y
-BR2_PACKAGE_NTP_NTPDATE=y
-BR2_PACKAGE_MACCHANGER=y
-BR2_PACKAGE_AVAHI=y
-BR2_PACKAGE_AVAHI_AUTOIPD=y
-# avahi mdns is buggy
-# BR2_PACKAGE_AVAHI_DAEMON is not set
-# BR2_PACKAGE_AVAHI_LIBDNSSD_COMPATIBILITY is not set
-# BR2_PACKAGE_AVAHI_DEFAULT_SERVICES is not set
-BR2_PACKAGE_MDNSD=y
-BR2_PACKAGE_MDNSD_MQUERY=y
-BR2_PACKAGE_MDNSD_HTTP_SERVICE=y
-BR2_PACKAGE_MDNSD_SSH_SERVICE=y
-BR2_PACKAGE_WIRELESS_TOOLS=y
-BR2_PACKAGE_WIRELESS_TOOLS_IFRENAME=y
-BR2_PACKAGE_WIRELESS_TOOLS_IWCONFIG=y
-BR2_PACKAGE_WIRELESS_TOOLS_LIB=y
-BR2_PACKAGE_AIRCRACK_NG=y
-BR2_PACKAGE_UTIL_LINUX_RFKILL=y
-BR2_PACKAGE_IPERF3=y
-BR2_PACKAGE_ETHTOOL=y
-BR2_PACKAGE_DNSMASQ=y
-BR2_PACKAGE_DNSMASQ_DHCP=y
-BR2_PACKAGE_RSYNC=y
-BR2_PACKAGE_SOCAT=y
-BR2_PACKAGE_TINC=y
-BR2_PACKAGE_WIRELESS_REGDB=y
-BR2_PACKAGE_MOSH=y
-BR2_PACKAGE_LRZSZ=y
-BR2_PACKAGE_IW=y
-BR2_PACKAGE_WIREGUARD_TOOLS=y
-BR2_PACKAGE_WPA_SUPPLICANT=y
-BR2_PACKAGE_WPA_SUPPLICANT_NL80211=y
-BR2_PACKAGE_WPA_SUPPLICANT_WPA3=y
-BR2_PACKAGE_WPA_SUPPLICANT_AUTOSCAN=y
-BR2_PACKAGE_WPA_SUPPLICANT_AP_SUPPORT=y
-BR2_PACKAGE_WPA_SUPPLICANT_OVERRIDES=y
-BR2_PACKAGE_WPA_SUPPLICANT_WIFI_DISPLAY=y
-BR2_PACKAGE_WPA_SUPPLICANT_MESH_NETWORKING=y
-BR2_PACKAGE_WPA_SUPPLICANT_IBSS_RSN=y
-BR2_PACKAGE_WPA_SUPPLICANT_WEXT=y
-BR2_PACKAGE_WPA_SUPPLICANT_EAP=y
-BR2_PACKAGE_WPA_SUPPLICANT_HOTSPOT=y
-BR2_PACKAGE_WPA_SUPPLICANT_DEBUG_SYSLOG=y
-BR2_PACKAGE_WPA_SUPPLICANT_WPS=y
-BR2_PACKAGE_WPA_SUPPLICANT_CLI=y
-BR2_PACKAGE_WPA_SUPPLICANT_WPA_CLIENT_SO=y
-BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y
-BR2_PACKAGE_WPA_SUPPLICANT_CTRL_IFACE=y
-BR2_PACKAGE_WPA_SUPPLICANT_DBUS=y
-BR2_PACKAGE_HOSTAPD=y
-BR2_PACKAGE_HOSTAPD_DRIVER_HOSTAP=y
-BR2_PACKAGE_HOSTAPD_DRIVER_NL80211=y
-BR2_PACKAGE_HOSTAPD_ACS=y
-BR2_PACKAGE_HOSTAPD_EAP=y
-BR2_PACKAGE_HOSTAPD_WPS=y
-BR2_PACKAGE_HOSTAPD_WPA3=y
-# BR2_PACKAGE_HOSTAPD_VLAN is not set
-BR2_PACKAGE_OPENSSH=y
-BR2_PACKAGE_OPENSSH_CLIENT=y
-BR2_PACKAGE_OPENSSH_SERVER=y
-BR2_PACKAGE_OPENSSH_KEY_UTILS=y
-BR2_PACKAGE_HAVEGED=y
-BR2_PACKAGE_LIBOPENSSL_BIN=y
-BR2_PACKAGE_LIBOPENSSL_ENGINES=y
-BR2_PACKAGE_PARTED=y
-BR2_PACKAGE_MEMTESTER=y
-BR2_PACKAGE_CACHE_CALIBRATOR=y
-BR2_PACKAGE_DHRYSTONE=y
-BR2_PACKAGE_RAMSPEED=y
-BR2_PACKAGE_SPIDEV_TEST=y
-BR2_PACKAGE_STRESS_NG=y
-BR2_PACKAGE_STRACE=y
-BR2_PACKAGE_VMTOUCH=y
+BR2_ROOTFS_MERGED_USR=y
+BR2_TARGET_GENERIC_ROOT_PASSWD="root"
+BR2_ENABLE_LOCALE_WHITELIST="C en_US en_US.utf8"
+BR2_TARGET_TZ_INFO=y
+BR2_ROOTFS_OVERLAY="$(TOPDIR)/board/cvitek/SG200X/overlay"
+BR2_PACKAGE_BUSYBOX_CONFIG_FRAGMENT_FILES="$(TOPDIR)/board/cvitek/SG200X/busybox-extra.config"
 BR2_PACKAGE_ALSA_UTILS=y
-BR2_PACKAGE_ALSA_UTILS_ALSACTL=y
-BR2_PACKAGE_ALSA_UTILS_ALSAMIXER=y
+BR2_PACKAGE_ALSA_UTILS_AMIXER=y
 BR2_PACKAGE_ALSA_UTILS_APLAY=y
+BR2_PACKAGE_FFMPEG_GPL=y
+BR2_PACKAGE_FFMPEG_NONFREE=y
+BR2_PACKAGE_FFMPEG_FFPROBE=y
+BR2_PACKAGE_FFMPEG_POSTPROC=y
 BR2_PACKAGE_MPG123=y
-BR2_PACKAGE_BZIP2=y
+BR2_PACKAGE_BROTLI=y
 BR2_PACKAGE_LRZIP=y
 BR2_PACKAGE_LZIP=y
+BR2_PACKAGE_LZOP=y
 BR2_PACKAGE_P7ZIP=y
 BR2_PACKAGE_PIGZ=y
 BR2_PACKAGE_PIXZ=y
 BR2_PACKAGE_UNRAR=y
 BR2_PACKAGE_UNZIP=y
 BR2_PACKAGE_ZIP=y
-BR2_PACKAGE_ZSTD=y
-BR2_PACKAGE_LZOP=y
-BR2_PACKAGE_BROTLI=y
-BR2_PACKAGE_LIBZIP=y
-BR2_PACKAGE_LZ4_PROGS=y
-BR2_PACKAGE_SZIP=y
-BR2_PACKAGE_CA_CERTIFICATES=y
-BR2_PACKAGE_EVTEST=y
-BR2_PACKAGE_FILE=y
-BR2_PACKAGE_EMPTY=y
+BR2_PACKAGE_CACHE_CALIBRATOR=y
+BR2_PACKAGE_COREMARK=y
+BR2_PACKAGE_DHRYSTONE=y
+BR2_PACKAGE_GDB=y
+BR2_PACKAGE_GDB_SERVER=y
+BR2_PACKAGE_GDB_DEBUGGER=y
+BR2_PACKAGE_GDB_TUI=y
+BR2_PACKAGE_GDB_PYTHON=y
+BR2_PACKAGE_RAMSPEED=y
+BR2_PACKAGE_SPIDEV_TEST=y
+BR2_PACKAGE_STRACE=y
+BR2_PACKAGE_STRESS_NG=y
+BR2_PACKAGE_VMTOUCH=y
 BR2_PACKAGE_E2FSPROGS=y
 BR2_PACKAGE_E2FSPROGS_RESIZE2FS=y
-BR2_PACKAGE_TMUX=y
-BR2_PACKAGE_HTOP=y
-BR2_PACKAGE_LIBCURL=y
-BR2_PACKAGE_LIBCURL_CURL=y
-BR2_PACKAGE_LIBCURL_VERBOSE=y
-BR2_PACKAGE_LIBCURL_PROXY_SUPPORT=y
-BR2_PACKAGE_LIBCURL_COOKIES_SUPPORT=y
-BR2_PACKAGE_LIBCURL_WEBSOCKETS_SUPPORT=y
-BR2_PACKAGE_LIBCURL_EXTRA_PROTOCOLS_FEATURES=y
-BR2_PACKAGE_LIBCURL_OPENSSL=y
-BR2_PACKAGE_LIBWEBSOCKETS=y
-BR2_PACKAGE_WATCHDOG=y
+BR2_PACKAGE_EXFATPROGS=y
 BR2_PACKAGE_SQUASHFS=y
-BR2_PACKAGE_SQUASHFS_GZIP=y
 BR2_PACKAGE_SQUASHFS_LZ4=y
 BR2_PACKAGE_SQUASHFS_LZMA=y
 BR2_PACKAGE_SQUASHFS_LZO=y
 BR2_PACKAGE_SQUASHFS_XZ=y
 BR2_PACKAGE_SQUASHFS_ZSTD=y
-BR2_PACKAGE_LCDTEST=y
 BR2_PACKAGE_ASCII_INVADERS=y
 BR2_PACKAGE_GNUCHESS=y
 BR2_PACKAGE_SL=y
 BR2_PACKAGE_XORCURSES=y
-BR2_PACKAGE_INPUT_EVENT_DAEMON=y
-BR2_PACKAGE_BLUEZ_TOOLS=y
-BR2_PACKAGE_TPUDEMO_SG200X=y
-BR2_PACKAGE_SG2002_CODEC_FIRMWARE=y
-BR2_PACKAGE_TCPDUMP=y
-BR2_PACKAGE_SSDP_RESPONDER=y
-BR2_PACKAGE_PPPD=y
-BR2_PACKAGE_NFTABLES=y
-BR2_PACKAGE_IPTABLES=y
-BR2_PACKAGE_IPTABLES_NFTABLES=y
-BR2_PACKAGE_NCURSES_WCHAR=y
-BR2_PACKAGE_LIBEDIT=y
-BR2_PACKAGE_NGINX=y
-BR2_PACKAGE_NGINX_HTTP=y
-BR2_PACKAGE_NGINX_HTTP_DAV_MODULE=y
-BR2_PACKAGE_NGINX_HTTP_MP4_MODULE=y
-BR2_PACKAGE_NGINX_HTTP_FLV_MODULE=y
-BR2_PACKAGE_NGINX_HTTP_GUNZIP_MODULE=y
-BR2_PACKAGE_NGINX_STREAM=y
-BR2_PACKAGE_NGINX_SELECT_MODULE=y
-BR2_PACKAGE_NGINX_HTTP_FASTCGI_MODULE=y
-BR2_PACKAGE_NGINX_HTTP_UWSGI_MODULE=y
-BR2_PACKAGE_NGINX_HTTP_SCGI_MODULE=y
-BR2_PACKAGE_RTC_TOOLS=y
-BR2_PACKAGE_PICOCOM=y
 BR2_PACKAGE_FBGRAB=y
+BR2_PACKAGE_DBUS_GLIB=y
+BR2_PACKAGE_EVTEST=y
+BR2_PACKAGE_IPMITOOL=y
+BR2_PACKAGE_IPMITOOL_LANPLUS=y
+BR2_PACKAGE_IPMITOOL_USB=y
+BR2_PACKAGE_IPMITOOL_IPMIEVD=y
+BR2_PACKAGE_IPMITOOL_IPMISHELL=y
+BR2_PACKAGE_MEMTESTER=y
 BR2_PACKAGE_MHZ=y
+BR2_PACKAGE_OPENIPMI=y
+BR2_PACKAGE_PARTED=y
+BR2_PACKAGE_PICOCOM=y
+BR2_PACKAGE_RTC_TOOLS=y
 BR2_PACKAGE_SETSERIAL=y
+BR2_PACKAGE_SYSSTAT=y
 BR2_PACKAGE_UBOOT_TOOLS=y
 BR2_PACKAGE_UBOOT_TOOLS_FIT_SUPPORT=y
 BR2_PACKAGE_UBOOT_TOOLS_MKIMAGE=y
 BR2_PACKAGE_UBOOT_TOOLS_DUMPIMAGE=y
-
-# if your sdnand is small, you can delete some package
-
-BR2_PACKAGE_IMAGEMAGICK=y
-BR2_PACKAGE_OCRAD=y
-BR2_PACKAGE_SDL=y
-BR2_PACKAGE_SDL_FBCON=y
-BR2_PACKAGE_SDL_GFX=y
-BR2_PACKAGE_SDL_IMAGE=y
-BR2_PACKAGE_SDL_IMAGE_BMP=y
-BR2_PACKAGE_SDL_IMAGE_GIF=y
-BR2_PACKAGE_SDL_IMAGE_JPEG=y
-BR2_PACKAGE_SDL_IMAGE_PNG=y
-BR2_PACKAGE_SDL_IMAGE_WEBP=y
-BR2_PACKAGE_SDL_MIXER=y
-BR2_PACKAGE_SDL_NET=y
-BR2_PACKAGE_SDL_SOUND=y
-BR2_PACKAGE_SDL_SOUND_PLAYSOUND=y
-BR2_PACKAGE_LBREAKOUT2=y
-BR2_PACKAGE_LBREAKOUT2_AUDIO=y
-BR2_PACKAGE_LBREAKOUT2_NET=y
-BR2_PACKAGE_LTRIS=y
-BR2_PACKAGE_LTRIS_AUDIO=y
-BR2_PACKAGE_PRBOOM=y
-BR2_PACKAGE_DOOM_WAD=y
+BR2_PACKAGE_PYTHON3=y
+BR2_PACKAGE_PYTHON3_PY_PYC=y
+BR2_PACKAGE_PYTHON3_2TO3=y
+BR2_PACKAGE_PYTHON3_CURSES=y
+BR2_PACKAGE_PYTHON3_READLINE=y
+BR2_PACKAGE_PYTHON3_XZ=y
+BR2_PACKAGE_PYTHON_AENUM=y
+BR2_PACKAGE_PYTHON_ALSAAUDIO=y
+BR2_PACKAGE_PYTHON_BEAUTIFULSOUP4=y
+BR2_PACKAGE_PYTHON_BROTLI=y
+BR2_PACKAGE_PYTHON_BSDIFF4=y
+BR2_PACKAGE_PYTHON_CRC16=y
+BR2_PACKAGE_PYTHON_CRCMOD=y
+BR2_PACKAGE_PYTHON_CRONTAB=y
+BR2_PACKAGE_PYTHON_CYCLER=y
+BR2_PACKAGE_PYTHON_DBUS_FAST=y
+BR2_PACKAGE_PYTHON_DBUS_NEXT=y
+BR2_PACKAGE_PYTHON_DJANGO=y
+BR2_PACKAGE_PYTHON_EVDEV=y
+BR2_PACKAGE_PYTHON_FLASK_BABEL=y
+BR2_PACKAGE_PYTHON_FLASK_CORS=y
+BR2_PACKAGE_PYTHON_FLASK_JSONRPC=y
+BR2_PACKAGE_PYTHON_FLASK_LOGIN=y
+BR2_PACKAGE_PYTHON_FLASK_SMOREST=y
+BR2_PACKAGE_PYTHON_FLASK_SQLALCHEMY=y
+BR2_PACKAGE_PYTHON_FLASK_WTF=y
+BR2_PACKAGE_PYTHON_FLATBUFFERS=y
+BR2_PACKAGE_PYTHON_HTML5LIB=y
+BR2_PACKAGE_PYTHON_HUMANIZE=y
+BR2_PACKAGE_PYTHON_HWDATA=y
+BR2_PACKAGE_PYTHON_INTELHEX=y
+BR2_PACKAGE_PYTHON_IPYTHON=y
+BR2_PACKAGE_PYTHON_IPYTHON_GENUTILS=y
+BR2_PACKAGE_PYTHON_KIWISOLVER=y
+BR2_PACKAGE_PYTHON_LIBEVDEV=y
+BR2_PACKAGE_PYTHON_LIBUSB1=y
+BR2_PACKAGE_PYTHON_LXML=y
+BR2_PACKAGE_PYTHON_MARKDOWN=y
+BR2_PACKAGE_PYTHON_MSGPACK=y
+BR2_PACKAGE_PYTHON_NETADDR=y
+BR2_PACKAGE_PYTHON_NETIFACES=y
+BR2_PACKAGE_PYTHON_NETWORKX=y
+BR2_PACKAGE_PYTHON_PAHO_MQTT=y
+BR2_PACKAGE_PYTHON_PERIPHERY=y
+BR2_PACKAGE_PYTHON_PIP=y
+BR2_PACKAGE_PYTHON_POSIX_IPC=y
+BR2_PACKAGE_PYTHON_PROTOBUF=y
+BR2_PACKAGE_PYTHON_PSUTIL=y
+BR2_PACKAGE_PYTHON_PYAES=y
+BR2_PACKAGE_PYTHON_PYALSA=y
+BR2_PACKAGE_PYTHON_PYDEVMEM=y
+BR2_PACKAGE_PYTHON_PYLIBFDT=y
+BR2_PACKAGE_PYTHON_PYMODBUS=y
+BR2_PACKAGE_PYTHON_PYPARSING=y
+BR2_PACKAGE_PYTHON_PYQRCODE=y
+BR2_PACKAGE_PYTHON_PYSMB=y
+BR2_PACKAGE_PYTHON_PYUDEV=y
+BR2_PACKAGE_PYTHON_PYUSB=y
+BR2_PACKAGE_PYTHON_PYZMQ=y
+BR2_PACKAGE_PYTHON_QRCODE=y
+BR2_PACKAGE_PYTHON_QRCODE_PIL=y
+BR2_PACKAGE_PYTHON_REQUESTS_OAUTHLIB=y
+BR2_PACKAGE_PYTHON_REQUESTS_TOOLBELT=y
+BR2_PACKAGE_PYTHON_SCAPY=y
+BR2_PACKAGE_PYTHON_SELENIUM=y
+BR2_PACKAGE_PYTHON_SERIAL_ASYNCIO=y
+BR2_PACKAGE_PYTHON_SMBUS_CFFI=y
+BR2_PACKAGE_PYTHON_SNAPPY=y
+BR2_PACKAGE_PYTHON_SOCKETIO=y
+BR2_PACKAGE_PYTHON_SPIDEV=y
+BR2_PACKAGE_PYTHON_TINYRPC=y
+BR2_PACKAGE_PYTHON_TOML=y
+BR2_PACKAGE_PYTHON_TORNADO=y
+BR2_PACKAGE_PYTHON_UBJSON=y
+BR2_PACKAGE_PYTHON_UHID=y
+BR2_PACKAGE_PYTHON_UJSON=y
+BR2_PACKAGE_PYTHON_WATCHDOG=y
+BR2_PACKAGE_PYTHON_WEBSOCKET_CLIENT=y
+BR2_PACKAGE_PYTHON_WEBSOCKETS=y
+BR2_PACKAGE_PYTHON_XLSXWRITER=y
+BR2_PACKAGE_PYTHON_XLUTILS=y
+BR2_PACKAGE_PYTHON_XMODEM=y
+BR2_PACKAGE_PYTHON_ZEROCONF=y
 BR2_PACKAGE_TCL=y
-# BR2_PACKAGE_TCL_SHLIB_ONLY is not set
 # BR2_PACKAGE_TCL_DEL_ENCODINGS is not set
+# BR2_PACKAGE_TCL_SHLIB_ONLY is not set
 BR2_PACKAGE_EXPECT=y
 BR2_PACKAGE_TCLLIB=y
+BR2_PACKAGE_SBC=y
+BR2_PACKAGE_LIBZIP=y
+BR2_PACKAGE_LZ4_PROGS=y
+BR2_PACKAGE_SZIP=y
+BR2_PACKAGE_CA_CERTIFICATES=y
+BR2_PACKAGE_LIBOPENSSL_BIN=y
+BR2_PACKAGE_LIBOPENSSL_ENGINES=y
+BR2_PACKAGE_LIBQRENCODE=y
+BR2_PACKAGE_LIBQRENCODE_TOOLS=y
 BR2_PACKAGE_OPENCV4=y
-BR2_PACKAGE_OPENCV4_LIB_CALIB3D=y
-BR2_PACKAGE_OPENCV4_LIB_DNN=y
-BR2_PACKAGE_OPENCV4_LIB_HIGHGUI=y
-BR2_PACKAGE_OPENCV4_LIB_OBJDETECT=y
-BR2_PACKAGE_OPENCV4_LIB_PHOTO=y
+BR2_PACKAGE_OPENCV4_LIB_PYTHON=y
 BR2_PACKAGE_OPENCV4_LIB_SHAPE=y
 BR2_PACKAGE_OPENCV4_LIB_STITCHING=y
 BR2_PACKAGE_OPENCV4_LIB_SUPERRES=y
@@ -269,137 +206,85 @@ BR2_PACKAGE_OPENCV4_WITH_TIFF=y
 BR2_PACKAGE_OPENCV4_WITH_V4L=y
 BR2_PACKAGE_OPENCV4_WITH_WEBP=y
 BR2_PACKAGE_OPENCV4_INSTALL_DATA=y
-BR2_PACKAGE_LIBQRENCODE=y
-BR2_PACKAGE_LIBQRENCODE_TOOLS=y
-BR2_PACKAGE_FFMPEG=y
-BR2_PACKAGE_FFMPEG_FFMPEG=y
-BR2_PACKAGE_FFMPEG_FFPROBE=y
-BR2_PACKAGE_FFMPEG_GPL=y
-BR2_PACKAGE_FFMPEG_NONFREE=y
-BR2_PACKAGE_FFMPEG_POSTPROC=y
-BR2_PACKAGE_MULTICAT=y
-BR2_PACKAGE_WQY_ZENHEI=y
-BR2_PACKAGE_DEJAVU=y
-BR2_PACKAGE_GNUPLOT=y
-BR2_PACKAGE_TESSERACT_OCR=y
-BR2_PACKAGE_TESSERACT_OCR_LANG_ENG=y
-BR2_PACKAGE_TESSERACT_OCR_LANG_CHI_SIM=y
-BR2_PACKAGE_TESSERACT_OCR_LANG_CHI_TRA=y
-BR2_PACKAGE_QT5=y
-BR2_PACKAGE_QT5BASE_SQLITE_SYSTEM=y
-BR2_PACKAGE_QT5BASE_GUI=y
-BR2_PACKAGE_QT5BASE_LINUXFB=y
-BR2_PACKAGE_QT5BASE_WIDGETS=y
-BR2_PACKAGE_QT5BASE_DEFAULT_QPA="linuxfb"
-BR2_PACKAGE_QT5BASE_FONTCONFIG=y
-BR2_PACKAGE_QT5BASE_GIF=y
-BR2_PACKAGE_QT5BASE_PNG=y
-BR2_PACKAGE_QT5BASE_JPEG=y
-BR2_PACKAGE_QT5BASE_SYSLOG=y
-BR2_PACKAGE_QT5BASE_DBUS=y
-BR2_PACKAGE_QT5BASE_TSLIB=y
-BR2_PACKAGE_QT5BASE_EXAMPLES=y
-BR2_PACKAGE_QT5BASE_CONCURRENT=y
-BR2_PACKAGE_QT5CONNECTIVITY=y
-BR2_PACKAGE_QT5IMAGEFORMATS=y
-BR2_PACKAGE_QT5MULTIMEDIA=y
-BR2_PACKAGE_QT5SENSORS=y
-BR2_PACKAGE_QT5SERIALBUS=y
-BR2_PACKAGE_QT5CHARTS=y
-BR2_PACKAGE_QT5COAP=y
-BR2_PACKAGE_QT5ENGINIO=y
-BR2_PACKAGE_QT5KNX=y
-BR2_PACKAGE_QT5LOCATION=y
-BR2_PACKAGE_QT5MQTT=y
-BR2_PACKAGE_QT5OPCUA=y
-BR2_PACKAGE_QT5REMOTEOBJECTS=y
-BR2_PACKAGE_QT5SPEECH=y
-BR2_PACKAGE_QT5SVG=y
-BR2_PACKAGE_QT5WEBSOCKETS=y
-BR2_PACKAGE_QT5WEBCHANNEL=y
-BR2_PACKAGE_QEXTSERIALPORT=y
-BR2_PACKAGE_QT5X11EXTRAS=y
-BR2_PACKAGE_QT5XMLPATTERNS=y
-BR2_PACKAGE_QT5BASE_MYSQL=y
-BR2_PACKAGE_QJSON=y
-BR2_PACKAGE_QUAZIP=y
-BR2_PACKAGE_PYTHON3=y
-BR2_PACKAGE_PYTHON3_2TO3=y
-BR2_PACKAGE_PYTHON3_BZIP2=y
-BR2_PACKAGE_PYTHON3_CODECSCJK=y
-BR2_PACKAGE_PYTHON3_CURSES=y
-BR2_PACKAGE_PYTHON3_SSL=y
-BR2_PACKAGE_PYTHON3_UNICODEDATA=y
-BR2_PACKAGE_PYTHON3_SQLITE=y
-BR2_PACKAGE_PYTHON3_XZ=y
-BR2_PACKAGE_PYTHON3_ZLIB=y
-BR2_PACKAGE_PYTHON_NUMPY=y
-BR2_PACKAGE_OPENCV4_LIB_PYTHON=y
-BR2_PACKAGE_OPENCV4_WITH_QT5=y
-BR2_PACKAGE_PYTHON_BSDIFF4=y
-BR2_PACKAGE_PYTHON_BEAUTIFULSOUP4=y
-BR2_PACKAGE_PYTHON_CFFI=y
-BR2_PACKAGE_PYTHON_CRC16=y
-BR2_PACKAGE_PYTHON_DBUS_FAST=y
-BR2_PACKAGE_PYTHON_DATEUTIL=y
-BR2_PACKAGE_PYTHON_DBUS_NEXT=y
-BR2_PACKAGE_PYTHON_DJANGO=y
-BR2_PACKAGE_PYTHON_FLASK=y
-BR2_PACKAGE_PYTHON_EVDEV=y
-BR2_PACKAGE_PYTHON_FLASK_BABEL=y
-BR2_PACKAGE_PYTHON_FLASK_CORS=y
-BR2_PACKAGE_PYTHON_FLASK_JSONRPC=y
-BR2_PACKAGE_PYTHON_FLASK_LOGIN=y
-BR2_PACKAGE_PYTHON_FLASK_SMOREST=y
-BR2_PACKAGE_PYTHON_FLASK_SQLALCHEMY=y
-BR2_PACKAGE_PYTHON_FLASK_WTF=y
-BR2_PACKAGE_PYTHON_HWDATA=y
-BR2_PACKAGE_PYTHON_PIP=y
-BR2_PACKAGE_PYTHON_PEXPECT=y
-BR2_PACKAGE_PYTHON_PSUTIL=y
-BR2_PACKAGE_PYTHON_PYAES=y
-BR2_PACKAGE_PYTHON_PYALSA=y
-BR2_PACKAGE_PYTHON_PYDEVMEM=y
-BR2_PACKAGE_PYTHON_PYUSB=y
-BR2_PACKAGE_PYTHON_REQUESTS=y
-BR2_PACKAGE_PYTHON_REQUESTS_OAUTHLIB=y
-BR2_PACKAGE_PYTHON_REQUESTS_TOOLBELT=y
-BR2_PACKAGE_PYTHON_SERIAL=y
-BR2_PACKAGE_PYTHON_SERIAL_ASYNCIO=y
-BR2_PACKAGE_PYTHON_WEBSOCKETS=y
-BR2_PACKAGE_PYTHON_WEBSOCKET_CLIENT=y
-BR2_PACKAGE_PYTHON_XMODEM=y
-BR2_PACKAGE_PYTHON3_PY_PYC=y
-BR2_PACKAGE_PYTHON_PYQT5=y
-BR2_PACKAGE_PYTHON_PYQRCODE=y
-BR2_PACKAGE_PYTHON_PYLIBFDT=y
-BR2_PACKAGE_PYTHON3_READLINE=y
-BR2_PACKAGE_PYTHON_JEDI=y
-BR2_PACKAGE_PYTHON_LIBUSB1=y
-BR2_PACKAGE_PYTHON_LXML=y
-BR2_PACKAGE_PYTHON_MARKDOWN=y
-BR2_PACKAGE_PYTHON_MSGPACK=y
-BR2_PACKAGE_PYTHON_PERIPHERY=y
-BR2_PACKAGE_PYTHON_PILLOW=y
-BR2_PACKAGE_PYTHON_POSIX_IPC=y
-BR2_PACKAGE_PYTHON_PROTOBUF=y
-BR2_PACKAGE_PYTHON_PYGAME=y
-BR2_PACKAGE_PYTHON_PYGAME_IMAGE=y
-BR2_PACKAGE_PYTHON_PYGAME_EXAMPLES=y
-BR2_PACKAGE_PYTHON_PYGAME_FONT=y
-BR2_PACKAGE_PYTHON_PYGAME_MIXER=y
-BR2_PACKAGE_PYTHON_PYUDEV=y
-BR2_PACKAGE_PYTHON_PYYAML=y
-BR2_PACKAGE_PYTHON_QRCODE=y
-BR2_PACKAGE_PYTHON_QRCODE_PIL=y
-BR2_PACKAGE_PYTHON_INTELHEX=y
-
+BR2_PACKAGE_LIBCURL=y
+BR2_PACKAGE_LIBCURL_CURL=y
+BR2_PACKAGE_LIBCURL_VERBOSE=y
+BR2_PACKAGE_LIBCURL_WEBSOCKETS_SUPPORT=y
+BR2_PACKAGE_LIBWEBSOCKETS=y
+BR2_PACKAGE_LIBBSD=y
+BR2_PACKAGE_NCURSES_WCHAR=y
+BR2_PACKAGE_EMPTY=y
+BR2_PACKAGE_HAVEGED=y
+BR2_PACKAGE_AIRCRACK_NG=y
+BR2_PACKAGE_AVAHI=y
+# BR2_PACKAGE_AVAHI_AUTOIPD is not set
+BR2_PACKAGE_AVAHI_DAEMON=y
+BR2_PACKAGE_AVAHI_DEFAULT_SERVICES=y
+BR2_PACKAGE_BIND=y
+BR2_PACKAGE_DNSMASQ=y
+BR2_PACKAGE_ETHTOOL=y
+BR2_PACKAGE_HOSTAPD=y
+BR2_PACKAGE_HOSTAPD_EAP=y
+BR2_PACKAGE_HOSTAPD_WPS=y
+BR2_PACKAGE_HOSTAPD_WPA3=y
+# BR2_PACKAGE_HOSTAPD_VLAN is not set
+BR2_PACKAGE_IPERF3=y
+BR2_PACKAGE_IPROUTE2=y
+BR2_PACKAGE_IPTABLES=y
+BR2_PACKAGE_IPTABLES_NFTABLES=y
+BR2_PACKAGE_IPUTILS=y
+BR2_PACKAGE_IW=y
+BR2_PACKAGE_LRZSZ=y
+BR2_PACKAGE_MACCHANGER=y
+BR2_PACKAGE_MOSH=y
+BR2_PACKAGE_MTR=y
+BR2_PACKAGE_NETCAT=y
+BR2_PACKAGE_NFTABLES=y
+BR2_PACKAGE_NTP=y
+BR2_PACKAGE_NTP_NTPDATE=y
+BR2_PACKAGE_PPPD=y
+BR2_PACKAGE_RSYNC=y
+BR2_PACKAGE_SER2NET=y
+BR2_PACKAGE_SOCAT=y
+BR2_PACKAGE_SSDP_RESPONDER=y
+BR2_PACKAGE_TCPDUMP=y
+BR2_PACKAGE_TINC=y
+BR2_PACKAGE_TRACEROUTE=y
+BR2_PACKAGE_WIREGUARD_TOOLS=y
+BR2_PACKAGE_WIRELESS_REGDB=y
+BR2_PACKAGE_WIRELESS_TOOLS=y
+BR2_PACKAGE_WIRELESS_TOOLS_IFRENAME=y
+BR2_PACKAGE_WIRELESS_TOOLS_LIB=y
+BR2_PACKAGE_WPA_SUPPLICANT=y
+BR2_PACKAGE_WPA_SUPPLICANT_WEXT=y
+BR2_PACKAGE_WPA_SUPPLICANT_IBSS_RSN=y
+BR2_PACKAGE_WPA_SUPPLICANT_AP_SUPPORT=y
+BR2_PACKAGE_WPA_SUPPLICANT_WIFI_DISPLAY=y
+BR2_PACKAGE_WPA_SUPPLICANT_MESH_NETWORKING=y
+BR2_PACKAGE_WPA_SUPPLICANT_OVERRIDES=y
+BR2_PACKAGE_WPA_SUPPLICANT_AUTOSCAN=y
+BR2_PACKAGE_WPA_SUPPLICANT_HOTSPOT=y
+BR2_PACKAGE_WPA_SUPPLICANT_DEBUG_SYSLOG=y
+BR2_PACKAGE_WPA_SUPPLICANT_WPS=y
+BR2_PACKAGE_WPA_SUPPLICANT_WPA3=y
+BR2_PACKAGE_WPA_SUPPLICANT_CLI=y
+BR2_PACKAGE_WPA_SUPPLICANT_WPA_CLIENT_SO=y
+BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y
+BR2_PACKAGE_WPA_SUPPLICANT_DBUS=y
+BR2_PACKAGE_BASH=y
+BR2_PACKAGE_FILE=y
+BR2_PACKAGE_TMUX=y
+BR2_PACKAGE_AXP2101=y
+BR2_PACKAGE_HTOP=y
+BR2_PACKAGE_UTIL_LINUX_RFKILL=y
+BR2_PACKAGE_WATCHDOG=y
+BR2_PACKAGE_NANO=y
 BR2_PACKAGE_VIM=y
-BR2_PACKAGE_VIM_RUNTIME=y
-
+BR2_PACKAGE_AIC8800_SDIO_FIRMWARE=y
+BR2_PACKAGE_CVITEK_RISCV64_MUSL_SYSROOT=y
+BR2_PACKAGE_LCDTEST=y
+BR2_PACKAGE_TPUDEMO_SG200X=y
+BR2_PACKAGE_SG2002_CODEC_FIRMWARE=y
 BR2_TARGET_ROOTFS_EXT2=y
 BR2_TARGET_ROOTFS_EXT2_4=y
-BR2_TARGET_ROOTFS_EXT2_SIZE="900M"
-
-BR2_ROOTFS_OVERLAY="$(TOPDIR)/board/cvitek/SG200X/overlay"
-BR2_PACKAGE_BUSYBOX_CONFIG_FRAGMENT_FILES="$(TOPDIR)/board/cvitek/SG200X/busybox-extra.config"
+BR2_TARGET_ROOTFS_EXT2_SIZE="1536M"

buildroot/package/Config.in

@@ -2680,6 +2680,7 @@ menu "System tools"
 	source "package/atop/Config.in"
 	source "package/attr/Config.in"
 	source "package/audit/Config.in"
+	source "package/axp2101/Config.in"
 	source "package/balena-engine/Config.in"
 	source "package/bubblewrap/Config.in"
 	source "package/cgroupfs-mount/Config.in"
@@ -2808,6 +2809,8 @@ menu "Sipeed"
 	source "package/tpudemo-sg200x/Config.in"
 	source "package/xuantie-gdb/Config.in"
 	source "package/sg2002-codec-firmware/Config.in"
+	source "package/mgba/Config.in"
+	source "package/gb-test-roms/Config.in"
 endmenu
 
 

buildroot/package/aic8800-sdio-firmware/aic8800-sdio-firmware.mk

@@ -4,8 +4,8 @@
 #
 ################################################################################
 
-AIC8800_SDIO_FIRMWARE_VERSION = e44a51d3c129bbd7413848a430b8206556e923a5
-AIC8800_SDIO_FIRMWARE_SITE = $(call github,0x754C,aic8800-sdio-firmware,$(AIC8800_SDIO_FIRMWARE_VERSION))
+AIC8800_SDIO_FIRMWARE_VERSION = c56f910044cc854d6c553bcb9a644f3bca5a4c38
+AIC8800_SDIO_FIRMWARE_SITE = $(call github,lxowalle,aic8800-sdio-firmware,$(AIC8800_SDIO_FIRMWARE_VERSION))
 
 define AIC8800_SDIO_FIRMWARE_INSTALL_TARGET_CMDS
 	mkdir -pv $(TARGET_DIR)/usr/lib/firmware/aic8800_sdio/

buildroot/package/axp2101/Config.in

@@ -0,0 +1,5 @@
+config BR2_PACKAGE_AXP2101
+    bool "axp2101"
+    help
+      If you say Y here you get support for the X-Powers AXP2101 power
+      management ICs (PMICs) controlled with I2C.

buildroot/package/axp2101/axp2101.mk

@@ -0,0 +1,20 @@
+################################################################################
+#
+# axp2101
+#
+################################################################################
+
+AXP2101_VERSION = 1.1.0
+AXP2101_SITE = $(TOPDIR)/package/axp2101/src
+AXP2101_SITE_METHOD = local
+AXP2101_CFLAGS = -Iinclude -IXPowersLib -IXPowersLib/REG -Wall -Wextra
+
+define AXP2101_BUILD_CMDS
+    $(MAKE) $(TARGET_CONFIGURE_OPTS) CFLAGS="$(AXP2101_CFLAGS)" -C $(@D)
+endef
+
+define AXP2101_INSTALL_TARGET_CMDS
+    $(INSTALL) -D -m 0755 $(@D)/axp2101 $(TARGET_DIR)/usr/bin/axp2101
+endef
+
+$(eval $(generic-package))

buildroot/package/axp2101/src/Makefile

@@ -0,0 +1,26 @@
+APP_DIR = ./src
+SRC_DIR = ./XPowersLib
+DIR_BIN = ./bin
+
+OBJ_C = $(wildcard ${SRC_DIR}/*.cpp ${APP_DIR}/*.cpp)
+OBJ_O = $(patsubst %.cpp,${DIR_BIN}/%.o,$(notdir ${OBJ_C}))
+
+TARGET = axp2101
+
+$(shell mkdir -p $(DIR_BIN))
+
+MSG = -g -O0 -Wall 
+CFLAGS += $(MSG)
+
+${TARGET}:${OBJ_O}
+	$(CXX) $(CFLAGS) $(OBJ_O) -o $@ $(LIB)
+
+${DIR_BIN}/%.o:$(APP_DIR)/%.cpp
+	$(CXX) $(CFLAGS) -c  $< -o $@ -I $(SRC_DIR)
+
+${DIR_BIN}/%.o:$(SRC_DIR)/%.cpp
+	$(CXX) $(CFLAGS) -c  $< -o $@ $(LIB)
+
+clean :
+	rm $(DIR_BIN)/*.* 
+	rm $(TARGET) 

buildroot/package/axp2101/src/XPowersLib/PowerDeliveryHUSB238.hpp

@@ -0,0 +1,171 @@
+/**
+ *
+ * @license MIT License
+ *
+ * Copyright (c) 2024 lewis he
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * @file      PowerDeliveryHUSB238.tpp
+ * @author    Lewis He (lewishe@outlook.com)
+ * @date      2024-07-24
+ *
+ */
+#if defined(ARDUINO)
+#include <Arduino.h>
+#else
+#include <math.h>
+#endif /*ARDUINO*/
+#include "XPowersCommon.tpp"
+#include "REG/HUSB238Constants.h"
+
+class PowerDeliveryHUSB238 :
+    public XPowersCommon<PowerDeliveryHUSB238>
+{
+    friend class XPowersCommon<PowerDeliveryHUSB238>;
+
+public:
+
+    enum PD_Status {
+        NO_RESPONSE,
+        SUCCESS,
+        INVALID_CMD,
+        NOT_SUPPORT,
+        TRANSACTION_FAIL
+    };
+
+    enum PD_Voltage {
+        PD_5V = 1,
+        PD_9V,
+        PD_12V,
+        PD_15V,
+        PD_18V,
+        PD_20V
+    };
+
+
+#if defined(ARDUINO)
+    PowerDeliveryHUSB238(TwoWire &w, int sda = SDA, int scl = SCL, uint8_t addr = HUSB238_SLAVE_ADDRESS)
+    {
+        __wire = &w;
+        __sda = sda;
+        __scl = scl;
+        __addr = addr;
+    }
+#endif
+
+    PowerDeliveryHUSB238(uint8_t addr, iic_fptr_t readRegCallback, iic_fptr_t writeRegCallback)
+    {
+        thisReadRegCallback = readRegCallback;
+        thisWriteRegCallback = writeRegCallback;
+        __addr = addr;
+    }
+
+    PowerDeliveryHUSB238()
+    {
+#if defined(ARDUINO)
+        __wire = &Wire;
+        __sda = SDA;
+        __scl = SCL;
+#endif
+        __addr = HUSB238_SLAVE_ADDRESS;
+    }
+
+
+    ~PowerDeliveryHUSB238()
+    {
+        log_i("~PowerDeliveryHUSB238");
+        deinit();
+    }
+
+#if defined(ARDUINO)
+    bool init(TwoWire &w, int sda = SDA, int scl = SCL, uint8_t addr = HUSB238_SLAVE_ADDRESS)
+    {
+        __wire = &w;
+        __sda = sda;
+        __scl = scl;
+        __addr = addr;
+        return begin();
+    }
+#endif
+
+    void deinit()
+    {
+        end();
+    }
+
+    uint8_t getPdVoltage()
+    {
+        int val =  readRegister(HUSB238_PD_STATUS0);
+        if (val == -1)return 0;
+        val &= 0xF0;
+        val >>= 4;
+        return pd_voltage_list[val];
+    }
+
+    float getPdCurrent()
+    {
+        int val =  readRegister(HUSB238_PD_STATUS0);
+        if (val == -1)return 0;
+        val &= 0x0F;
+        return pd_current_list[val];
+    }
+
+    void setPdVoltage(PD_Voltage vol)
+    {
+        writeRegister(HUSB238_SRC_PDO, vol);
+        writeRegister(HUSB238_GO_COMMAND, 0x01);
+    }
+
+    void resetPdVoltage()
+    {
+        writeRegister(HUSB238_GO_COMMAND, 0x10);
+    }
+
+    bool attach()
+    {
+        return getRegisterBit(HUSB238_PD_STATUS1, 6);
+    }
+
+    PD_Status status()
+    {
+        int val = readRegister(HUSB238_PD_STATUS1);
+        if (val == -1)return NO_RESPONSE;
+        val >>= 3;
+        val &= 0x03;
+        return static_cast<PD_Status>(val);
+    }
+
+
+private:
+    const uint8_t pd_voltage_list[7] = {0, 5, 9, 12, 15, 18, 20};
+    const float pd_current_list[16] = {
+        0.5, 0.7, 1, 1.25, 1.5, 1.75, 2, 2.25, 2.5,
+        2.75, 3, 3.25, 3.5, 4, 4.5, 5
+    };
+
+    bool initImpl()
+    {
+        return readRegister(HUSB238_PD_STATUS0) != -1;
+    }
+
+};
+
+
+

buildroot/package/axp2101/src/XPowersLib/REG/AXP192Constants.h

@@ -0,0 +1,182 @@
+#pragma once
+
+#define AXP192_SLAVE_ADDRESS                            (0x34)
+
+#define XPOWERS_AXP192_CHIP_ID                          (0x03)
+
+#define XPOWERS_AXP192_STATUS                           (0x00)
+#define XPOWERS_AXP192_MODE_CHGSTATUS                   (0x01)
+#define XPOWERS_AXP192_OTG_STATUS                       (0x02)
+#define XPOWERS_AXP192_IC_TYPE                          (0x03)
+
+#define XPOWERS_AXP192_DATA_BUFFER1                     (0x06)
+#define XPOWERS_AXP192_DATA_BUFFER2                     (0x07)
+#define XPOWERS_AXP192_DATA_BUFFER3                     (0x08)
+#define XPOWERS_AXP192_DATA_BUFFER4                     (0x09)
+#define XPOWERS_AXP192_DATA_BUFFER5                     (0x0A)
+#define XPOWERS_AXP192_DATA_BUFFER6                     (0x0B)
+#define XPOWERS_AXP192_DATA_BUFFER_SIZE                 (6)
+
+
+#define XPOWERS_AXP192_LDO23_DC123_EXT_CTL              (0x12)
+#define XPOWERS_AXP192_DC2OUT_VOL                       (0x23)
+#define XPOWERS_AXP192_DC2_DVM                          (0x25)
+#define XPOWERS_AXP192_DC3OUT_VOL                       (0x27)
+#define XPOWERS_AXP192_LDO24OUT_VOL                     (0x28)
+#define XPOWERS_AXP192_LDO3OUT_VOL                      (0x29)
+#define XPOWERS_AXP192_IPS_SET                          (0x30)
+#define XPOWERS_AXP192_VOFF_SET                         (0x31)
+#define XPOWERS_AXP192_OFF_CTL                          (0x32)
+#define XPOWERS_AXP192_CHARGE1                          (0x33)
+#define XPOWERS_AXP192_CHARGE2                          (0x34)
+#define XPOWERS_AXP192_BACKUP_CHG                       (0x35)
+#define XPOWERS_AXP192_POK_SET                          (0x36)
+#define XPOWERS_AXP192_DCDC_FREQSET                     (0x37)
+#define XPOWERS_AXP192_VLTF_CHGSET                      (0x38)
+#define XPOWERS_AXP192_VHTF_CHGSET                      (0x39)
+#define XPOWERS_AXP192_APS_WARNING1                     (0x3A)
+#define XPOWERS_AXP192_APS_WARNING2                     (0x3B)
+#define XPOWERS_AXP192_TLTF_DISCHGSET                   (0x3C)
+#define XPOWERS_AXP192_THTF_DISCHGSET                   (0x3D)
+#define XPOWERS_AXP192_DCDC_MODESET                     (0x80)
+#define XPOWERS_AXP192_ADC_EN1                          (0x82)
+#define XPOWERS_AXP192_ADC_EN2                          (0x83)
+#define XPOWERS_AXP192_ADC_SPEED                        (0x84)
+#define XPOWERS_AXP192_ADC_INPUTRANGE                   (0x85)
+#define XPOWERS_AXP192_ADC_IRQ_RETFSET                  (0x86)
+#define XPOWERS_AXP192_ADC_IRQ_FETFSET                  (0x87)
+#define XPOWERS_AXP192_TIMER_CTL                        (0x8A)
+#define XPOWERS_AXP192_VBUS_DET_SRP                     (0x8B)
+#define XPOWERS_AXP192_HOTOVER_CTL                      (0x8F)
+
+#define XPOWERS_AXP192_PWM1_FREQ_SET                    (0x98)
+#define XPOWERS_AXP192_PWM1_DUTY_SET1                   (0x99)
+#define XPOWERS_AXP192_PWM1_DUTY_SET2                   (0x9A)
+
+#define XPOWERS_AXP192_PWM2_FREQ_SET                    (0x9B)
+#define XPOWERS_AXP192_PWM2_DUTY_SET1                   (0x9C)
+#define XPOWERS_AXP192_PWM2_DUTY_SET2                   (0x9D)
+
+
+// INTERRUPT REGISTER
+#define XPOWERS_AXP192_INTEN1                           (0x40)
+#define XPOWERS_AXP192_INTEN2                           (0x41)
+#define XPOWERS_AXP192_INTEN3                           (0x42)
+#define XPOWERS_AXP192_INTEN4                           (0x43)
+#define XPOWERS_AXP192_INTEN5                           (0x4A)
+
+// INTERRUPT STATUS REGISTER
+#define XPOWERS_AXP192_INTSTS1                          (0x44)
+#define XPOWERS_AXP192_INTSTS2                          (0x45)
+#define XPOWERS_AXP192_INTSTS3                          (0x46)
+#define XPOWERS_AXP192_INTSTS4                          (0x47)
+#define XPOWERS_AXP192_INTSTS5                          (0x4D)
+#define XPOWERS_AXP192_INTSTS_CNT                       (5)
+
+#define XPOWERS_AXP192_DC1_VLOTAGE                      (0x26)
+#define XPOWERS_AXP192_LDO23OUT_VOL                     (0x28)
+#define XPOWERS_AXP192_GPIO0_CTL                        (0x90)
+#define XPOWERS_AXP192_GPIO0_VOL                        (0x91)
+#define XPOWERS_AXP192_GPIO1_CTL                        (0X92)
+#define XPOWERS_AXP192_GPIO2_CTL                        (0x93)
+#define XPOWERS_AXP192_GPIO012_SIGNAL                   (0x94)
+#define XPOWERS_AXP192_GPIO34_CTL                       (0x95)
+#define XPOWERS_AXP192_GPIO34_SIGNAL                    (0x96)
+#define XPOWERS_AXP192_GPIO012_PULLDOWN                 (0x97)
+#define XPOWERS_AXP192_GPIO5_CTL                        (0x9E)
+
+#define XPOWERS_AXP192_GPIO0_VOL_ADC_H8                 (0x64)
+#define XPOWERS_AXP192_GPIO0_VOL_ADC_L4                 (0x65)
+#define XPOWERS_AXP192_GPIO1_VOL_ADC_H8                 (0x66)
+#define XPOWERS_AXP192_GPIO1_VOL_ADC_L4                 (0x67)
+#define XPOWERS_AXP192_GPIO2_VOL_ADC_H8                 (0x68)
+#define XPOWERS_AXP192_GPIO2_VOL_ADC_L4                 (0x69)
+#define XPOWERS_AXP192_GPIO3_VOL_ADC_H8                 (0x6A)
+#define XPOWERS_AXP192_GPIO3_VOL_ADC_L4                 (0x6B)
+
+#define XPOWERS_AXP192_GPIO0_STEP                       (0.5F)
+#define XPOWERS_AXP192_GPIO1_STEP                       (0.5F)
+#define XPOWERS_AXP192_TS_IN_H8                         (0x62)
+#define XPOWERS_AXP192_TS_IN_L4                         (0x63)
+
+#define XPOWERS_AXP192_BAT_AVERCHGCUR_H8                (0x7A)
+#define XPOWERS_AXP192_BAT_AVERCHGCUR_L5                (0x7B)
+
+
+#define XPOWERS_AXP192_ACIN_VOL_H8                      (0x56)
+#define XPOWERS_AXP192_ACIN_VOL_L4                      (0x57)
+#define XPOWERS_AXP192_ACIN_CUR_H8                      (0x58)
+#define XPOWERS_AXP192_ACIN_CUR_L4                      (0x59)
+#define XPOWERS_AXP192_VBUS_VOL_H8                      (0x5A)
+#define XPOWERS_AXP192_VBUS_VOL_L4                      (0x5B)
+#define XPOWERS_AXP192_VBUS_CUR_H8                      (0x5C)
+#define XPOWERS_AXP192_VBUS_CUR_L4                      (0x5D)
+
+#define XPOWERS_AXP192_BAT_AVERDISCHGCUR_H8             (0x7C)
+#define XPOWERS_AXP192_BAT_AVERDISCHGCUR_L5             (0x7D)
+#define XPOWERS_AXP192_APS_AVERVOL_H8                   (0x7E)
+#define XPOWERS_AXP192_APS_AVERVOL_L4                   (0x7F)
+#define XPOWERS_AXP192_BAT_AVERVOL_H8                   (0x78)
+#define XPOWERS_AXP192_BAT_AVERVOL_L4                   (0x79)
+
+#define XPOWERS_AXP192_BAT_CHGCOULOMB3                  (0xB0)
+#define XPOWERS_AXP192_BAT_CHGCOULOMB2                  (0xB1)
+#define XPOWERS_AXP192_BAT_CHGCOULOMB1                  (0xB2)
+#define XPOWERS_AXP192_BAT_CHGCOULOMB0                  (0xB3)
+#define XPOWERS_AXP192_BAT_DISCHGCOULOMB3               (0xB4)
+#define XPOWERS_AXP192_BAT_DISCHGCOULOMB2               (0xB5)
+#define XPOWERS_AXP192_BAT_DISCHGCOULOMB1               (0xB6)
+#define XPOWERS_AXP192_BAT_DISCHGCOULOMB0               (0xB7)
+#define XPOWERS_AXP192_COULOMB_CTL                      (0xB8)
+
+
+#define XPOWERS_AXP192_BATT_VOLTAGE_STEP                (1.1F)
+#define XPOWERS_AXP192_BATT_DISCHARGE_CUR_STEP          (0.5F)
+#define XPOWERS_AXP192_BATT_CHARGE_CUR_STEP             (0.5F)
+#define XPOWERS_AXP192_ACIN_VOLTAGE_STEP                (1.7F)
+#define XPOWERS_AXP192_ACIN_CUR_STEP                    (0.625F)
+#define XPOWERS_AXP192_VBUS_VOLTAGE_STEP                (1.7F)
+#define XPOWERS_AXP192_VBUS_CUR_STEP                    (0.375F)
+#define XPOWERS_AXP192_APS_VOLTAGE_STEP                 (1.4F)
+#define XPOWERS_AXP192_TS_PIN_OUT_STEP                  (0.8F)
+
+
+#define XPOWERS_AXP192_LDO2_VOL_MIN                     (1800u)
+#define XPOWERS_AXP192_LDO2_VOL_MAX                     (3300u)
+#define XPOWERS_AXP192_LDO2_VOL_STEPS                   (100u)
+#define XPOWERS_AXP192_LDO2_VOL_BIT_MASK                (4u)
+
+#define XPOWERS_AXP192_LDO3_VOL_MIN                     (1800u)
+#define XPOWERS_AXP192_LDO3_VOL_MAX                     (3300u)
+#define XPOWERS_AXP192_LDO3_VOL_STEPS                   (100u)
+
+
+#define XPOWERS_AXP192_DC1_VOL_STEPS                    (25u)
+#define XPOWERS_AXP192_DC1_VOL_MIN                      (700u)
+#define XPOWERS_AXP192_DC1_VOL_MAX                      (3500u)
+
+#define XPOWERS_AXP192_DC2_VOL_STEPS                    (25u)
+#define XPOWERS_AXP192_DC2_VOL_MIN                      (700u)
+#define XPOWERS_AXP192_DC2_VOL_MAX                      (3500u)
+
+#define XPOWERS_AXP192_DC3_VOL_STEPS                    (25u)
+#define XPOWERS_AXP192_DC3_VOL_MIN                      (700u)
+#define XPOWERS_AXP192_DC3_VOL_MAX                      (3500u)
+
+#define XPOWERS_AXP192_LDOIO_VOL_STEPS                  (100)
+#define XPOWERS_AXP192_LDOIO_VOL_MIN                    (1800)
+#define XPOWERS_AXP192_LDOIO_VOL_MAX                    (3300)
+
+#define XPOWERS_AXP192_SYS_VOL_STEPS                    (100)
+#define XPOWERS_AXP192_VOFF_VOL_MIN                     (2600)
+#define XPOWERS_AXP192_VOFF_VOL_MAX                     (3300)
+
+#define XPOWERS_AXP192_CHG_EXT_CURR_MIN                 (300)
+#define XPOWERS_AXP192_CHG_EXT_CURR_MAX                 (1000)
+#define XPOWERS_AXP192_CHG_EXT_CURR_STEP                (100)
+
+
+#define XPOWERS_AXP192_INTERNAL_TEMP_H8                 (0x5E)
+#define XPOWERS_AXP192_INTERNAL_TEMP_L4                 (0x5F)
+#define XPOWERS_AXP192_INTERNAL_TEMP_STEP               (0.1F)
+#define XPOWERS_AXP192_INERNAL_TEMP_OFFSET              (144.7)

buildroot/package/axp2101/src/XPowersLib/REG/AXP202Constants.h

@@ -0,0 +1,192 @@
+#pragma once
+
+#define AXP202_SLAVE_ADDRESS                            (0x35)
+
+#define XPOWERS_AXP202_CHIP_ID                          (0x41)
+
+#define XPOWERS_AXP202_STATUS                           (0x00)
+#define XPOWERS_AXP202_MODE_CHGSTATUS                   (0x01)
+#define XPOWERS_AXP202_OTG_STATUS                       (0x02)
+#define XPOWERS_AXP202_IC_TYPE                          (0x03)
+#define XPOWERS_AXP202_DATA_BUFFER1                     (0x04)
+#define XPOWERS_AXP202_DATA_BUFFER2                     (0x05)
+#define XPOWERS_AXP202_DATA_BUFFER3                     (0x06)
+#define XPOWERS_AXP202_DATA_BUFFER4                     (0x07)
+#define XPOWERS_AXP202_DATA_BUFFER5                     (0x08)
+#define XPOWERS_AXP202_DATA_BUFFER6                     (0x09)
+#define XPOWERS_AXP202_DATA_BUFFER7                     (0x0A)
+#define XPOWERS_AXP202_DATA_BUFFER8                     (0x0B)
+#define XPOWERS_AXP202_DATA_BUFFER9                     (0x0C)
+#define XPOWERS_AXP202_DATA_BUFFERA                     (0x0D)
+#define XPOWERS_AXP202_DATA_BUFFERB                     (0x0E)
+#define XPOWERS_AXP202_DATA_BUFFERC                     (0x0F)
+#define XPOWERS_AXP202_LDO234_DC23_CTL                  (0x12)
+#define XPOWERS_AXP202_DC2OUT_VOL                       (0x23)
+#define XPOWERS_AXP202_LDO3_DC2_DVM                     (0x25)
+#define XPOWERS_AXP202_DC3OUT_VOL                       (0x27)
+#define XPOWERS_AXP202_LDO24OUT_VOL                     (0x28)
+#define XPOWERS_AXP202_LDO3OUT_VOL                      (0x29)
+#define XPOWERS_AXP202_IPS_SET                          (0x30)
+#define XPOWERS_AXP202_VOFF_SET                         (0x31)
+#define XPOWERS_AXP202_OFF_CTL                          (0x32)
+#define XPOWERS_AXP202_CHARGE1                          (0x33)
+#define XPOWERS_AXP202_CHARGE2                          (0x34)
+#define XPOWERS_AXP202_BACKUP_CHG                       (0x35)
+#define XPOWERS_AXP202_POK_SET                          (0x36)
+#define XPOWERS_AXP202_DCDC_FREQSET                     (0x37)
+#define XPOWERS_AXP202_VLTF_CHGSET                      (0x38)
+#define XPOWERS_AXP202_VHTF_CHGSET                      (0x39)
+#define XPOWERS_AXP202_APS_WARNING1                     (0x3A)
+#define XPOWERS_AXP202_APS_WARNING2                     (0x3B)
+#define XPOWERS_AXP202_TLTF_DISCHGSET                   (0x3C)
+#define XPOWERS_AXP202_THTF_DISCHGSET                   (0x3D)
+#define XPOWERS_AXP202_DCDC_MODESET                     (0x80)
+#define XPOWERS_AXP202_ADC_EN1                          (0x82)
+#define XPOWERS_AXP202_ADC_EN2                          (0x83)
+#define XPOWERS_AXP202_ADC_SPEED                        (0x84)
+#define XPOWERS_AXP202_ADC_INPUTRANGE                   (0x85)
+#define XPOWERS_AXP202_ADC_IRQ_RETFSET                  (0x86)
+#define XPOWERS_AXP202_ADC_IRQ_FETFSET                  (0x87)
+#define XPOWERS_AXP202_TIMER_CTL                        (0x8A)
+#define XPOWERS_AXP202_VBUS_DET_SRP                     (0x8B)
+#define XPOWERS_AXP202_HOTOVER_CTL                      (0x8F)
+
+#define XPOWERS_AXP202_DATA_BUFFER_SIZE                 (12)
+#define XPOWERS_AXP202_GPIO0_CTL                        (0x90)
+#define XPOWERS_AXP202_GPIO0_VOL                        (0x91)
+#define XPOWERS_AXP202_GPIO1_CTL                        (0x92)
+#define XPOWERS_AXP202_GPIO2_CTL                        (0x93)
+#define XPOWERS_AXP202_GPIO012_SIGNAL                   (0x94)
+#define XPOWERS_AXP202_GPIO3_CTL                        (0x95)
+
+// INTERRUPT REGISTER
+#define XPOWERS_AXP202_INTEN1                           (0x40)
+#define XPOWERS_AXP202_INTEN2                           (0x41)
+#define XPOWERS_AXP202_INTEN3                           (0x42)
+#define XPOWERS_AXP202_INTEN4                           (0x43)
+#define XPOWERS_AXP202_INTEN5                           (0x44)
+
+//INTERRUPT STATUS REGISTER
+#define XPOWERS_AXP202_INTSTS1                          (0x48)
+#define XPOWERS_AXP202_INTSTS2                          (0x49)
+#define XPOWERS_AXP202_INTSTS3                          (0x4A)
+#define XPOWERS_AXP202_INTSTS4                          (0x4B)
+#define XPOWERS_AXP202_INTSTS5                          (0x4C)
+#define XPOWERS_AXP202_INTSTS_CNT                       (5)
+
+
+//AXP ADC DATA REGISTER
+#define XPOWERS_AXP202_GPIO0_VOL_ADC_H8                 (0x64)
+#define XPOWERS_AXP202_GPIO0_VOL_ADC_L4                 (0x65)
+#define XPOWERS_AXP202_GPIO1_VOL_ADC_H8                 (0x66)
+#define XPOWERS_AXP202_GPIO1_VOL_ADC_L4                 (0x67)
+
+
+#define XPOWERS_AXP202_GPIO0_STEP                       (0.5F)
+#define XPOWERS_AXP202_GPIO1_STEP                       (0.5F)
+
+#define XPOWERS_AXP202_BAT_AVERVOL_H8                   (0x78)
+#define XPOWERS_AXP202_BAT_AVERVOL_L4                   (0x79)
+
+#define XPOWERS_AXP202_BAT_AVERCHGCUR_H8                (0x7A)
+#define XPOWERS_AXP202_BAT_AVERCHGCUR_L4                (0x7B)
+
+#define XPOWERS_AXP202_BAT_AVERCHGCUR_L5                (0x7B)
+#define XPOWERS_AXP202_ACIN_VOL_H8                      (0x56)
+#define XPOWERS_AXP202_ACIN_VOL_L4                      (0x57)
+#define XPOWERS_AXP202_ACIN_CUR_H8                      (0x58)
+#define XPOWERS_AXP202_ACIN_CUR_L4                      (0x59)
+#define XPOWERS_AXP202_VBUS_VOL_H8                      (0x5A)
+#define XPOWERS_AXP202_VBUS_VOL_L4                      (0x5B)
+#define XPOWERS_AXP202_VBUS_CUR_H8                      (0x5C)
+#define XPOWERS_AXP202_VBUS_CUR_L4                      (0x5D)
+#define XPOWERS_AXP202_INTERNAL_TEMP_H8                 (0x5E)
+#define XPOWERS_AXP202_INTERNAL_TEMP_L4                 (0x5F)
+#define XPOWERS_AXP202_TS_IN_H8                         (0x62)
+#define XPOWERS_AXP202_TS_IN_L4                         (0x63)
+#define XPOWERS_AXP202_GPIO0_VOL_ADC_H8                 (0x64)
+#define XPOWERS_AXP202_GPIO0_VOL_ADC_L4                 (0x65)
+#define XPOWERS_AXP202_GPIO1_VOL_ADC_H8                 (0x66)
+#define XPOWERS_AXP202_GPIO1_VOL_ADC_L4                 (0x67)
+
+#define XPOWERS_AXP202_BAT_AVERDISCHGCUR_H8             (0x7C)
+#define XPOWERS_AXP202_BAT_AVERDISCHGCUR_L5             (0x7D)
+#define XPOWERS_AXP202_APS_AVERVOL_H8                   (0x7E)
+#define XPOWERS_AXP202_APS_AVERVOL_L4                   (0x7F)
+#define XPOWERS_AXP202_INT_BAT_CHGCUR_H8                (0xA0)
+#define XPOWERS_AXP202_INT_BAT_CHGCUR_L4                (0xA1)
+#define XPOWERS_AXP202_EXT_BAT_CHGCUR_H8                (0xA2)
+#define XPOWERS_AXP202_EXT_BAT_CHGCUR_L4                (0xA3)
+#define XPOWERS_AXP202_INT_BAT_DISCHGCUR_H8             (0xA4)
+#define XPOWERS_AXP202_INT_BAT_DISCHGCUR_L4             (0xA5)
+#define XPOWERS_AXP202_EXT_BAT_DISCHGCUR_H8             (0xA6)
+#define XPOWERS_AXP202_EXT_BAT_DISCHGCUR_L4             (0xA7)
+#define XPOWERS_AXP202_BAT_CHGCOULOMB3                  (0xB0)
+#define XPOWERS_AXP202_BAT_CHGCOULOMB2                  (0xB1)
+#define XPOWERS_AXP202_BAT_CHGCOULOMB1                  (0xB2)
+#define XPOWERS_AXP202_BAT_CHGCOULOMB0                  (0xB3)
+#define XPOWERS_AXP202_BAT_DISCHGCOULOMB3               (0xB4)
+#define XPOWERS_AXP202_BAT_DISCHGCOULOMB2               (0xB5)
+#define XPOWERS_AXP202_BAT_DISCHGCOULOMB1               (0xB6)
+#define XPOWERS_AXP202_BAT_DISCHGCOULOMB0               (0xB7)
+#define XPOWERS_AXP202_COULOMB_CTL                      (0xB8)
+#define XPOWERS_AXP202_BATT_PERCENTAGE                  (0xB9)
+
+#define XPOWERS_AXP202_BAT_POWERH8                      (0x70)
+#define XPOWERS_AXP202_BAT_POWERM8                      (0x71)
+#define XPOWERS_AXP202_BAT_POWERL8                      (0x72)
+
+#define XPOWERS_AXP202_BATT_VOLTAGE_STEP                (1.1F)
+#define XPOWERS_AXP202_BATT_DISCHARGE_CUR_STEP          (0.5F)
+#define XPOWERS_AXP202_BATT_CHARGE_CUR_STEP             (0.5F)
+#define XPOWERS_AXP202_ACIN_VOLTAGE_STEP                (1.7F)
+#define XPOWERS_AXP202_ACIN_CUR_STEP                    (0.625F)
+#define XPOWERS_AXP202_VBUS_VOLTAGE_STEP                (1.7F)
+#define XPOWERS_AXP202_VBUS_CUR_STEP                    (0.375F)
+#define XPOWERS_AXP202_INTERNAL_TEMP_STEP               (0.1F)
+#define XPOWERS_AXP202_APS_VOLTAGE_STEP                 (1.4F)
+#define XPOWERS_AXP202_TS_PIN_OUT_STEP                  (0.8F)
+
+#define XPOWERS_AXP202_LDO2_VOL_MIN                     (1800u)
+#define XPOWERS_AXP202_LDO2_VOL_MAX                     (3300u)
+#define XPOWERS_AXP202_LDO2_VOL_STEPS                   (100u)
+#define XPOWERS_AXP202_LDO2_VOL_BIT_MASK                (4u)
+
+#define XPOWERS_AXP202_LDO3_VOL_MIN                     (1800u)
+#define XPOWERS_AXP202_LDO3_VOL_MAX                     (3300u)
+#define XPOWERS_AXP202_LDO3_VOL_STEPS                   (100u)
+
+#define XPOWERS_AXP202_DC2_VOL_STEPS                    (25u)
+#define XPOWERS_AXP202_DC2_VOL_MIN                      (700u)
+#define XPOWERS_AXP202_DC2_VOL_MAX                      (3500u)
+
+#define XPOWERS_AXP202_DC3_VOL_STEPS                    (25u)
+#define XPOWERS_AXP202_DC3_VOL_MIN                      (700u)
+#define XPOWERS_AXP202_DC3_VOL_MAX                      (3500u)
+
+#define XPOWERS_AXP202_LDOIO_VOL_STEPS                  (100)
+#define XPOWERS_AXP202_LDOIO_VOL_MIN                    (1800)
+#define XPOWERS_AXP202_LDOIO_VOL_MAX                    (3300)
+
+
+#define XPOWERS_AXP202_SYS_VOL_STEPS                    (100)
+#define XPOWERS_AXP202_VOFF_VOL_MIN                     (2600)
+#define XPOWERS_AXP202_VOFF_VOL_MAX                     (3300)
+
+#define XPOWERS_AXP202_CHG_EXT_CURR_MIN                 (300)
+#define XPOWERS_AXP202_CHG_EXT_CURR_MAX                 (1000)
+#define XPOWERS_AXP202_CHG_EXT_CURR_STEP                (100)
+
+#define XPOWERS_AXP202_INERNAL_TEMP_OFFSET              (144.7)
+
+
+
+
+
+
+
+
+
+
+
+

buildroot/package/axp2101/src/XPowersLib/REG/AXP2101Constants.h

@@ -0,0 +1,243 @@
+#pragma once
+
+#define AXP2101_SLAVE_ADDRESS                            (0x34)
+
+#define XPOWERS_AXP2101_CHIP_ID                          (0x4A)
+#define XPOWERS_AXP2101_CHIP_ID_2                        (0x47)
+
+#define XPOWERS_AXP2101_STATUS1                          (0x00)
+#define XPOWERS_AXP2101_STATUS2                          (0x01)
+#define XPOWERS_AXP2101_IC_TYPE                          (0x03)
+
+
+#define XPOWERS_AXP2101_DATA_BUFFER1                     (0x04)
+#define XPOWERS_AXP2101_DATA_BUFFER2                     (0x05)
+#define XPOWERS_AXP2101_DATA_BUFFER3                     (0x06)
+#define XPOWERS_AXP2101_DATA_BUFFER4                     (0x07)
+#define XPOWERS_AXP2101_DATA_BUFFER_SIZE                 (4u)
+
+#define XPOWERS_AXP2101_COMMON_CONFIG                    (0x10)
+#define XPOWERS_AXP2101_BATFET_CTRL                      (0x12)
+#define XPOWERS_AXP2101_DIE_TEMP_CTRL                    (0x13)
+#define XPOWERS_AXP2101_MIN_SYS_VOL_CTRL                 (0x14)
+#define XPOWERS_AXP2101_INPUT_VOL_LIMIT_CTRL             (0x15)
+#define XPOWERS_AXP2101_INPUT_CUR_LIMIT_CTRL             (0x16)
+#define XPOWERS_AXP2101_RESET_FUEL_GAUGE                 (0x17)
+#define XPOWERS_AXP2101_CHARGE_GAUGE_WDT_CTRL            (0x18)
+
+
+#define XPOWERS_AXP2101_WDT_CTRL                         (0x19)
+#define XPOWERS_AXP2101_LOW_BAT_WARN_SET                 (0x1A)
+
+
+#define XPOWERS_AXP2101_PWRON_STATUS                     (0x20)
+#define XPOWERS_AXP2101_PWROFF_STATUS                    (0x21)
+#define XPOWERS_AXP2101_PWROFF_EN                        (0x22)
+#define XPOWERS_AXP2101_DC_OVP_UVP_CTRL                  (0x23)
+#define XPOWERS_AXP2101_VOFF_SET                         (0x24)
+#define XPOWERS_AXP2101_PWROK_SEQU_CTRL                  (0x25)
+#define XPOWERS_AXP2101_SLEEP_WAKEUP_CTRL                (0x26)
+#define XPOWERS_AXP2101_IRQ_OFF_ON_LEVEL_CTRL            (0x27)
+
+#define XPOWERS_AXP2101_FAST_PWRON_SET0                  (0x28)
+#define XPOWERS_AXP2101_FAST_PWRON_SET1                  (0x29)
+#define XPOWERS_AXP2101_FAST_PWRON_SET2                  (0x2A)
+#define XPOWERS_AXP2101_FAST_PWRON_CTRL                  (0x2B)
+
+#define XPOWERS_AXP2101_ADC_CHANNEL_CTRL                 (0x30)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST0                 (0x34)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST1                 (0x35)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST2                 (0x36)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST3                 (0x37)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST4                 (0x38)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST5                 (0x39)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST6                 (0x3A)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST7                 (0x3B)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST8                 (0x3C)
+#define XPOWERS_AXP2101_ADC_DATA_RELUST9                 (0x3D)
+
+
+//XPOWERS INTERRUPT REGISTER
+#define XPOWERS_AXP2101_INTEN1                           (0x40)
+#define XPOWERS_AXP2101_INTEN2                           (0x41)
+#define XPOWERS_AXP2101_INTEN3                           (0x42)
+
+
+//XPOWERS INTERRUPT STATUS REGISTER
+#define XPOWERS_AXP2101_INTSTS1                          (0x48)
+#define XPOWERS_AXP2101_INTSTS2                          (0x49)
+#define XPOWERS_AXP2101_INTSTS3                          (0x4A)
+#define XPOWERS_AXP2101_INTSTS_CNT                       (3)
+
+#define XPOWERS_AXP2101_TS_PIN_CTRL                      (0x50)
+#define XPOWERS_AXP2101_TS_HYSL2H_SET                    (0x52)
+#define XPOWERS_AXP2101_TS_LYSL2H_SET                    (0x53)
+
+
+#define XPOWERS_AXP2101_VLTF_CHG_SET                     (0x54)
+#define XPOWERS_AXP2101_VHLTF_CHG_SET                    (0x55)
+#define XPOWERS_AXP2101_VLTF_WORK_SET                    (0x56)
+#define XPOWERS_AXP2101_VHLTF_WORK_SET                   (0x57)
+
+
+#define XPOWERS_AXP2101_JIETA_EN_CTRL                    (0x58)
+#define XPOWERS_AXP2101_JIETA_SET0                       (0x59)
+#define XPOWERS_AXP2101_JIETA_SET1                       (0x5A)
+#define XPOWERS_AXP2101_JIETA_SET2                       (0x5B)
+
+
+#define XPOWERS_AXP2101_IPRECHG_SET                      (0x61)
+#define XPOWERS_AXP2101_ICC_CHG_SET                      (0x62)
+#define XPOWERS_AXP2101_ITERM_CHG_SET_CTRL               (0x63)
+
+#define XPOWERS_AXP2101_CV_CHG_VOL_SET                   (0x64)
+
+#define XPOWERS_AXP2101_THE_REGU_THRES_SET               (0x65)
+#define XPOWERS_AXP2101_CHG_TIMEOUT_SET_CTRL             (0x67)
+
+#define XPOWERS_AXP2101_BAT_DET_CTRL                     (0x68)
+#define XPOWERS_AXP2101_CHGLED_SET_CTRL                  (0x69)
+
+#define XPOWERS_AXP2101_BTN_VOL_MIN                      (2600)
+#define XPOWERS_AXP2101_BTN_VOL_MAX                      (3300)
+#define XPOWERS_AXP2101_BTN_VOL_STEPS                    (100)
+
+
+#define XPOWERS_AXP2101_BTN_BAT_CHG_VOL_SET              (0x6A)
+
+
+#define XPOWERS_AXP2101_DC_ONOFF_DVM_CTRL                (0x80)
+#define XPOWERS_AXP2101_DC_FORCE_PWM_CTRL                (0x81)
+#define XPOWERS_AXP2101_DC_VOL0_CTRL                     (0x82)
+#define XPOWERS_AXP2101_DC_VOL1_CTRL                     (0x83)
+#define XPOWERS_AXP2101_DC_VOL2_CTRL                     (0x84)
+#define XPOWERS_AXP2101_DC_VOL3_CTRL                     (0x85)
+#define XPOWERS_AXP2101_DC_VOL4_CTRL                     (0x86)
+
+
+#define XPOWERS_AXP2101_LDO_ONOFF_CTRL0                  (0x90)
+#define XPOWERS_AXP2101_LDO_ONOFF_CTRL1                  (0x91)
+#define XPOWERS_AXP2101_LDO_VOL0_CTRL                    (0x92)
+#define XPOWERS_AXP2101_LDO_VOL1_CTRL                    (0x93)
+#define XPOWERS_AXP2101_LDO_VOL2_CTRL                    (0x94)
+#define XPOWERS_AXP2101_LDO_VOL3_CTRL                    (0x95)
+#define XPOWERS_AXP2101_LDO_VOL4_CTRL                    (0x96)
+#define XPOWERS_AXP2101_LDO_VOL5_CTRL                    (0x97)
+#define XPOWERS_AXP2101_LDO_VOL6_CTRL                    (0x98)
+#define XPOWERS_AXP2101_LDO_VOL7_CTRL                    (0x99)
+#define XPOWERS_AXP2101_LDO_VOL8_CTRL                    (0x9A)
+
+
+#define XPOWERS_AXP2101_BAT_PARAME                       (0xA1)
+#define XPOWERS_AXP2101_FUEL_GAUGE_CTRL                  (0xA2)
+#define XPOWERS_AXP2101_BAT_PERCENT_DATA                 (0xA4)
+
+// DCDC 1~5
+#define XPOWERS_AXP2101_DCDC1_VOL_MIN                    (1500)
+#define XPOWERS_AXP2101_DCDC1_VOL_MAX                    (3400)
+#define XPOWERS_AXP2101_DCDC1_VOL_STEPS                  (100u)
+
+#define XPOWERS_AXP2101_DCDC2_VOL1_MIN                  (500u)
+#define XPOWERS_AXP2101_DCDC2_VOL1_MAX                  (1200u)
+#define XPOWERS_AXP2101_DCDC2_VOL2_MIN                  (1220u)
+#define XPOWERS_AXP2101_DCDC2_VOL2_MAX                  (1540u)
+
+#define XPOWERS_AXP2101_DCDC2_VOL_STEPS1                 (10u)
+#define XPOWERS_AXP2101_DCDC2_VOL_STEPS2                 (20u)
+
+#define XPOWERS_AXP2101_DCDC2_VOL_STEPS1_BASE            (0u)
+#define XPOWERS_AXP2101_DCDC2_VOL_STEPS2_BASE            (71)
+
+
+#define XPOWERS_AXP2101_DCDC3_VOL1_MIN                  (500u)
+#define XPOWERS_AXP2101_DCDC3_VOL1_MAX                  (1200u)
+#define XPOWERS_AXP2101_DCDC3_VOL2_MIN                  (1220u)
+#define XPOWERS_AXP2101_DCDC3_VOL2_MAX                  (1540u)
+#define XPOWERS_AXP2101_DCDC3_VOL3_MIN                  (1600u)
+#define XPOWERS_AXP2101_DCDC3_VOL3_MAX                  (3400u)
+
+#define XPOWERS_AXP2101_DCDC3_VOL_MIN                    (500)
+#define XPOWERS_AXP2101_DCDC3_VOL_MAX                    (3400)
+
+#define XPOWERS_AXP2101_DCDC3_VOL_STEPS1                 (10u)
+#define XPOWERS_AXP2101_DCDC3_VOL_STEPS2                 (20u)
+#define XPOWERS_AXP2101_DCDC3_VOL_STEPS3                 (100u)
+
+#define XPOWERS_AXP2101_DCDC3_VOL_STEPS1_BASE            (0u)
+#define XPOWERS_AXP2101_DCDC3_VOL_STEPS2_BASE            (71)
+#define XPOWERS_AXP2101_DCDC3_VOL_STEPS3_BASE            (88)
+
+
+
+#define XPOWERS_AXP2101_DCDC4_VOL1_MIN                  (500u)
+#define XPOWERS_AXP2101_DCDC4_VOL1_MAX                  (1200u)
+#define XPOWERS_AXP2101_DCDC4_VOL2_MIN                  (1220u)
+#define XPOWERS_AXP2101_DCDC4_VOL2_MAX                  (1840u)
+
+#define XPOWERS_AXP2101_DCDC4_VOL_STEPS1                 (10u)
+#define XPOWERS_AXP2101_DCDC4_VOL_STEPS2                 (20u)
+
+#define XPOWERS_AXP2101_DCDC4_VOL_STEPS1_BASE            (0u)
+#define XPOWERS_AXP2101_DCDC4_VOL_STEPS2_BASE            (71)
+
+
+
+#define XPOWERS_AXP2101_DCDC5_VOL_1200MV                 (1200)
+#define XPOWERS_AXP2101_DCDC5_VOL_VAL                    (0x19)
+#define XPOWERS_AXP2101_DCDC5_VOL_MIN                    (1400)
+#define XPOWERS_AXP2101_DCDC5_VOL_MAX                    (3700)
+#define XPOWERS_AXP2101_DCDC5_VOL_STEPS                  (100u)
+
+#define XPOWERS_AXP2101_VSYS_VOL_THRESHOLD_MIN          (2600)
+#define XPOWERS_AXP2101_VSYS_VOL_THRESHOLD_MAX          (3300)
+#define XPOWERS_AXP2101_VSYS_VOL_THRESHOLD_STEPS        (100)
+
+// ALDO 1~4
+
+#define XPOWERS_AXP2101_ALDO1_VOL_MIN                    (500)
+#define XPOWERS_AXP2101_ALDO1_VOL_MAX                    (3500)
+#define XPOWERS_AXP2101_ALDO1_VOL_STEPS                  (100u)
+
+#define XPOWERS_AXP2101_ALDO2_VOL_MIN                    (500)
+#define XPOWERS_AXP2101_ALDO2_VOL_MAX                    (3500)
+#define XPOWERS_AXP2101_ALDO2_VOL_STEPS                  (100u)
+
+
+#define XPOWERS_AXP2101_ALDO3_VOL_MIN                    (500)
+#define XPOWERS_AXP2101_ALDO3_VOL_MAX                    (3500)
+#define XPOWERS_AXP2101_ALDO3_VOL_STEPS                  (100u)
+
+
+#define XPOWERS_AXP2101_ALDO4_VOL_MIN                    (500)
+#define XPOWERS_AXP2101_ALDO4_VOL_MAX                    (3500)
+#define XPOWERS_AXP2101_ALDO4_VOL_STEPS                  (100u)
+
+// BLDO 1~2
+
+#define XPOWERS_AXP2101_BLDO1_VOL_MIN                    (500)
+#define XPOWERS_AXP2101_BLDO1_VOL_MAX                    (3500)
+#define XPOWERS_AXP2101_BLDO1_VOL_STEPS                  (100u)
+
+#define XPOWERS_AXP2101_BLDO2_VOL_MIN                    (500)
+#define XPOWERS_AXP2101_BLDO2_VOL_MAX                    (3500)
+#define XPOWERS_AXP2101_BLDO2_VOL_STEPS                  (100u)
+
+// CPUSLDO
+
+#define XPOWERS_AXP2101_CPUSLDO_VOL_MIN                  (500)
+#define XPOWERS_AXP2101_CPUSLDO_VOL_MAX                  (1400)
+#define XPOWERS_AXP2101_CPUSLDO_VOL_STEPS                (50)
+
+
+// DLDO 1~2
+#define XPOWERS_AXP2101_DLDO1_VOL_MIN                  (500)
+#define XPOWERS_AXP2101_DLDO1_VOL_MAX                  (3400)
+#define XPOWERS_AXP2101_DLDO1_VOL_STEPS                (100u)
+
+#define XPOWERS_AXP2101_DLDO2_VOL_MIN                  (500)
+#define XPOWERS_AXP2101_DLDO2_VOL_MAX                  (3400)
+#define XPOWERS_AXP2101_DLDO2_VOL_STEPS                (100u)
+
+
+#define XPOWERS_AXP2101_CONVERSION(raw)                 (22.0 + (7274 - raw) / 20.0)
+

buildroot/package/axp2101/src/XPowersLib/REG/AXP216Constants.h

@@ -0,0 +1,95 @@
+#pragma once
+
+#define AXP216_SLAVE_ADDRESS                            (0x34)
+
+#define XPOWERS_AXP216_CHIP_ID                          (0x41)
+
+//CONTROL REGISTER
+#define XPOWERS_AXP216_STATUS                           (0x00)
+#define XPOWERS_AXP216_MODE_CHGSTATUS                   (0x01)
+#define XPOWERS_AXP216_DATA_BUFFER1                     (0x04)
+#define XPOWERS_AXP216_DATA_BUFFER2                     (0x05)
+#define XPOWERS_AXP216_DATA_BUFFER3                     (0x06)
+#define XPOWERS_AXP216_DATA_BUFFER4                     (0x07)
+#define XPOWERS_AXP216_DATA_BUFFER5                     (0x08)
+#define XPOWERS_AXP216_DATA_BUFFER6                     (0x09)
+#define XPOWERS_AXP216_DATA_BUFFER7                     (0x0A)
+#define XPOWERS_AXP216_DATA_BUFFER8                     (0x0B)
+#define XPOWERS_AXP216_DATA_BUFFER9                     (0x0C)
+#define XPOWERS_AXP216_DATA_BUFFERA                     (0x0D)
+#define XPOWERS_AXP216_DATA_BUFFERB                     (0x0E)
+#define XPOWERS_AXP216_DATA_BUFFERC                     (0x0F)
+
+#define XPOWERS_AXP216_IC_TYPE                          (0x03)
+
+#define XPOWERS_AXP216_DC12345_ALDO12_CTL               (0x10)
+#define XPOWERS_AXP216_LDO123_CTL                       (0x12)
+#define XPOWERS_AXP216_OUTPUT_CTL                       (0x13)
+#define XPOWERS_AXP216_ELDO1_VCTL                       (0x19)
+#define XPOWERS_AXP216_ELDO2_VCTL                       (0x1A)
+#define XPOWERS_AXP216_DCDC1_VCTL                       (0x21)
+#define XPOWERS_AXP216_DCDC2_VCTL                       (0x22)
+#define XPOWERS_AXP216_DCDC3_VCTL                       (0x23)
+
+#define XPOWERS_AXP216_DCDC4_VCTL                       (0x24)
+#define XPOWERS_AXP216_DCDC5_VCTL                       (0x25)
+#define XPOWERS_AXP216_DCDC23_VOLX                      (0x27)
+#define XPOWERS_AXP216_ALDO1_VCTL                       (0x28)
+#define XPOWERS_AXP216_ALDO2_VCTL                       (0x29)
+#define XPOWERS_AXP216_ALDO3_VCTL                       (0x2A)
+#define XPOWERS_AXP216_VBUS_IPSOUT                      (0x30)
+#define XPOWERS_AXP216_VOFF_SET                         (0x31)
+#define XPOWERS_AXP216_OFF_CTL                          (0x32)
+#define XPOWERS_AXP216_CHARGE1                          (0x33)
+#define XPOWERS_AXP216_CHARGE2                          (0x34)
+#define XPOWERS_AXP216_CHARGE3                          (0x35)
+#define XPOWERS_AXP216_PEK_SET                          (0x36)
+#define XPOWERS_AXP216_OFFLEVEL                         (0x37)
+#define XPOWERS_AXP216_VLTF_CHGSET                      (0x38)
+#define XPOWERS_AXP216_VHTF_CHGSET                      (0x39)
+#define XPOWERS_AXP216_DCDC_FREQ                        (0x3B)
+#define XPOWERS_AXP216_TLTF_DISCHGSET                   (0x3C)
+#define XPOWERS_AXP216_THTF_DISCHGSET                   (0x3D)
+#define XPOWERS_AXP216_DCDC_MODESET                     (0x80)
+#define XPOWERS_AXP216_ADC_CTL                          (0x82)
+#define XPOWERS_AXP216_ADC_SPEED                        (0x84)
+#define XPOWERS_AXP216_TS_ADC                           (0x85)
+#define XPOWERS_AXP216_TIMER_CTL                        (0x8A)
+#define XPOWERS_AXP216_HOTOVER_CTL                      (0x8F)
+
+//GPIO REGISTER
+#define XPOWERS_AXP216_GPIO1_CTL                        (0x92)
+#define XPOWERS_AXP216_GPIO1_LDO_CTL                    (0x93)
+#define XPOWERS_AXP216_GPIO01_STATUS                    (0x94)
+#define XPOWERS_AXP216_GPIO1_PULLDOWN_CTL               (0x97)
+
+//XPOWERS INTERRUPT REGISTER
+#define XPOWERS_AXP216_INTEN1                           (0x40)
+#define XPOWERS_AXP216_INTEN2                           (0x41)
+#define XPOWERS_AXP216_INTEN3                           (0x42)
+#define XPOWERS_AXP216_INTEN4                           (0x43)
+#define XPOWERS_AXP216_INTEN5                           (0x44)
+
+//XPOWERS INTERRUPT STATUS REGISTER
+#define XPOWERS_AXP216_INTSTS1                          (0x48)
+#define XPOWERS_AXP216_INTSTS2                          (0x49)
+#define XPOWERS_AXP216_INTSTS3                          (0x4A)
+#define XPOWERS_AXP216_INTSTS4                          (0x4B)
+#define XPOWERS_AXP216_INTSTS5                          (0x4C)
+
+//XPOWERS ADC DATA REGISTER
+#define XPOWERS_AXP216_INTERNAL_TEMP_H8                 (0x56)
+#define XPOWERS_AXP216_INTERNAL_TEMP_L4                 (0x57)
+#define XPOWERS_AXP216_TS_IN_H8                         (0x58)
+#define XPOWERS_AXP216_TS_IN_L4                         (0x59)
+#define XPOWERS_AXP216_BAT_VOLTAGE_H8                   (0x78)
+#define XPOWERS_AXP216_BAT_VOLTAGE_L4                   (0x79)
+#define XPOWERS_AXP216_BAT_CHGCURCUR_H8                 (0x7A)
+#define XPOWERS_AXP216_BAT_CHGCURCUR_L4                 (0x7B)
+#define XPOWERS_AXP216_BAT_DISCHGCUR_H8                 (0x7C)
+#define XPOWERS_AXP216_BAT_DISCHGCUR_L4                 (0x7D)
+#define XPOWERS_AXP216_FUEL_GAUGE_CTRL                  (0xB8)
+#define XPOWERS_AXP216_FUEL_GAUGE_REULST                (0xB9)
+#define XPOWERS_AXP216_BAT_CAPACITY_0                   (0xE0)
+#define XPOWERS_AXP216_BAT_CAPACITY_1                   (0xE1)
+#define XPOWERS_AXP216_BAT_LOW_WARNING_CTRL             (0xE6)

buildroot/package/axp2101/src/XPowersLib/REG/HUSB238Constants.h

@@ -0,0 +1,45 @@
+/**
+ *
+ * @license MIT License
+ *
+ * Copyright (c) 2022 lewis he
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * @file      HUSB238Constants.h
+ * @author    Lewis He (lewishe@outlook.com)
+ * @date      2024-07-24
+ *
+ */
+#pragma once
+
+#define HUSB238_SLAVE_ADDRESS                                    (0x8)
+
+#define HUSB238_PD_STATUS0                                       (0x0)
+#define HUSB238_PD_STATUS1                                       (0x1)
+#define HUSB238_SRC_PDO_5V                                       (0x2)
+#define HUSB238_SRC_PDO_9V                                       (0x3)
+#define HUSB238_SRC_PDO_12V                                      (0x4)
+#define HUSB238_SRC_PDO_15V                                      (0x5)
+#define HUSB238_SRC_PDO_18V                                      (0x6)
+#define HUSB238_SRC_PDO_20V                                      (0x7)
+#define HUSB238_SRC_PDO                                          (0x8)
+#define HUSB238_GO_COMMAND                                       (0x9)
+
+

buildroot/package/axp2101/src/XPowersLib/REG/SY6970Constants.h

@@ -0,0 +1,126 @@
+/**
+ *
+ * @license MIT License
+ *
+ * Copyright (c) 2022 lewis he
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * @file      SY6970Constants.h
+ * @author    Lewis He (lewishe@outlook.com)
+ * @date      2023-07-20
+ *
+ */
+#pragma once
+
+#define SY6970_SLAVE_ADDRESS                                    (0x6A)
+// https://www.ti.com/product/BQ25896
+#define BQ25896_SLAVE_ADDRESS                                   (0x6B)
+// https://www.sg-micro.com/cnproduct/SGM41511
+#define SGM41511_SLAVE_ADDRESS                                  (0x6B)
+
+#define SY6970_DEV_REV                                          (0x00)
+#define BQ25896_DEV_REV                                         (0x02)
+
+#define POWERS_SY6970_REG_00H                                   (0x00)
+#define POWERS_SY6970_REG_01H                                   (0x01)
+#define POWERS_SY6970_REG_02H                                   (0x02)
+#define POWERS_SY6970_REG_03H                                   (0x03)
+#define POWERS_SY6970_REG_04H                                   (0x04)
+#define POWERS_SY6970_REG_05H                                   (0x05)
+#define POWERS_SY6970_REG_06H                                   (0x06)
+#define POWERS_SY6970_REG_07H                                   (0x07)
+#define POWERS_SY6970_REG_08H                                   (0x08)
+#define POWERS_SY6970_REG_09H                                   (0x09)
+#define POWERS_SY6970_REG_0AH                                   (0x0A)
+// Read only STATUS REG
+#define POWERS_SY6970_REG_0BH                                   (0x0B)
+// Read only CHARGE IRQ REG
+#define POWERS_SY6970_REG_0CH                                   (0x0C)
+// Absolute VINDPM Threshold
+#define POWERS_SY6970_REG_0DH                                   (0x0D)
+// Read only BATTERY VOLTAGE
+#define POWERS_SY6970_REG_0EH                                   (0x0E)
+// Read only SYSTEM VOLTAGE
+#define POWERS_SY6970_REG_0FH                                   (0x0F)
+// Read only NTC PERCENTAGE
+#define POWERS_SY6970_REG_10H                                   (0x10)
+// Read only VBUS VOLTAGE
+#define POWERS_SY6970_REG_11H                                   (0x11)
+// Read only CHARGE CURRENT
+#define POWERS_SY6970_REG_12H                                   (0x12)
+// Read only VINDPM/IINDPM STATUS/CURR LIMIT SETTING 
+#define POWERS_SY6970_REG_13H                                   (0x13)
+// RESET REG
+#define POWERS_SY6970_REG_14H                                   (0x14)
+
+#define POWERS_SY6970_VBUS_MASK_VAL(val)                        (val & 0x7F)
+#define POWERS_SY6970_VBAT_MASK_VAL(val)                        (val & 0x7F)
+#define POWERS_SY6970_VSYS_MASK_VAL(val)                        (val & 0x7F)
+#define POWERS_SY6970_NTC_MASK_VAL(val)                         (val & 0x7F)
+
+#define POWERS_SY6970_VBUS_BASE_VAL                             (2600)
+#define POWERS_SY6970_VBAT_BASE_VAL                             (2304)
+#define POWERS_SY6970_VSYS_BASE_VAL                             (2304)
+#define POWERS_SY6970_NTC_BASE_VAL                              (21)
+
+#define POWERS_SY6970_VBUS_VOL_STEP                             (100)
+#define POWERS_SY6970_VBAT_VOL_STEP                             (20)
+#define POWERS_SY6970_VSYS_VOL_STEP                             (20)
+#define POWERS_SY6970_NTC_VOL_STEP                              (0.465)
+#define POWERS_SY6970_CHG_STEP_VAL                              (50)
+
+#define POWERS_SY6970_PRE_CHG_CUR_BASE                          (64)
+#define POWERS_SY6970_FAST_CHG_CUR_STEP                         (64)
+#define POWERS_SY6970_PRE_CHG_CUR_STEP                          (64)
+
+#define POWERS_FAST_CHG_CURRENT_MIN                             (0)
+#define POWERS_FAST_CHG_CURRENT_MAX                             (5056)
+
+#define POWERS_PRE_CHG_CURRENT_MIN                              (64)
+#define POWERS_PRE_CHG_CURRENT_MAX                              (1024)
+
+#define POWERS_SY6970_CHG_VOL_BASE                              (3840)
+#define POWERS_SY6970_CHG_VOL_STEP                              (16)
+#define POWERS_FAST_CHG_VOL_MIN                                 (3840)
+#define POWERS_FAST_CHG_VOL_MAX                                 (4608)
+
+#define POWERS_SY6970_SYS_VOL_STEPS                             (100)
+#define POWERS_SY6970_SYS_VOFF_VOL_MIN                          (3000)
+#define POWERS_SY6970_SYS_VOFF_VOL_MAX                          (3700)
+
+#define POWERS_SY6970_IN_CURRENT_STEP                           (50)
+#define POWERS_SY6970_IN_CURRENT_MIN                            (100)
+#define POWERS_SY6970_IN_CURRENT_MAX                            (3250)
+
+#define POWERS_SY6970_BOOTS_VOL_BASE                            (4550)
+#define POWERS_SY6970_BOOTS_VOL_STEP                            (64)
+#define POWERS_SY6970_BOOST_VOL_MIN                             (4550)
+#define POWERS_SY6970_BOOST_VOL_MAX                             (5510)
+
+#define POWERS_SY6970_IRQ_WTD_FAULT(x)                          (bool)(( x & 0xFF ) >> 7)
+#define POWERS_SY6970_IRQ_BOOST_FAULT(x)                        (bool)(( x & 0xFF ) >> 6)
+#define POWERS_SY6970_IRQ_CHG_FAULT(x)                          (bool)(( x & 0xFF ) >> 5)
+#define POWERS_SY6970_IRQ_BAT_FAULT(x)                          (bool)(( x & 0xFF ) >> 4)
+#define POWERS_SY6970_IRQ_NTC_FAULT(x)                          (bool)(( x & 0xFF ) & 0x03)
+
+#define POWERS_SY6970_VINDPM_VOL_BASE                           (4550)
+#define POWERS_SY6970_VINDPM_VOL_STEPS                          (100)
+#define POWERS_SY6970_VINDPM_VOL_MIN                            (3900)
+#define POWERS_SY6970_VINDPM_VOL_MAX                            (15300)

buildroot/package/axp2101/src/XPowersLib/XPowersCommon.tpp

@@ -0,0 +1,512 @@
+/**
+ *
+ * @license MIT License
+ *
+ * Copyright (c) 2022 lewis he
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * @file      XPowersCommon.h
+ * @author    Lewis He (lewishe@outlook.com)
+ * @date      2022-05-07
+ *
+ */
+
+
+#pragma once
+
+#include <stdint.h>
+
+#if defined(ARDUINO)
+#include <Wire.h>
+#elif defined(ESP_PLATFORM)
+#include "esp_log.h"
+#include "esp_err.h"
+#include <cstring>
+#include "esp_idf_version.h"
+#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5,0,0)) && defined(CONFIG_XPOWERS_ESP_IDF_NEW_API)
+#include "driver/i2c_master.h"
+#else
+#include "driver/i2c.h"
+#define XPOWERSLIB_I2C_MASTER_TX_BUF_DISABLE   0                          /*!< I2C master doesn't need buffer */
+#define XPOWERSLIB_I2C_MASTER_RX_BUF_DISABLE   0                          /*!< I2C master doesn't need buffer */
+#define XPOWERSLIB_I2C_MASTER_TIMEOUT_MS       1000
+#endif //ESP_IDF_VERSION
+
+
+#endif //ESP_PLATFORM
+
+#define XPOWERSLIB_I2C_MASTER_SPEED            400000
+
+
+#ifdef _BV
+#undef _BV
+#endif
+#define _BV(b)                          (1ULL << (uint64_t)(b))
+
+
+#ifndef constrain
+#define constrain(amt,low,high) ((amt)<(low)?(low):((amt)>(high)?(high):(amt)))
+#endif
+
+
+
+#define XPOWERS_ATTR_NOT_IMPLEMENTED    __attribute__((error("Not implemented")))
+#define IS_BIT_SET(val,mask)            (((val)&(mask)) == (mask))
+
+#if !defined(ARDUINO)
+#ifdef linux
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+#define log_e(__info,...)          printf("error :"  __info,##__VA_ARGS__)
+#define log_i(__info,...)          printf("info  :"  __info,##__VA_ARGS__)
+#define log_d(__info,...)          printf("debug :"  __info,##__VA_ARGS__)
+#else
+#define log_e(...)
+#define log_i(...)
+#define log_d(...)
+#endif
+
+#define LOW                 0x0
+#define HIGH                0x1
+
+//GPIO FUNCTIONS
+#define INPUT               0x01
+#define OUTPUT              0x03
+#define PULLUP              0x04
+#define INPUT_PULLUP        0x05
+#define PULLDOWN            0x08
+#define INPUT_PULLDOWN      0x09
+
+#define RISING              0x01
+#define FALLING             0x02
+#endif
+
+#ifndef ESP32
+#ifdef LOG_FILE_LINE_INFO
+#undef LOG_FILE_LINE_INFO
+#endif
+#define LOG_FILE_LINE_INFO __FILE__, __LINE__
+#ifndef log_e
+#define log_e(fmt, ...)     Serial.printf("[E][%s:%d] " fmt "\n", LOG_FILE_LINE_INFO, ##__VA_ARGS__)
+#endif
+#ifndef log_i
+#define log_i(fmt, ...)     Serial.printf("[I][%s:%d] " fmt "\n", LOG_FILE_LINE_INFO, ##__VA_ARGS__)
+#endif
+#ifndef log_d
+#define log_d(fmt, ...)     Serial.printf("[D][%s:%d] " fmt "\n", LOG_FILE_LINE_INFO, ##__VA_ARGS__)
+#endif
+#endif
+
+
+#if defined(NRF52840_XXAA) || defined(NRF52832_XXAA)
+#ifndef SDA
+#define SDA     (0xFF)
+#endif
+
+#ifndef SCL
+#define SCL     (0xFF)
+#endif
+#endif
+
+
+typedef int (*iic_fptr_t)(uint8_t devAddr, uint8_t regAddr, uint8_t *data, uint8_t len);
+
+template <class chipType>
+class XPowersCommon
+{
+
+public:
+
+#if defined(ARDUINO)
+    bool begin(TwoWire &w, uint8_t addr, int sda, int scl)
+    {
+        if (__has_init)return thisChip().initImpl();
+        __has_init = true;
+        __sda = sda;
+        __scl = scl;
+        __wire = &w;
+
+#if defined(NRF52840_XXAA) || defined(NRF52832_XXAA)
+        if (__sda != 0xFF && __scl != 0xFF) {
+            __wire->setPins(__sda, __scl);
+        }
+        __wire->begin();
+#elif defined(ARDUINO_ARCH_RP2040) || defined(ARDUINO_ARCH_STM32)
+        if (__sda != 0xFF && __scl != 0xFF) {
+            __wire->end();
+            __wire->setSDA(__sda);
+            __wire->setSCL(__scl);
+        }
+        __wire->begin();
+#elif defined(ARDUINO_ARCH_ESP32)
+        __wire->begin(__sda, __scl);
+#else
+        __wire->begin();
+#endif
+        __addr = addr;
+        return thisChip().initImpl();
+    }
+#elif defined(ESP_PLATFORM)
+
+
+#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5,0,0)) && defined(CONFIG_XPOWERS_ESP_IDF_NEW_API)
+
+    // * Using the new API of esp-idf 5.x, you need to pass the I2C BUS handle,
+    // * which is useful when the bus shares multiple devices.
+    bool begin(i2c_master_bus_handle_t i2c_dev_bus_handle, uint8_t addr)
+    {
+        log_i("Using ESP-IDF Driver interface.");
+        if (i2c_dev_bus_handle == NULL) return false;
+        if (__has_init)return thisChip().initImpl();
+
+        thisReadRegCallback = NULL;
+        thisWriteRegCallback = NULL;
+
+        /*
+            i2c_master_bus_config_t i2c_bus_config;
+            memset(&i2c_bus_config, 0, sizeof(i2c_bus_config));
+            i2c_bus_config.clk_source = I2C_CLK_SRC_DEFAULT;
+            i2c_bus_config.i2c_port = port_num;
+            i2c_bus_config.scl_io_num = (gpio_num_t)__scl;
+            i2c_bus_config.sda_io_num = (gpio_num_t)__sda;
+            i2c_bus_config.glitch_ignore_cnt = 7;
+
+            i2c_new_master_bus(&i2c_bus_config, &bus_handle);
+        */
+
+        bus_handle = i2c_dev_bus_handle;
+
+        i2c_device_config_t i2c_dev_conf = {
+            .dev_addr_length = I2C_ADDR_BIT_LEN_7,
+            .device_address = addr,
+            .scl_speed_hz = XPOWERSLIB_I2C_MASTER_SPEED,
+#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5,3,0))
+#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5,4,0))
+            // New fields since esp-idf-v5.3-beta1
+            .scl_wait_us = 0,
+#endif
+            .flags = {
+                . disable_ack_check = 0
+            }
+#endif
+        };
+
+        if (ESP_OK != i2c_master_bus_add_device(bus_handle,
+                                                &i2c_dev_conf,
+                                                &__i2c_device)) {
+            return false;
+        }
+
+        __has_init = thisChip().initImpl();
+
+        if (!__has_init) {
+            // Initialization failed, delete device
+            i2c_master_bus_rm_device(__i2c_device);
+        }
+        return __has_init;
+    }
+
+
+#else //ESP 4.X
+
+
+    bool begin(i2c_port_t port_num, uint8_t addr, int sda, int scl)
+    {
+        __i2c_num = port_num;
+        log_i("Using ESP-IDF Driver interface.");
+        if (__has_init)return thisChip().initImpl();
+        __sda = sda;
+        __scl = scl;
+        __addr = addr;
+        thisReadRegCallback = NULL;
+        thisWriteRegCallback = NULL;
+
+        i2c_config_t i2c_conf;
+        memset(&i2c_conf, 0, sizeof(i2c_conf));
+        i2c_conf.mode = I2C_MODE_MASTER;
+        i2c_conf.sda_io_num = sda;
+        i2c_conf.scl_io_num = scl;
+        i2c_conf.sda_pullup_en = GPIO_PULLUP_ENABLE;
+        i2c_conf.scl_pullup_en = GPIO_PULLUP_ENABLE;
+        i2c_conf.master.clk_speed = XPOWERSLIB_I2C_MASTER_SPEED;
+
+        /**
+         * @brief Without checking whether the initialization is successful,
+         * I2C may be initialized externally,
+         * so just make sure there is an initialization here.
+         */
+        i2c_param_config(__i2c_num, &i2c_conf);
+        i2c_driver_install(__i2c_num,
+                           i2c_conf.mode,
+                           XPOWERSLIB_I2C_MASTER_RX_BUF_DISABLE,
+                           XPOWERSLIB_I2C_MASTER_TX_BUF_DISABLE, 0);
+        __has_init = thisChip().initImpl();
+        return __has_init;
+    }
+#endif //ESP 5.X
+#endif //ESP_PLATFORM
+
+    bool begin(uint8_t addr, iic_fptr_t readRegCallback, iic_fptr_t writeRegCallback)
+    {
+        if (__has_init)return thisChip().initImpl();
+        __has_init = true;
+        thisReadRegCallback = readRegCallback;
+        thisWriteRegCallback = writeRegCallback;
+        __addr = addr;
+        return thisChip().initImpl();
+    }
+
+    int readRegister(uint8_t reg)
+    {
+        uint8_t val = 0;
+        return readRegister(reg, &val, 1) == -1 ? -1 : val;
+    }
+
+    int writeRegister(uint8_t reg, uint8_t val)
+    {
+        return writeRegister(reg, &val, 1);
+    }
+
+    int readRegister(uint8_t reg, uint8_t *buf, uint8_t length)
+    {
+        if (thisReadRegCallback) {
+            return thisReadRegCallback(__addr, reg, buf, length);
+        }
+#if defined(ARDUINO)
+        if (__wire) {
+            __wire->beginTransmission(__addr);
+            __wire->write(reg);
+            if (__wire->endTransmission() != 0) {
+                return -1;
+            }
+            __wire->requestFrom(__addr, length);
+            return __wire->readBytes(buf, length) == length ? 0 : -1;
+        }
+#elif defined(ESP_PLATFORM)
+
+#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5,0,0)) && defined(CONFIG_XPOWERS_ESP_IDF_NEW_API)
+        if (ESP_OK == i2c_master_transmit_receive(
+                    __i2c_device,
+                    (const uint8_t *)&reg,
+                    1,
+                    buf,
+                    length,
+                    -1)) {
+            return 0;
+        }
+#else //ESP_IDF_VERSION
+        if (ESP_OK == i2c_master_write_read_device(__i2c_num,
+                __addr,
+                (uint8_t *)&reg,
+                1,
+                buf,
+                length,
+                XPOWERSLIB_I2C_MASTER_TIMEOUT_MS / portTICK_PERIOD_MS)) {
+            return 0;
+        }
+#endif //ESP_IDF_VERSION
+#endif //ESP_PLATFORM
+        return -1;
+    }
+
+    int writeRegister(uint8_t reg, uint8_t *buf, uint8_t length)
+    {
+        if (thisWriteRegCallback) {
+            return thisWriteRegCallback(__addr, reg, buf, length);
+        }
+#if defined(ARDUINO)
+        if (__wire) {
+            __wire->beginTransmission(__addr);
+            __wire->write(reg);
+            __wire->write(buf, length);
+            return (__wire->endTransmission() == 0) ? 0 : -1;
+        }
+        return -1;
+#elif defined(ESP_PLATFORM)
+        uint8_t *write_buffer = (uint8_t *)malloc(sizeof(uint8_t) * (length + 1));
+        if (!write_buffer) {
+            return -1;
+        }
+        write_buffer[0] = reg;
+        memcpy(write_buffer + 1, buf, length);
+
+
+#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5,0,0)) && defined(CONFIG_XPOWERS_ESP_IDF_NEW_API)
+        if (ESP_OK != i2c_master_transmit(
+                    __i2c_device,
+                    write_buffer,
+                    length + 1,
+                    -1)) {
+            free(write_buffer);
+            return -1;
+        }
+#else //ESP_IDF_VERSION
+        if (ESP_OK != i2c_master_write_to_device(__i2c_num,
+                __addr,
+                write_buffer,
+                length + 1,
+                XPOWERSLIB_I2C_MASTER_TIMEOUT_MS / portTICK_PERIOD_MS)) {
+            free(write_buffer);
+            return -1;
+        }
+#endif //ESP_IDF_VERSION
+        free(write_buffer);
+        return 0;
+#endif //ESP_PLATFORM
+        return 0;
+    }
+
+
+    bool inline clrRegisterBit(uint8_t registers, uint8_t bit)
+    {
+        int val = readRegister(registers);
+        if (val == -1) {
+            return false;
+        }
+        return  writeRegister(registers, (val & (~_BV(bit)))) == 0;
+    }
+
+    bool inline setRegisterBit(uint8_t registers, uint8_t bit)
+    {
+        int val = readRegister(registers);
+        if (val == -1) {
+            return false;
+        }
+        return  writeRegister(registers, (val | (_BV(bit)))) == 0;
+    }
+
+    bool inline getRegisterBit(uint8_t registers, uint8_t bit)
+    {
+        int val = readRegister(registers);
+        if (val == -1) {
+            return false;
+        }
+        return val & _BV(bit);
+    }
+
+    uint16_t inline readRegisterH8L4(uint8_t highReg, uint8_t lowReg)
+    {
+        int h8 = readRegister(highReg);
+        int l4 = readRegister(lowReg);
+        if (h8 == -1 || l4 == -1)return 0;
+        return (h8 << 4) | (l4 & 0x0F);
+    }
+
+    uint16_t inline readRegisterH8L5(uint8_t highReg, uint8_t lowReg)
+    {
+        int h8 = readRegister(highReg);
+        int l5 = readRegister(lowReg);
+        if (h8 == -1 || l5 == -1)return 0;
+        return (h8 << 5) | (l5 & 0x1F);
+    }
+
+    uint16_t inline readRegisterH6L8(uint8_t highReg, uint8_t lowReg)
+    {
+        int h6 = readRegister(highReg);
+        int l8 = readRegister(lowReg);
+        if (h6 == -1 || l8 == -1)return 0;
+        return ((h6 & 0x3F) << 8) | l8;
+    }
+
+    uint16_t inline readRegisterH5L8(uint8_t highReg, uint8_t lowReg)
+    {
+        int h5 = readRegister(highReg);
+        int l8 = readRegister(lowReg);
+        if (h5 == -1 || l8 == -1)return 0;
+        return ((h5 & 0x1F) << 8) | l8;
+    }
+
+    /*
+     * CRTP Helper
+     */
+protected:
+
+    bool begin()
+    {
+#if defined(ARDUINO)
+        if (__has_init) return thisChip().initImpl();
+        __has_init = true;
+        if (__wire) {
+            log_i("SDA:%d SCL:%d", __sda, __scl);
+#if defined(NRF52840_XXAA) || defined(NRF52832_XXAA)
+            if (__sda != 0xFF && __scl != 0xFF) {
+                __wire->setPins(__sda, __scl);
+            }
+            __wire->begin();
+#elif defined(ARDUINO_ARCH_RP2040) || defined(ARDUINO_ARCH_STM32)
+            if (__sda != 0xFF && __scl != 0xFF) {
+                __wire->end();
+                __wire->setSDA(__sda);
+                __wire->setSCL(__scl);
+            }
+            __wire->begin();
+#elif defined(ARDUINO_ARCH_ESP32)
+            __wire->begin(__sda, __scl);
+#else
+            __wire->begin();
+#endif
+        }
+#endif  /*ARDUINO*/
+        return thisChip().initImpl();
+    }
+
+    void end()
+    {
+#if defined(ARDUINO)
+        if (__wire) {
+#if defined(ESP_IDF_VERSION)
+#if ESP_IDF_VERSION > ESP_IDF_VERSION_VAL(4,4,0)
+            __wire->end();
+#endif  /*ESP_IDF_VERSION*/
+#endif  /*ESP_IDF_VERSION*/
+        }
+#endif /*ARDUINO*/
+    }
+
+
+    inline const chipType &thisChip() const
+    {
+        return static_cast<const chipType &>(*this);
+    }
+
+    inline chipType &thisChip()
+    {
+        return static_cast<chipType &>(*this);
+    }
+
+protected:
+    bool        __has_init              = false;
+#if defined(ARDUINO)
+    TwoWire     *__wire                 = NULL;
+#elif defined(ESP_PLATFORM)
+    i2c_port_t  __i2c_num;
+#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5,0,0)) && defined(CONFIG_XPOWERS_ESP_IDF_NEW_API)
+    i2c_master_bus_handle_t  bus_handle;
+    i2c_master_dev_handle_t  __i2c_device;
+#endif //ESP_IDF_VERSION
+
+#endif //ESP_PLATFORM
+    int         __sda                   = -1;
+    int         __scl                   = -1;
+    uint8_t     __addr                  = 0xFF;
+    iic_fptr_t  thisReadRegCallback     = NULL;
+    iic_fptr_t  thisWriteRegCallback    = NULL;
+};

buildroot/package/axp2101/src/XPowersLib/XPowersLib.h

@@ -0,0 +1,37 @@
+/**
+ * @file      XPowersLib.h
+ * @author    Lewis He (lewishe@outlook.com)
+ * @license   MIT
+ * @copyright Copyright (c) 2022
+ * @date      2022-05-07
+ *
+ */
+
+#ifndef __XPOWERSLIB_H__
+#define __XPOWERSLIB_H__
+
+
+#if defined(XPOWERS_CHIP_AXP192)
+#include "XPowersAXP192.tpp"
+typedef XPowersAXP192 XPowersPMU;
+#elif defined(XPOWERS_CHIP_AXP202)
+#include "XPowersAXP202.tpp"
+typedef XPowersAXP202 XPowersPMU;
+#elif defined(XPOWERS_CHIP_AXP2101)
+#include "XPowersAXP2101.tpp"
+typedef XPowersAXP2101 XPowersPMU;
+#else
+#include "XPowersAXP192.tpp"
+#include "XPowersAXP202.tpp"
+#include "XPowersAXP2101.tpp"
+#include "PowersSY6970.tpp"
+#include "PowerDeliveryHUSB238.hpp"
+#endif
+
+
+
+
+
+
+
+#endif /*__XPOWERSLIB_H__*/

buildroot/package/axp2101/src/XPowersLib/XPowersLibInterface.cpp

@@ -0,0 +1,173 @@
+/**
+ *
+ * @license MIT License
+ *
+ * Copyright (c) 2022 lewis he
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * @file      XPowersLibInterface.cpp
+ * @author    Lewis He (lewishe@outlook.com)
+ * @date      2022-08-28
+ *
+ */
+#if defined(ARDUINO)
+#include <Arduino.h>
+#endif
+
+#include "XPowersLibInterface.hpp"
+
+
+bool XPowersLibInterface::isChannelAvailable(uint8_t channel)
+{
+    if (__chipModel == XPOWERS_AXP192) {
+        switch (channel) {
+        case XPOWERS_DCDC1:
+        case XPOWERS_DCDC2:
+        case XPOWERS_DCDC3:
+        case XPOWERS_LDO2:
+        case XPOWERS_LDO3:
+        case XPOWERS_LDOIO:
+            return true;
+        default:
+            return false;
+        }
+    } else if (__chipModel == XPOWERS_AXP202) {
+
+        switch (channel) {
+        case XPOWERS_DCDC2:
+        case XPOWERS_DCDC3:
+        case XPOWERS_LDO2:
+        case XPOWERS_LDO3:
+        case XPOWERS_LDO4:
+        case XPOWERS_LDO5:
+            return true;
+        default:
+            return false;
+        }
+
+    } else if (__chipModel == XPOWERS_AXP2101) {
+        switch (channel) {
+        case XPOWERS_DCDC1:
+        case XPOWERS_DCDC2:
+        case XPOWERS_DCDC3:
+        case XPOWERS_DCDC4:
+        case XPOWERS_DCDC5:
+        case XPOWERS_ALDO1:
+        case XPOWERS_ALDO2:
+        case XPOWERS_ALDO3:
+        case XPOWERS_ALDO4:
+        case XPOWERS_BLDO1:
+        case XPOWERS_BLDO2:
+        case XPOWERS_VBACKUP:
+        case XPOWERS_CPULDO:
+            return true;
+        default:
+            // DLDO is not available, will also return false
+            return false;
+        }
+    }
+    return false;
+}
+
+void XPowersLibInterface::setProtectedChannel(uint8_t channel)
+{
+    __protectedMask |= _BV(channel);
+}
+
+void XPowersLibInterface::setUnprotectChannel(uint8_t channel)
+{
+    __protectedMask &= (~_BV(channel));
+}
+
+bool XPowersLibInterface::getProtectedChannel(uint8_t channel)
+{
+    return __protectedMask & _BV(channel);
+}
+
+
+uint16_t XPowersLibInterface::getVbusVoltage()
+{
+    return 0;
+}
+
+static uint64_t inline check_params(uint32_t opt, uint32_t params, uint64_t mask)
+{
+    return ((opt & params) == params) ? mask : 0;
+}
+
+bool XPowersLibInterface::enableInterrupt(uint32_t option)
+{
+    return setInterruptMask(option, true);
+}
+
+bool XPowersLibInterface::disableInterrupt(uint32_t option)
+{
+    return setInterruptMask(option, false);
+}
+
+bool XPowersLibInterface::setInterruptMask(uint32_t option, bool enable)
+{
+    uint64_t params = 0;
+    switch (__chipModel) {
+    case XPOWERS_AXP173:
+        break;
+    case XPOWERS_AXP192:
+        params |=  check_params(option, XPOWERS_USB_INSERT_INT, XPOWERS_AXP192_VBUS_INSERT_IRQ);
+        params |=  check_params(option, XPOWERS_USB_REMOVE_INT, XPOWERS_AXP192_VBUS_REMOVE_IRQ);
+        params |=  check_params(option, XPOWERS_BATTERY_INSERT_INT, XPOWERS_AXP192_BAT_INSERT_IRQ);
+        params |=  check_params(option, XPOWERS_BATTERY_REMOVE_INT, XPOWERS_AXP192_BAT_REMOVE_IRQ);
+        params |=  check_params(option, XPOWERS_CHARGE_START_INT, XPOWERS_AXP192_BAT_CHG_START_IRQ);
+        params |=  check_params(option, XPOWERS_CHARGE_DONE_INT, XPOWERS_AXP192_BAT_CHG_DONE_IRQ);
+        params |=  check_params(option, XPOWERS_PWR_BTN_CLICK_INT, XPOWERS_AXP192_PKEY_SHORT_IRQ);
+        params |=  check_params(option, XPOWERS_PWR_BTN_LONGPRESSED_INT, XPOWERS_AXP192_PKEY_LONG_IRQ);
+        params |=  check_params(option, XPOWERS_ALL_INT, XPOWERS_AXP192_ALL_IRQ);
+        return enable ? enableIRQ(params) : disableIRQ(params);
+        break;
+    case XPOWERS_AXP202:
+        params |=  check_params(option, XPOWERS_USB_INSERT_INT, XPOWERS_AXP202_VBUS_INSERT_IRQ);
+        params |=  check_params(option, XPOWERS_USB_REMOVE_INT, XPOWERS_AXP202_VBUS_REMOVE_IRQ);
+        params |=  check_params(option, XPOWERS_BATTERY_INSERT_INT, XPOWERS_AXP202_BAT_INSERT_IRQ);
+        params |=  check_params(option, XPOWERS_BATTERY_REMOVE_INT, XPOWERS_AXP202_BAT_REMOVE_IRQ);
+        params |=  check_params(option, XPOWERS_CHARGE_START_INT, XPOWERS_AXP202_BAT_CHG_START_IRQ);
+        params |=  check_params(option, XPOWERS_CHARGE_DONE_INT, XPOWERS_AXP202_BAT_CHG_DONE_IRQ);
+        params |=  check_params(option, XPOWERS_PWR_BTN_CLICK_INT, XPOWERS_AXP202_PKEY_SHORT_IRQ);
+        params |=  check_params(option, XPOWERS_PWR_BTN_LONGPRESSED_INT, XPOWERS_AXP202_PKEY_LONG_IRQ);
+        params |=  check_params(option, XPOWERS_ALL_INT, XPOWERS_AXP202_ALL_IRQ);
+        return enable ? enableIRQ(params) : disableIRQ(params);
+        break;
+    case XPOWERS_AXP216:
+        break;
+    case XPOWERS_AXP2101:
+        params |=  check_params(option, XPOWERS_USB_INSERT_INT, XPOWERS_AXP2101_VBUS_INSERT_IRQ);
+        params |=  check_params(option, XPOWERS_USB_REMOVE_INT, XPOWERS_AXP2101_VBUS_REMOVE_IRQ);
+        params |=  check_params(option, XPOWERS_BATTERY_INSERT_INT, XPOWERS_AXP2101_BAT_INSERT_IRQ);
+        params |=  check_params(option, XPOWERS_BATTERY_REMOVE_INT, XPOWERS_AXP2101_BAT_REMOVE_IRQ);
+        params |=  check_params(option, XPOWERS_CHARGE_START_INT, XPOWERS_AXP2101_BAT_CHG_START_IRQ);
+        params |=  check_params(option, XPOWERS_CHARGE_DONE_INT, XPOWERS_AXP2101_BAT_CHG_DONE_IRQ);
+        params |=  check_params(option, XPOWERS_PWR_BTN_CLICK_INT, XPOWERS_AXP2101_PKEY_SHORT_IRQ);
+        params |=  check_params(option, XPOWERS_PWR_BTN_LONGPRESSED_INT, XPOWERS_AXP2101_PKEY_LONG_IRQ);
+        params |=  check_params(option, XPOWERS_ALL_INT, XPOWERS_AXP2101_ALL_IRQ);
+        return enable ? enableIRQ(params) : disableIRQ(params);
+        break;
+    default:
+        break;
+    }
+    return false;
+}

buildroot/package/axp2101/src/XPowersLib/XPowersLibInterface.hpp

@@ -0,0 +1,672 @@
+/**
+ *
+ * @license MIT License
+ *
+ * Copyright (c) 2022 lewis he
+ *
+ * Permission is hereby granted,free of charge,to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"),to deal
+ * in the Software without restriction,including without limitation the rights
+ * to use,copy,modify,merge,publish,distribute,sublicense,and/or sell
+ * copies of the Software,and to permit persons to whom the Software is
+ * furnished to do so,subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS",WITHOUT WARRANTY OF ANY KIND,EXPRESS OR
+ * IMPLIED,INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,DAMAGES OR OTHER
+ * LIABILITY,WHETHER IN AN ACTION OF CONTRACT,TORT OR OTHERWISE,ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * @file      XPowersLibInterface.hpp
+ * @author    Lewis He (lewishe@outlook.com)
+ * @date      2022-08-28
+ *
+ */
+#pragma once
+
+#include <stdint.h>
+#include "XPowersParams.hpp"
+
+/*
+| CHIP       | AXP173            | AXP192            | AXP202            | AXP2101                                |
+| ---------- | ----------------- | ----------------- | ----------------- | -------------------------------------- |
+| DC1        | 0.7V-3.5V /1.2A   | 0.7V-3.5V  /1.2A  | X                 | 1.5-3.4V                        /2A    |
+| DC2        | 0.7-2.275V/0.6A   | 0.7-2.275V /1.6A  | 0.7-2.275V /1.6A  | 0.5-1.2V,1.22-1.54V             /2A    |
+| DC3        | X                 | 0.7-3.5V   /0.7A  | 0.7-3.5V   /1.2A  | 0.5-1.2V,1.22-1.54V,1.6-3.4V    /2A    |
+| DC4        | X                 | x                 | x                 | 0.5-1.2V,1.22-1.84V             /1.5A   |
+| DC5        | X                 | x                 | x                 | 1.2V,1.4-3.7V                   /1A    |
+| LDO1(VRTC) | 3.3V       /30mA  | 3.3V       /30mA  | 3.3V       /30mA  | 1.8V                            /30mA  |
+| LDO2       | 1.8V-3.3V  /200mA | 1.8V-3.3V  /200mA | 1.8V-3.3V  /200mA | x                                      |
+| LDO3       | 1.8V-3.3V  /200mA | 1.8-3.3V   /200mA | 0.7-3.5V   /200mA | x                                      |
+| LDO4       | 0.7-3.5V   /500mA | X                 | 1.8V-3.3V  /200mA | x                                      |
+| LDO5/IO0   | X                 | 1.8-3.3V   /50mA  | 1.8-3.3V   /50mA  | x                                      |
+| ALDO1      | x                 | x                 | x                 | 0.5-3.5V                        /300mA |
+| ALDO2      | x                 | x                 | x                 | 0.5-3.5V                        /300mA |
+| ALDO3      | x                 | x                 | x                 | 0.5-3.5V                        /300mA |
+| ALDO4      | x                 | x                 | x                 | 0.5-3.5V                        /300mA |
+| BLDO1      | x                 | x                 | x                 | 0.5-3.5V                        /300mA |
+| BLDO2      | x                 | x                 | x                 | 0.5-3.5V                        /300mA |
+| DLDO1      | x                 | x                 | x                 | 0.5-3.3V/ 0.5-1.4V              /300mA |
+| DLDO1      | x                 | x                 | x                 | 0.5-3.3V/ 0.5-1.4V              /300mA |
+| CPUSLDO    | x                 | x                 | x                 | 0.5-1.4V                        /30mA  |
+|            |                   |                   |                   |                                        |
+*/
+
+
+
+// @brief Each chip resource is different,please refer to the table above
+typedef enum __XPowersPowerChannel {
+
+    XPOWERS_DCDC1,
+    XPOWERS_DCDC2,
+    XPOWERS_DCDC3,
+    XPOWERS_DCDC4,
+    XPOWERS_DCDC5,
+
+    XPOWERS_LDO1,
+    XPOWERS_LDO2,
+    XPOWERS_LDO3,
+    XPOWERS_LDO4,
+    XPOWERS_LDO5,
+
+    XPOWERS_LDOIO,
+
+    XPOWERS_ALDO1,
+    XPOWERS_ALDO2,
+    XPOWERS_ALDO3,
+    XPOWERS_ALDO4,
+
+    XPOWERS_BLDO1,
+    XPOWERS_BLDO2,
+
+    XPOWERS_DLDO1,
+    XPOWERS_DLDO2,
+
+    XPOWERS_VBACKUP,
+
+    XPOWERS_CPULDO,
+
+} XPowersPowerChannel_t;
+
+// @brief Chip type
+typedef enum __XPowersChipModel {
+    XPOWERS_AXP173,
+    XPOWERS_AXP192,
+    XPOWERS_AXP202,
+    XPOWERS_AXP216,
+    XPOWERS_AXP2101,
+    XPOWERS_UNDEFINED,
+} XPowersChipModel_t;
+
+
+/**
+ * @brief  Compatible with subclasses of the Meshtastic-devic project
+ */
+class HasBatteryLevel
+{
+public:
+    /**
+    * @brief  Get battery percentage
+    * @retval 0~100% , -1 no battery is connected
+    */
+    virtual int getBatteryPercent()
+    {
+        return -1;
+    }
+
+    /**
+    * @brief  Get battery Voltage
+    * @retval Voltage unit: millivolt , 0 is no battery is connected
+    */
+    virtual uint16_t getBattVoltage()
+    {
+        return 0;
+    }
+
+    /**
+     * @brief Query whether the current battery is connected
+     * @retval true to access,false to not access
+     */
+    virtual bool isBatteryConnect()
+    {
+        return false;
+    }
+
+    /**
+     * @brief Query whether the current USB is connected
+     * @retval true to access,false to not access
+     */
+    virtual bool isVbusIn()
+    {
+        return false;
+    }
+
+    /**
+    * @brief Query whether it is currently in charging state
+    * @retval true to charge,false to not charge
+    */
+    virtual bool isCharging()
+    {
+        return false;
+    }
+};
+
+// @brief Power resource interface class
+class XPowersLibInterface : public HasBatteryLevel
+{
+public:
+
+    XPowersLibInterface() : __chipModel(XPOWERS_UNDEFINED), __protectedMask(0) {};
+
+    virtual ~XPowersLibInterface() {}
+
+    /**
+     * @brief  Calling the XPowersLibInterface interface class
+     *         requires calling init for initialization
+     * @retval
+     */
+    virtual bool init() = 0;
+
+    /**
+     * @brief  When calling the XPowersLibInterface interface class,
+     *         calling deinit releases the Wire handle
+     * @retval None
+     */
+    virtual void deinit() = 0;
+
+
+    /**
+     * @brief  Set the PMU sleep flag,
+     *         need to manually close the power channel after setting
+     * @retval true success false failed
+     */
+    virtual bool enableSleep() = 0;
+
+
+    /**
+     * @brief  Set shutdown, calling shutdown will turn off all power channels,
+     *         only VRTC belongs to normal power supply
+     * @retval None
+     */
+    virtual void shutdown() = 0;
+
+
+    /**
+     * @brief Get PMU satatus register
+     * @note
+     * @retval register value
+     */
+    virtual uint16_t status() = 0;
+
+
+    /**
+     * @brief Query chip ID
+     * @retval  Chip ID
+     */
+    virtual uint8_t getChipID() = 0;
+
+    //Status function
+    /**
+    * @brief Query whether it is currently in charging state
+    * @retval true to charge,false to not charge
+    */
+    // virtual bool isCharging() = 0;
+
+    /**
+     * @brief Query whether the current USB is connected
+     * @retval true to access,false to not access
+     */
+    // virtual bool isVbusIn() = 0;
+
+    /**
+     * @brief Query whether the current battery is connected
+     * @retval true to access,false to not access
+     */
+    // virtual bool isBatteryConnect() = 0;
+
+    /**
+     * @brief Query whether the current is in the discharge state
+     * @retval true the battery is discharged,false is not discharged
+     */
+    virtual bool isDischarge() = 0;
+
+    //Power Channel Control
+
+    /**
+     * @brief  Turn on the power channel
+     * @param  channel: Parameters See XPowersPowerChannel_t enumeration
+     * @retval true success false failed
+     */
+    virtual bool enablePowerOutput(uint8_t channel) = 0;
+
+    /**
+     * @brief  Turn off the power channel
+     * @param  channel: Parameters See XPowersPowerChannel_t enumeration
+     * @retval true success false failed
+     */
+    virtual bool disablePowerOutput(uint8_t channel) = 0;
+
+    /**
+     * @brief  Get whether the power channel is enabled
+     * @param  channel: Parameters See XPowersPowerChannel_t enumeration
+     * @retval true success false failed
+     */
+    virtual bool isPowerChannelEnable(uint8_t channel) = 0;
+
+    /**
+     * @brief  Get the set voltage of the power channel
+     * @param  channel: Parameters See XPowersPowerChannel_t enumeration
+     * @retval true success false failed
+     */
+    virtual uint16_t getPowerChannelVoltage(uint8_t channel) = 0;
+
+    /**
+     * @brief  Set the output voltage of a channel power supply
+     * @param  channel: Parameters See XPowersPowerChannel_t enumeration
+     * @retval true success false failed
+     */
+    virtual bool setPowerChannelVoltage(uint8_t channel, uint16_t millivolt) = 0;
+
+    /**
+     * @brief  Set a channel power protection,after setting this channel
+     *         will not be able to be set and closed
+     * @param  channel: Parameters See XPowersPowerChannel_t enumeration
+     */
+    virtual void setProtectedChannel(uint8_t channel);
+
+    /**
+     * @brief  Unprotect the channel, call this to unprotect the channel lock
+     * @param  channel: Parameters See XPowersPowerChannel_t enumeration
+     */
+    virtual void setUnprotectChannel(uint8_t channel);
+
+    /**
+     * * @brief  Get whether a channel power supply has been protected
+     * @param  channel: Parameters See XPowersPowerChannel_t enumeration
+     * @retval true is set,false is not set
+     */
+    virtual bool getProtectedChannel(uint8_t channel);
+
+
+    /**
+     * @brief  Query whether the PMU input parameter channel is valid
+     * @param  channel: Parameters See XPowersPowerChannel_t enumeration
+     * @retval true valid false invalid
+     */
+    virtual bool isChannelAvailable(uint8_t channel);
+
+    virtual void setPrechargeCurr(uint8_t opt) = 0;
+    virtual void disableChargerTerminationLimit(void) = 0;
+
+    virtual bool setVbusVoltageLimit(uint8_t opt) = 0;
+    virtual uint8_t getVbusVoltageLimit(void) = 0;
+
+    virtual bool isStandby(void) = 0;
+    virtual bool isVbusGood(void) = 0;
+    virtual uint8_t getChargerStatus(void) = 0;
+    virtual void enableCellbatteryCharge(void) = 0;
+    virtual void enableGauge(void) = 0;
+    virtual void disableGauge(void) = 0;
+    virtual void setLinearChargerVsysDpm(uint8_t opt) = 0;
+    virtual void disablePwronShutPMIC(void) = 0;
+
+    virtual void fuelGaugeControl(bool writeROM, bool enable) = 0;
+    virtual void printIntRegister() = 0;
+
+    //battery
+    /**
+    * @brief  Get battery Voltage
+    * @retval Voltage unit: millivolt , 0 is no battery is connected
+    */
+    // virtual uint16_t getBattVoltage() = 0;
+
+    /**
+    * @brief  Get battery percentage
+    * @retval 0~100% , -1 no battery is connected
+    */
+    // virtual int getBatteryPercent(void);
+
+    // Vbus
+    /**
+    * @brief  Get PMU VBUS/USB Voltage
+    * @retval Voltage unit: millivolt , 0 is no vbus is connected
+    */
+    virtual uint16_t getVbusVoltage();
+
+
+    /**
+     * @brief  Set VBUS Current Input Limit.
+     * @param  opt: View the related chip type xpowers_axpxxx_vbus_cur_limit_t enumeration
+     *              parameters in "XPowersParams.hpp"
+     * @retval true valid false invalid
+     */
+    virtual bool setVbusCurrentLimit(uint8_t opt) = 0;
+
+    /**
+    * @brief  Get VBUS Current Input Limit.
+    * @retval View the related chip type xpowers_axpxxx_vbus_cur_limit_t enumeration
+    *              parameters in "XPowersParams.hpp"
+    */
+    virtual uint8_t getVbusCurrentLimit(void) = 0;
+
+
+    // SYS
+    /**
+    * @brief  Get PMU SYS main Voltage
+    * @retval Voltage unit: millivolt
+    */
+    virtual uint16_t getSystemVoltage() = 0;
+
+    /**
+     * @brief  Set PMU Low Voltage Shutdown Threshold
+     * @param  millivolt: 2600mV ~ 3300mV
+     * @retval true valid false invalid
+     */
+    virtual bool setSysPowerDownVoltage(uint16_t millivolt) = 0;
+
+    /**
+     * @brief  Get PMU Low Voltage Shutdown Threshold
+     * @retval Voltage unit: millivolt
+     */
+    virtual uint16_t getSysPowerDownVoltage() = 0;
+
+    /**
+     * @brief  Set charge target voltage.
+     * @param  opt: View the related chip type xpowers_axpxxx_chg_vol_t enumeration
+     *              parameters in "XPowersParams.hpp"
+     * @retval true valid false invalid
+     */
+    virtual bool setChargeTargetVoltage(uint8_t opt) = 0;
+
+    /**
+     * @brief  Get charge target voltage.
+     * @retval View the related chip type xpowers_axpxxx_chg_vol_t enumeration
+     *         parameters in "XPowersParams.hpp"
+     *   parameters in "XPowersParams.hpp"
+     */
+    virtual uint8_t getChargeTargetVoltage() = 0;
+
+    /**
+     * @brief  Set charge current.
+     * @param  opt: View the related chip type xpowers_axpxxx_chg_curr_t enumeration
+     *              parameters in "XPowersParams.hpp"
+     * @retval true valid false invalid
+     */
+    virtual bool setChargerConstantCurr(uint8_t opt) = 0;
+
+    /**
+     * @brief  Get charge current.
+     * @retval View the related chip type xpowers_axpxxx_chg_curr_t enumeration
+     *         parameters in "XPowersParams.hpp"
+     */
+    virtual uint8_t getChargerConstantCurr() = 0;
+
+
+    //!PMU Interrupt control
+    /*
+     *  Example of interrupt usage
+     *  if (pmuInterrupt) {
+     *      pmuInterrupt = false;
+     *
+     *      Read interrupt status
+     *      uint64_t mask =  PMU->getIrqStatus();
+     *      Serial.print("IRQ Mask:0b");
+     *      Serial.println(mask,BIN);
+     *
+     *      if (PMU->isPekeyShortPressIrq()) {
+     *          Serial.println("isPekeyShortPressIrq");
+     *      }
+     *      if (PMU->isBatChagerStartIrq()) {
+     *          Serial.println("isBatChagerStart");
+     *      }
+     *      ......
+     *
+     *      After reading the interrupt status,you need to manually clear the status register
+     *      PMU->clearIrqStatus();
+     *  }
+     * * * */
+
+
+    /**
+    * @brief  Get the interrupt controller mask value.
+    * @retval   Mask value corresponds to xpowers_axpxxx_irq_t ,
+    */
+    virtual uint64_t getIrqStatus() = 0;
+
+    /**
+     * @brief  Clear interrupt controller state.
+     */
+    virtual void clearIrqStatus() = 0;
+
+    /**
+     * @brief  Eanble PMU interrupt control mask .
+     * @param  opt: View the related chip type xpowers_axpxxx_irq_t enumeration
+     *              parameters in "XPowersParams.hpp"
+     * @retval true valid false invalid
+     */
+    virtual bool enableIRQ(uint64_t opt) = 0;
+
+    /**
+     * @brief  Disable PMU interrupt control mask .
+     * @param  opt: View the related chip type xpowers_axpxxx_irq_t enumeration
+     *              parameters in "XPowersParams.hpp"
+     * @retval true valid false invalid
+     */
+    virtual bool disableIRQ(uint64_t opt) = 0;
+
+    /**
+     * @brief   .
+     * @param  opt: View the related chip type xpowers_interrupt_enum_t enumeration
+     *              parameters in "XPowersParams.hpp"
+     * @retval true valid false invalid
+     */
+    bool enableInterrupt(uint32_t opt);
+
+    /**
+     * @brief   .
+     * @param  opt: View the related chip type xpowers_interrupt_enum_t enumeration
+     *              parameters in "XPowersParams.hpp"
+     * @retval true valid false invalid
+     */
+    bool disableInterrupt(uint32_t opt);
+
+    /**
+     * @brief   .
+     * @param  opt: View the related chip type xpowers_interrupt_enum_t enumeration
+     *              parameters in "XPowersParams.hpp"
+     * @retval true valid false invalid
+     */
+    bool setInterruptMask(uint32_t option, bool enable);
+
+    /**
+     * @brief  Interrupt response when PMU PEKEY is short pressed
+     * @retval true valid false invalid
+     */
+    virtual bool isPekeyShortPressIrq() = 0;
+
+    /**
+     * @brief  Interrupt response when PMU PEKEY is long pressed
+     * @retval true valid false invalid
+     */
+    virtual bool isPekeyLongPressIrq() = 0;
+
+    /**
+     * @brief  Interrupt response when PMU battery is connected
+     * @retval true valid false invalid
+     */
+    virtual bool isBatInsertIrq() = 0;
+
+    /**
+     * @brief  Interrupt response when PMU battery is removed
+     * @retval true valid false invalid
+     */
+    virtual bool isBatRemoveIrq() = 0;
+
+    /**
+     * @brief  Interrupt response when PMU USB is plugged in
+     * @retval true valid false invalid
+     */
+    virtual bool isVbusInsertIrq() = 0;
+
+    /**
+     * @brief  Interrupt response when PMU USB is removed
+     * @retval true valid false invalid
+     */
+    virtual bool isVbusRemoveIrq() = 0;
+
+    /**
+     * @brief  Interrupt response when PMU charging is complete
+     * @retval true valid false invalid
+     */
+    virtual bool isBatChagerDoneIrq() = 0;
+
+    /**
+     * @brief  Interrupt response when PMU charging starts
+     * @retval true valid false invalid
+     */
+    virtual bool isBatChagerStartIrq() = 0;
+
+
+    //Data collection function
+
+    /**
+     * @brief  Enable battery detection function,the default is on
+     * @retval true success false failed
+     */
+    virtual bool enableBattDetection() = 0;
+
+    /**
+     * @brief  Disable battery detection
+     * @retval true success false failed
+     */
+    virtual bool disableBattDetection() = 0;
+
+    /**
+     * @brief  Enable USB input voltage detection
+     * @retval true success false failed
+     */
+    virtual bool enableVbusVoltageMeasure(void) = 0;
+
+    /**
+     * @brief  Disable USB input voltage detection
+     * @retval true success false failed
+     */
+    virtual bool disableVbusVoltageMeasure(void) = 0;
+
+    /**
+     * @brief  Enable system voltage detection
+     * @retval true success false failed
+     */
+    virtual bool enableSystemVoltageMeasure(void) = 0;
+
+    /**
+     * @brief  Disable system voltage detection
+     * @retval true success false failed
+     */
+    virtual bool disableSystemVoltageMeasure(void) = 0;
+
+    /**
+     * @brief  Enable PMU internal temperature sensor detection
+     * @retval true success false failed
+     */
+    virtual bool enableTemperatureMeasure(void) = 0;
+
+    /**
+     * @brief  Disable PMU internal temperature sensor detection
+     * @retval true success false failed
+     */
+    virtual bool disableTemperatureMeasure(void) = 0;
+
+    /**
+     * @brief  Enable battery input voltage detection
+     * @retval true success false failed
+     */
+    virtual bool enableBattVoltageMeasure(void) = 0;
+
+    /**
+     * @brief  Disable battery input voltage detection
+     * @retval true success false failed
+     */
+    virtual bool disableBattVoltageMeasure(void) = 0;
+
+    /**
+     * @brief  Enable NTC thermistor detection (requires hardware support)
+     * @retval true success false failed
+     */
+    virtual bool enableTSPinMeasure(void) = 0;
+
+    /**
+     * @brief  Disable NTC thermistor detection (requires hardware support)
+     * @retval true success false failed
+     */
+    virtual bool disableTSPinMeasure(void) = 0;
+
+    // Charge indicator function
+    /**
+    * @brief  Set charging led mode
+    * @param  opt: View the related chip type xpowers_chg_led_mode_t enumeration
+    *              parameters in "XPowersParams.hpp"
+    */
+    virtual void setChargingLedMode(uint8_t mode) = 0;
+    virtual void setChargerTerminationCurr(uint8_t opt) = 0;
+    virtual void disableDieOverTempDetect(void) = 0;
+    virtual void resetGauge(void) = 0;
+    virtual void enableLongPressShutdown(void) = 0;
+
+    // PMU PEKEY settings
+    /**
+    * @brief  Set PEKEY press power on time
+    * @param  opt: View the related chip type xpowers_press_on_time_t enumeration
+    *              parameters in "XPowersParams.hpp"
+    * @retval true success false failed
+    */
+    virtual bool setPowerKeyPressOnTime(uint8_t opt) = 0;
+
+    /**
+     * @brief Get PEKEY press power on time
+     * @retval View the related chip type xpowers_press_on_time_t enumeration
+     *              parameters in "XPowersParams.hpp"
+     */
+    virtual uint8_t getPowerKeyPressOnTime() = 0;
+
+    /**
+     * @brief Set PEKEY press power off time
+     * @param  opt: View the related chip type xpowers_press_off_time_t enumeration
+     *              parameters in "XPowersParams.hpp"
+     * @retval true success false failed
+     */
+    virtual bool setPowerKeyPressOffTime(uint8_t opt) = 0;
+
+    /**
+     * @brief Get PEKEY press power off time
+     * @retval View the related chip type xpowers_press_off_time_t enumeration
+     *              parameters in "XPowersParams.hpp"
+     */
+    virtual uint8_t getPowerKeyPressOffTime() = 0;
+
+    /**
+     * @brief Get the chip model
+     * @retval See XPowersChipModel_t enumeration
+     */
+    uint8_t getChipModel()
+    {
+        return __chipModel;
+    }
+
+protected:
+
+    void setChipModel(uint8_t m)
+    {
+        __chipModel = m;
+    }
+
+    uint8_t __chipModel;
+    uint32_t __protectedMask;
+
+};
+

buildroot/package/axp2101/src/XPowersLib/XPowersParams.hpp

@@ -0,0 +1,399 @@
+/**
+ *
+ * @license MIT License
+ *
+ * Copyright (c) 2022 lewis he
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * @file      XPowersParams.hpp
+ * @author    Lewis He (lewishe@outlook.com)
+ * @date      2022-08-28
+ *
+ */
+
+#pragma once
+
+#ifdef _BV
+#undef _BV
+#endif
+#define _BV(b)                          (1ULL << (uint64_t)(b))
+
+
+//TODO:Unified interface functions and parameters
+
+/**
+ * @brief PMU PEKEY Press off time parameters.
+ */
+typedef enum __xpowers_press_off_time {
+    XPOWERS_POWEROFF_4S,
+    XPOWERS_POWEROFF_6S,
+    XPOWERS_POWEROFF_8S,
+    XPOWERS_POWEROFF_10S,
+} xpowers_press_off_time_t;
+
+/**
+ * @brief PMU PEKEY Press on time parameters.
+ */
+typedef enum __xpowers_press_on_time {
+    XPOWERS_POWERON_128MS,
+    XPOWERS_POWERON_512MS,
+    XPOWERS_POWERON_1S,
+    XPOWERS_POWERON_2S,
+} xpowers_press_on_time_t;
+
+
+/**
+ * @brief Charging led mode parameters.
+ */
+typedef enum __xpowers_chg_led_mode {
+    XPOWERS_CHG_LED_OFF,
+    XPOWERS_CHG_LED_BLINK_1HZ,
+    XPOWERS_CHG_LED_BLINK_4HZ,
+    XPOWERS_CHG_LED_ON,
+    XPOWERS_CHG_LED_CTRL_CHG,    // The charging indicator is controlled by the charger
+} xpowers_chg_led_mode_t;
+
+/**
+ * @brief axp2101 charge target voltage parameters.
+ */
+typedef enum __xpowers_axp2101_chg_vol {
+    XPOWERS_AXP2101_CHG_VOL_4V = 1,
+    XPOWERS_AXP2101_CHG_VOL_4V1,
+    XPOWERS_AXP2101_CHG_VOL_4V2,
+    XPOWERS_AXP2101_CHG_VOL_4V35,
+    XPOWERS_AXP2101_CHG_VOL_4V4,
+    XPOWERS_AXP2101_CHG_VOL_MAX
+} xpowers_axp2101_chg_vol_t;
+
+/**
+ * @brief axp2101 charge currnet voltage parameters.
+ */
+typedef enum __xpowers_axp2101_chg_curr {
+    XPOWERS_AXP2101_CHG_CUR_0MA,
+    XPOWERS_AXP2101_CHG_CUR_100MA = 4,
+    XPOWERS_AXP2101_CHG_CUR_125MA,
+    XPOWERS_AXP2101_CHG_CUR_150MA,
+    XPOWERS_AXP2101_CHG_CUR_175MA,
+    XPOWERS_AXP2101_CHG_CUR_200MA,
+    XPOWERS_AXP2101_CHG_CUR_300MA,
+    XPOWERS_AXP2101_CHG_CUR_400MA,
+    XPOWERS_AXP2101_CHG_CUR_500MA,
+    XPOWERS_AXP2101_CHG_CUR_600MA,
+    XPOWERS_AXP2101_CHG_CUR_700MA,
+    XPOWERS_AXP2101_CHG_CUR_800MA,
+    XPOWERS_AXP2101_CHG_CUR_900MA,
+    XPOWERS_AXP2101_CHG_CUR_1000MA,
+} xpowers_axp2101_chg_curr_t;
+
+
+/**
+ * @brief axp192 charge target voltage parameters.
+ */
+typedef enum __xpowers_axp192_chg_vol {
+    XPOWERS_AXP192_CHG_VOL_4V1,
+    XPOWERS_AXP192_CHG_VOL_4V15,
+    XPOWERS_AXP192_CHG_VOL_4V2,
+    XPOWERS_AXP192_CHG_VOL_4V36,
+    XPOWERS_AXP192_CHG_VOL_MAX,
+} xpowers_axp192_chg_vol_t;
+
+/**
+ * @brief axp202 charge target voltage parameters.
+ */
+typedef enum __xpowers_axp202_chg_vol {
+    XPOWERS_AXP202_CHG_VOL_4V1,
+    XPOWERS_AXP202_CHG_VOL_4V15,
+    XPOWERS_AXP202_CHG_VOL_4V2,
+    XPOWERS_AXP202_CHG_VOL_4V36,
+    XPOWERS_AXP202_CHG_VOL_MAX,
+} xpowers_axp202_chg_vol_t;
+
+/**
+ * @brief axp192 charge currnet voltage parameters.
+ */
+typedef enum __xpowers_axp192_chg_curr {
+    XPOWERS_AXP192_CHG_CUR_100MA,
+    XPOWERS_AXP192_CHG_CUR_190MA,
+    XPOWERS_AXP192_CHG_CUR_280MA,
+    XPOWERS_AXP192_CHG_CUR_360MA,
+    XPOWERS_AXP192_CHG_CUR_450MA,
+    XPOWERS_AXP192_CHG_CUR_550MA,
+    XPOWERS_AXP192_CHG_CUR_630MA,
+    XPOWERS_AXP192_CHG_CUR_700MA,
+    XPOWERS_AXP192_CHG_CUR_780MA,
+    XPOWERS_AXP192_CHG_CUR_880MA,
+    XPOWERS_AXP192_CHG_CUR_960MA,
+    XPOWERS_AXP192_CHG_CUR_1000MA,
+    XPOWERS_AXP192_CHG_CUR_1080MA,
+    XPOWERS_AXP192_CHG_CUR_1160MA,
+    XPOWERS_AXP192_CHG_CUR_1240MA,
+    XPOWERS_AXP192_CHG_CUR_1320MA,
+} xpowers_axp192_chg_curr_t;
+
+/**
+ * @brief axp202 charge currnet voltage parameters.
+ */
+typedef enum __xpowers_axp202_chg_curr {
+    XPOWERS_AXP202_CHG_CUR_100MA,
+    XPOWERS_AXP202_CHG_CUR_190MA,
+    XPOWERS_AXP202_CHG_CUR_280MA,
+    XPOWERS_AXP202_CHG_CUR_360MA,
+    XPOWERS_AXP202_CHG_CUR_450MA,
+    XPOWERS_AXP202_CHG_CUR_550MA,
+    XPOWERS_AXP202_CHG_CUR_630MA,
+    XPOWERS_AXP202_CHG_CUR_700MA,
+    XPOWERS_AXP202_CHG_CUR_780MA,
+    XPOWERS_AXP202_CHG_CUR_880MA,
+    XPOWERS_AXP202_CHG_CUR_960MA,
+    XPOWERS_AXP202_CHG_CUR_1000MA,
+    XPOWERS_AXP202_CHG_CUR_1080MA,
+    XPOWERS_AXP202_CHG_CUR_1160MA,
+    XPOWERS_AXP202_CHG_CUR_1240MA,
+    XPOWERS_AXP202_CHG_CUR_1320MA,
+} xpowers_axp202_chg_curr_t;
+
+
+/**
+ * @brief axp2101 vbus currnet limit parameters.
+ */
+typedef enum {
+    XPOWERS_AXP2101_VBUS_CUR_LIM_100MA,
+    XPOWERS_AXP2101_VBUS_CUR_LIM_500MA,
+    XPOWERS_AXP2101_VBUS_CUR_LIM_900MA,
+    XPOWERS_AXP2101_VBUS_CUR_LIM_1000MA,
+    XPOWERS_AXP2101_VBUS_CUR_LIM_1500MA,
+    XPOWERS_AXP2101_VBUS_CUR_LIM_2000MA,
+} xpowers_axp2101_vbus_cur_limit_t;
+
+/**
+ * @brief axp192 vbus currnet limit parameters.
+ */
+typedef enum {
+    XPOWERS_AXP192_VBUS_CUR_LIM_500MA,
+    XPOWERS_AXP192_VBUS_CUR_LIM_100MA,
+    XPOWERS_AXP192_VBUS_CUR_LIM_OFF,
+} xpowers_axp192_vbus_cur_limit_t;
+
+
+/**
+ * @brief axp202 vbus currnet limit parameters.
+ */
+typedef enum {
+    XPOWERS_AXP202_VBUS_CUR_LIM_900MA,
+    XPOWERS_AXP202_VBUS_CUR_LIM_500MA,
+    XPOWERS_AXP202_VBUS_CUR_LIM_100MA,
+    XPOWERS_AXP202_VBUS_CUR_LIM_OFF,
+} xpowers_axp202_vbus_cur_limit_t;
+
+/**
+ * @brief XPowersLibInterface interrupt control mask parameters.
+ *          Common interrupt interfaces
+ * @Example: enableInterrupt(XPOWERS_USB_INSERT_INT|XPOWERS_USB_REMOVE_INT);
+ *           disableInterrupt(XPOWERS_CHARGE_START_INT|XPOWERS_PWR_BTN_CLICK_INT);
+ */
+typedef enum __xpowers_interrupt_enum {
+    XPOWERS_USB_INSERT_INT          = _BV(0),
+    XPOWERS_USB_REMOVE_INT          = _BV(1),
+    XPOWERS_BATTERY_INSERT_INT      = _BV(2),
+    XPOWERS_BATTERY_REMOVE_INT      = _BV(3),
+    XPOWERS_CHARGE_START_INT        = _BV(4),
+    XPOWERS_CHARGE_DONE_INT         = _BV(5),
+    XPOWERS_PWR_BTN_CLICK_INT       = _BV(6),
+    XPOWERS_PWR_BTN_LONGPRESSED_INT = _BV(7),
+    XPOWERS_ALL_INT                 = _BV(8),
+} xpowers_interrupt_enum_t;
+
+
+/**
+ * @brief axp192 interrupt control mask parameters.
+ */
+typedef enum __xpowers_axp192_irq {
+    //! IRQ1 REG 40H
+    XPOWERS_AXP192_VBUS_VHOLD_LOW_IRQ       = _BV(1),   //VBUS is available, but lower than V HOLD, IRQ enable
+    XPOWERS_AXP192_VBUS_REMOVE_IRQ          = _BV(2),   //VBUS removed, IRQ enable
+    XPOWERS_AXP192_VBUS_INSERT_IRQ          = _BV(3),   //VBUS connected, IRQ enable
+    XPOWERS_AXP192_VBUS_OVER_VOL_IRQ        = _BV(4),   //VBUS over-voltage, IRQ enable
+    XPOWERS_AXP192_ACIN_REMOVED_IRQ         = _BV(5),   //ACIN removed, IRQ enable
+    XPOWERS_AXP192_ACIN_CONNECT_IRQ         = _BV(6),   //ACIN connected, IRQ enable
+    XPOWERS_AXP192_ACIN_OVER_VOL_IRQ        = _BV(7),   //ACIN over-voltage, IRQ enable
+
+    //! IRQ2 REG 41H
+    XPOWERS_AXP192_BATT_LOW_TEMP_IRQ        = _BV(8),   //Battery low-temperature, IRQ enable
+    XPOWERS_AXP192_BATT_OVER_TEMP_IRQ       = _BV(9),   //Battery over-temperature, IRQ enable
+    XPOWERS_AXP192_BAT_CHG_DONE_IRQ         = _BV(10),  //Charge finished, IRQ enable
+    XPOWERS_AXP192_BAT_CHG_START_IRQ        = _BV(11),  //Be charging, IRQ enable
+    XPOWERS_AXP192_BATT_EXIT_ACTIVATE_IRQ   = _BV(12),  //Exit battery activate mode, IRQ enable
+    XPOWERS_AXP192_BATT_ACTIVATE_IRQ        = _BV(13),  //Battery activate mode, IRQ enable
+    XPOWERS_AXP192_BAT_REMOVE_IRQ           = _BV(14),  //Battery removed, IRQ enable
+    XPOWERS_AXP192_BAT_INSERT_IRQ           = _BV(15),  //Battery connected, IRQ enable
+
+    //! IRQ3 REG 42H
+    XPOWERS_AXP192_PKEY_LONG_IRQ            = _BV(16),  //PEK long press, IRQ enable
+    XPOWERS_AXP192_PKEY_SHORT_IRQ           = _BV(17),  //PEK short press, IRQ enable
+    //**Reserved and unchangeable BIT 2
+    XPOWERS_AXP192_DC3_LOW_VOL_IRQ          = _BV(19),  //DC-DC3output voltage is lower than the set value, IRQ enable
+    XPOWERS_AXP192_DC2_LOW_VOL_IRQ          = _BV(20),  //DC-DC2 output voltage is lower than the set value, IRQ enable
+    XPOWERS_AXP192_DC1_LOW_VOL_IRQ          = _BV(21),  //DC-DC1 output voltage is lower than the set value, IRQ enable
+    XPOWERS_AXP192_CHARGE_LOW_CUR_IRQ       = _BV(22),  //Charge current is lower than the set current, IRQ enable
+    XPOWERS_AXP192_CHIP_TEMP_HIGH_IRQ       = _BV(23),  //XPOWERS internal over-temperature, IRQ enable
+
+    //! IRQ4 REG 43H
+    XPOWERS_AXP192_APS_LOW_VOL_LEVEL_IRQ    = _BV(24),  //APS low-voltage, IRQ enable
+    //**Reserved and unchangeable BIT 1
+    XPOWERS_AXP192_VBUS_SESSION_END_IRQ     = _BV(26),  //VBUS Session End IRQ enable
+    XPOWERS_AXP192_VBUS_SESSION_AB_IRQ      = _BV(27),  //VBUS Session A/B IRQ enable
+    XPOWERS_AXP192_VBUS_INVALID_IRQ         = _BV(28),  //VBUS invalid, IRQ enable
+    XPOWERS_AXP192_VBUS_VAILD_IRQ           = _BV(29),  //VBUS valid, IRQ enable
+    XPOWERS_AXP192_NOE_OFF_IRQ              = _BV(30),  //N_OE shutdown, IRQ enable
+    XPOWERS_AXP192_NOE_ON_IRQ               = _BV(31),  //N_OE startup, IRQ enable
+
+    //! IRQ5 REG 4AH
+    XPOWERS_AXP192_GPIO0_EDGE_TRIGGER_IRQ   = _BV(32),  //GPIO0 input edge trigger, IRQ enable
+    XPOWERS_AXP192_GPIO1_EDGE_TRIGGER_IRQ   = _BV(33),  //GPIO1input edge trigger or ADC input, IRQ enable
+    XPOWERS_AXP192_GPIO2_EDGE_TRIGGER_IRQ   = _BV(34),  //GPIO2input edge trigger, IRQ enable
+    //**Reserved and unchangeable BIT 3
+    //**Reserved and unchangeable BIT 4
+    //**Reserved and unchangeable BIT 5
+    //**Reserved and unchangeable BIT 6
+    XPOWERS_AXP192_TIMER_TIMEOUT_IRQ        = _BV(39),  //Timer timeout, IRQ enable
+
+    XPOWERS_AXP192_ALL_IRQ                  = (0xFFFFFFFFFFULL)
+} xpowers_axp192_irq_t;
+
+
+
+/**
+ * @brief axp2101 interrupt control mask parameters.
+ */
+typedef enum __xpowers_axp2101_irq {
+    //! IRQ1 REG 40H
+    XPOWERS_AXP2101_BAT_NOR_UNDER_TEMP_IRQ   = _BV(0),   // Battery Under Temperature in Work
+    XPOWERS_AXP2101_BAT_NOR_OVER_TEMP_IRQ    = _BV(1),   // Battery Over Temperature in Work mode
+    XPOWERS_AXP2101_BAT_CHG_UNDER_TEMP_IRQ   = _BV(2),   // Battery Under Temperature in Charge mode IRQ(bcut_irq)
+    XPOWERS_AXP2101_BAT_CHG_OVER_TEMP_IRQ    = _BV(3),   // Battery Over Temperature in Charge mode IRQ(bcot_irq) enable
+    XPOWERS_AXP2101_GAUGE_NEW_SOC_IRQ        = _BV(4),   // Gauge New SOC IRQ(lowsoc_irq) enable ???
+    XPOWERS_AXP2101_WDT_TIMEOUT_IRQ          = _BV(5),   // Gauge Watchdog Timeout IRQ(gwdt_irq) enable
+    XPOWERS_AXP2101_WARNING_LEVEL1_IRQ       = _BV(6),   // SOC drop to Warning Level1 IRQ(socwl1_irq) enable
+    XPOWERS_AXP2101_WARNING_LEVEL2_IRQ       = _BV(7),   // SOC drop to Warning Level2 IRQ(socwl2_irq) enable
+
+    //! IRQ2 REG 41H
+    XPOWERS_AXP2101_PKEY_POSITIVE_IRQ        = _BV(8),   // POWERON Positive Edge IRQ(ponpe_irq_en) enable
+    XPOWERS_AXP2101_PKEY_NEGATIVE_IRQ        = _BV(9),   // POWERON Negative Edge IRQ(ponne_irq_en) enable
+    XPOWERS_AXP2101_PKEY_LONG_IRQ            = _BV(10),  // POWERON Long PRESS IRQ(ponlp_irq) enable
+    XPOWERS_AXP2101_PKEY_SHORT_IRQ           = _BV(11),  // POWERON Short PRESS IRQ(ponsp_irq_en) enable
+    XPOWERS_AXP2101_BAT_REMOVE_IRQ           = _BV(12),  // Battery Remove IRQ(bremove_irq) enable
+    XPOWERS_AXP2101_BAT_INSERT_IRQ           = _BV(13),  // Battery Insert IRQ(binsert_irq) enabl
+    XPOWERS_AXP2101_VBUS_REMOVE_IRQ          = _BV(14),  // VBUS Remove IRQ(vremove_irq) enabl
+    XPOWERS_AXP2101_VBUS_INSERT_IRQ          = _BV(15),  // VBUS Insert IRQ(vinsert_irq) enable
+
+    //! IRQ3 REG 42H
+    XPOWERS_AXP2101_BAT_OVER_VOL_IRQ         = _BV(16),  // Battery Over Voltage Protection IRQ(bovp_irq) enable
+    XPOWERS_AXP2101_CHAGER_TIMER_IRQ         = _BV(17),  // Charger Safety Timer1/2 expire IRQ(chgte_irq) enable
+    XPOWERS_AXP2101_DIE_OVER_TEMP_IRQ        = _BV(18),  // DIE Over Temperature level1 IRQ(dotl1_irq) enable
+    XPOWERS_AXP2101_BAT_CHG_START_IRQ        = _BV(19),  // Charger start IRQ(chgst_irq) enable
+    XPOWERS_AXP2101_BAT_CHG_DONE_IRQ         = _BV(20),  // Battery charge done IRQ(chgdn_irq) enable
+    XPOWERS_AXP2101_BATFET_OVER_CURR_IRQ     = _BV(21),  // BATFET Over Current Protection IRQ(bocp_irq) enable
+    XPOWERS_AXP2101_LDO_OVER_CURR_IRQ        = _BV(22),  // LDO Over Current IRQ(ldooc_irq) enable
+    XPOWERS_AXP2101_WDT_EXPIRE_IRQ           = _BV(23),  // Watchdog Expire IRQ(wdexp_irq) enable
+
+    XPOWERS_AXP2101_ALL_IRQ                  = (0xFFFFFFFFUL)
+} xpowers_axp2101_irq_t;
+
+
+/**
+ * @brief axp202 interrupt control mask parameters.
+ */
+typedef enum __xpowers_axp202_irq {
+    //! IRQ1 REG 40H
+    XPOWERS_AXP202_VBUS_VHOLD_LOW_IRQ       = _BV(1),   //VBUS is available, but lower than V HOLD, IRQ enable
+    XPOWERS_AXP202_VBUS_REMOVE_IRQ          = _BV(2),   //VBUS removed, IRQ enable
+    XPOWERS_AXP202_VBUS_INSERT_IRQ          = _BV(3),   //VBUS connected, IRQ enable
+    XPOWERS_AXP202_VBUS_OVER_VOL_IRQ        = _BV(4),   //VBUS over-voltage, IRQ enable
+    XPOWERS_AXP202_ACIN_REMOVED_IRQ         = _BV(5),   //ACIN removed, IRQ enable
+    XPOWERS_AXP202_ACIN_CONNECT_IRQ         = _BV(6),   //ACIN connected, IRQ enable
+    XPOWERS_AXP202_ACIN_OVER_VOL_IRQ        = _BV(7),   //ACIN over-voltage, IRQ enable
+
+    //! IRQ2 REG 41H
+    XPOWERS_AXP202_BATT_LOW_TEMP_IRQ        = _BV(8),   //Battery low-temperature, IRQ enable
+    XPOWERS_AXP202_BATT_OVER_TEMP_IRQ       = _BV(9),   //Battery over-temperature, IRQ enable
+    XPOWERS_AXP202_BAT_CHG_DONE_IRQ         = _BV(10),  //Charge finished, IRQ enable
+    XPOWERS_AXP202_BAT_CHG_START_IRQ        = _BV(11),  //Be charging, IRQ enable
+    XPOWERS_AXP202_BATT_EXIT_ACTIVATE_IRQ   = _BV(12),  //Exit battery activate mode, IRQ enable
+    XPOWERS_AXP202_BATT_ACTIVATE_IRQ        = _BV(13),  //Battery activate mode, IRQ enable
+    XPOWERS_AXP202_BAT_REMOVE_IRQ           = _BV(14),  //Battery removed, IRQ enable
+    XPOWERS_AXP202_BAT_INSERT_IRQ           = _BV(15),  //Battery connected, IRQ enable
+
+    //! IRQ3 REG 42H
+    XPOWERS_AXP202_PKEY_LONG_IRQ            = _BV(16),  //PEK long press, IRQ enable
+    XPOWERS_AXP202_PKEY_SHORT_IRQ           = _BV(17),  //PEK short press, IRQ enable
+    XPOWERS_AXP202_LDO3_LOW_VOL_IRQ         = _BV(18),  //LDO3output voltage is lower than the set value, IRQ enable
+    XPOWERS_AXP202_DC3_LOW_VOL_IRQ          = _BV(19),  //DC-DC3output voltage is lower than the set value, IRQ enable
+    XPOWERS_AXP202_DC2_LOW_VOL_IRQ          = _BV(20),  //DC-DC2 output voltage is lower than the set value, IRQ enable
+    //**Reserved and unchangeable BIT 5
+    XPOWERS_AXP202_CHARGE_LOW_CUR_IRQ       = _BV(22),  //Charge current is lower than the set current, IRQ enable
+    XPOWERS_AXP202_CHIP_TEMP_HIGH_IRQ       = _BV(23),  //AXP202 internal over-temperature, IRQ enable
+
+    //! IRQ4 REG 43H
+    XPOWERS_AXP202_APS_LOW_VOL_LEVEL2_IRQ   = _BV(24),  //APS low-voltage, IRQ enable（LEVEL2）
+    XPOWERS_APX202_APS_LOW_VOL_LEVEL1_IRQ   = _BV(25),  //APS low-voltage, IRQ enable（LEVEL1）
+    XPOWERS_AXP202_VBUS_SESSION_END_IRQ     = _BV(26),  //VBUS Session End IRQ enable
+    XPOWERS_AXP202_VBUS_SESSION_AB_IRQ      = _BV(27),  //VBUS Session A/B IRQ enable
+    XPOWERS_AXP202_VBUS_INVALID_IRQ         = _BV(28),  //VBUS invalid, IRQ enable
+    XPOWERS_AXP202_VBUS_VAILD_IRQ           = _BV(29),  //VBUS valid, IRQ enable
+    XPOWERS_AXP202_NOE_OFF_IRQ              = _BV(30),  //N_OE shutdown, IRQ enable
+    XPOWERS_AXP202_NOE_ON_IRQ               = _BV(31),  //N_OE startup, IRQ enable
+
+    //! IRQ5 REG 44H
+    XPOWERS_AXP202_GPIO0_EDGE_TRIGGER_IRQ   = _BV(32),  //GPIO0 input edge trigger, IRQ enable
+    XPOWERS_AXP202_GPIO1_EDGE_TRIGGER_IRQ   = _BV(33),  //GPIO1input edge trigger or ADC input, IRQ enable
+    XPOWERS_AXP202_GPIO2_EDGE_TRIGGER_IRQ   = _BV(34),  //GPIO2input edge trigger, IRQ enable
+    XPOWERS_AXP202_GPIO3_EDGE_TRIGGER_IRQ   = _BV(35),  //GPIO3 input edge trigger, IRQ enable
+    //**Reserved and unchangeable BIT 4
+    XPOWERS_AXP202_PKEY_NEGATIVE_IRQ        = _BV(37),  //PEK press falling edge, IRQ enable
+    XPOWERS_AXP202_PKEY_POSITIVE_IRQ        = _BV(38),  //PEK press rising edge, IRQ enable
+    XPOWERS_AXP202_TIMER_TIMEOUT_IRQ        = _BV(39),  //Timer timeout, IRQ enable
+
+    XPOWERS_AXP202_ALL_IRQ                  = (0xFFFFFFFFFFULL)
+} xpowers_axp202_irq_t;
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buildroot/package/axp2101/src/include/main.h

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+#pragma once
+
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