* add vsftpd & lftp package

i2c: fix stack buffer overflow vulnerability in i2c md command

.gitignore

@@ -3,7 +3,9 @@
 *.o
 *.ko
 *.d
+!init.d
 host-tools/
+host-tools
 *.sqfs
 build/tools/common/sd_tools/genimage.cfg.tmp
 fsbl/build/*
@@ -419,3 +421,4 @@ osdrv/extdrv/wireless/.tmp_4261/
 middleware/v2/lib
 host-tools/
 kvm/
+.vscode*

build/boards/default/dts/sg200x/soph_base.dtsi

@@ -233,6 +233,7 @@
 		clocks = <&clk CV181X_CLK_SPI>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		bias-pull-up;
 	};
 
 	spi3:spi3@041B0000 {

build/boards/sg200x/sg2002_licheervnano_sd/dts_riscv/sg2002_licheervnano_sd.dts

@@ -145,6 +145,23 @@
 
 &spi2 {
 	status = "okay";
+
+        // /delete-node/ spidev@0;
+        st7789: st7789@0{
+		compatible = "sitronix,st7789";
+		reg = <0>;
+		status = "disabled";
+		spi-max-frequency = <80000000>;
+		spi-cpol;
+		spi-cpha;
+		rotate = <0>;
+		fps = <60>;
+		rgb;
+		buswidth = <8>;
+		dc = <&porte 20 GPIO_ACTIVE_HIGH>;
+		reset = <&porta 14 GPIO_ACTIVE_LOW>;
+		debug = <0>;
+	};
 };
 
 &spi3 {
@@ -231,12 +248,12 @@
                 reg_names = "core_mem";
                 src-frequency = <375000000>;
                 min-frequency = <400000>; // 400Khz
-                max-frequency = <50000000>; // 50Mhz
+                //max-frequency = <50000000>; // 50Mhz
                 //max-frequency = <45000000>; // 45Mhz
                 //max-frequency = <40000000>; // 40Mhz
                 //max-frequency = <35000000>; // 35Mhz
                 //max-frequency = <30000000>; // 30Mhz
-                //max-frequency = <25000000>; // 25Mhz
+                max-frequency = <25000000>; // 25Mhz
                 //max-frequency = <20000000>; // 20Mhz
                 //max-frequency = <15000000>; // 15Mhz
                 //max-frequency = <10000000>; // 10Mhz

build/boards/sg200x/sg2002_licheervnano_sd/linux/sg2002_licheervnano_sd_defconfig

@@ -357,6 +357,8 @@ CONFIG_VIDEO_CVITEK_MIPI_TX=m
 # end of Digital TV options
 
 CONFIG_FB=y
+# CONFIG_FB_TFT is not set
+# CONFIG_FB_TFT_ST7789 is not set
 CONFIG_FB_CVITEK=m
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -365,7 +367,9 @@ CONFIG_SND=y
 # CONFIG_SND_DRIVERS is not set
 CONFIG_SND_HDA_PREALLOC_SIZE=1
 # CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
 CONFIG_SND_SOC=y
 CONFIG_SND_SOC_CV182XA_CV182XAADC=y
 CONFIG_SND_SOC_CV182XA_CV182XADAC=y
@@ -534,6 +538,8 @@ CONFIG_KEYBOARD_GPIO=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_HYNITRON_TS=y
 CONFIG_MAGIC_SYSRQ=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
 # CONFIG_MAGIC_SYSRQ_SERIAL is not set
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
@@ -556,6 +562,7 @@ CONFIG_VT=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=m
 CONFIG_BACKLIGHT_PWM=m
 CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
 CONFIG_SPI_DESIGNWARE=y
 CONFIG_SPI_DW_MMIO=y
 CONFIG_SPI_GPIO=m
@@ -1002,4 +1009,4 @@ CONFIG_USB_SERIAL=y
 CONFIG_USB_SERIAL_OPTION=y
 CONFIG_USB_ACM=y
 
-CONFIG_VETH=y
+CONFIG_VETH=y

build/boards/sg200x/sg2002_licheervnano_sd/partition/partition_sd.xml

@@ -1,4 +1,4 @@
 <physical_partition type="sd">
     <partition label="BOOT" size_in_kb="80960" readonly="false" file="boot.sd"/>
-    <partition label="ROOTFS" size_in_kb="1126400" readonly="false" file="rootfs.sd" />
+    <partition label="ROOTFS" size_in_kb="1638400" readonly="false" file="rootfs.sd" />
 </physical_partition>

build/boards/sg200x/sg2002_licheervnano_sd/u-boot/cvi_board_init.c

@@ -88,6 +88,14 @@ int cvi_board_init(void)
         mmio_write_32(0x030010E0, 0x0); // CMD
         mmio_write_32(0x030010E4, 0x0); // CLK
 
+        // spi2 pinmux
+        // mmio_write_32(0x030010D0, 0x1); // CS
+        // mmio_write_32(0x030010DC, 0x1); // MISO
+        // mmio_write_32(0x030010E0, 0x1); // MOSI
+        // mmio_write_32(0x030010E4, 0x1); // SCK
+        // mmio_write_32(0x030010D8, 0x3); // DC
+        // mmio_write_32(0x03001038, 0x3); // RESET
+
         // uart bluetooth
         mmio_write_32(0x03001070, 0x1); // GPIOA 28 UART1 TX
         mmio_write_32(0x03001074, 0x1); // GPIOA 29 UART1 RX

buildroot/board/cvitek/SG200X/overlay/etc/adbd_monitor.sh

@@ -0,0 +1,15 @@
+#!/bin/bash
+
+UDC_PATH=/sys/kernel/config/usb_gadget/g0/UDC
+if [ -f /boot/usb.adbd ] && [ -f /boot/usb.dev ];
+then
+    while true; do
+        if [ -z "$(cat $UDC_PATH | tr -d '[:space:]')" ];
+        then
+            echo "try restart usb device"
+            /etc/init.d/S03usbdev stop
+            /etc/init.d/S03usbdev start
+        fi
+        sleep 5
+    done
+fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S00kmod

@@ -7,8 +7,8 @@ then
 	cd /mnt/system/ko/
 	insmod soph_sys.ko
 	insmod soph_base.ko
-	insmod soph_rtos_cmdqu.ko
-	insmod soph_fast_image.ko
+	insmod soph_rtos_cmdqu.ko # optional for RTOS core
+	insmod soph_fast_image.ko # optional for RTOS core
 	insmod soph_mipi_rx.ko
 	insmod soph_snsr_i2c.ko
 	insmod soph_vi.ko
@@ -17,18 +17,14 @@ then
 	insmod soph_vo.ko
 #	insmod soph_mipi_tx.ko
 	insmod soph_rgn.ko
-	insmod soph_wdt.ko
-	insmod soph_clock_cooling.ko
 	insmod soph_tpu.ko
 	insmod soph_vcodec.ko
 	insmod soph_jpeg.ko
 	insmod soph_vc_driver.ko MaxVencChnNum=9 MaxVdecChnNum=9
-	insmod soph_rtc.ko
 	insmod soph_ive.ko
-	insmod soph_mon.ko
 	insmod soph_pwm.ko
 	insmod soph_saradc.ko
-	insmod soph_wiegand.ko
+#	insmod soph_wiegand.ko # uncomment it if want use wiegand
 	echo "OK"
 	exit 0
 fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S00pmu

@@ -1,31 +1,62 @@
 #!/bin/sh
 
-if ! command -v i2cget &> /dev/null
-then
-    echo "i2cdetect not find, please install i2c-tools"
-    exit 1
-fi
+PMU_BUS=4
+PMU_ADDR=0x34
+PMU_REG_VER=0x03
 
-pmu_version=$(i2cget -y 4 0x34 0x03)
-pmu_version=$((pmu_version & 0xCF))
+pmu_detected() {
+    pmu_version=$(i2cget -y "$PMU_BUS" "$PMU_ADDR" "$PMU_REG_VER" 2>/dev/null)
+    if [ $? -ne 0 ]; then
+        return 1
+    fi
 
-chip_id_1=$(printf "%d" 0x47)
-chip_id_2=$(printf "%d" 0x4a)
+    pmu_version=$((pmu_version & 0xCF))
+    chip_id_1=$((0x47))
+    chip_id_2=$((0x4a))
 
-if [ "$pmu_version" -eq "$chip_id_1" ] || [ "$pmu_version" -eq "$chip_id_2" ]; then
-    case "$1" in
-    start)
+    if [ "$pmu_version" -eq "$chip_id_1" ] || [ "$pmu_version" -eq "$chip_id_2" ]; then
+        return 0
+    else
+        return 1
+    fi
+}
+
+start() {
+    # if ! command -v i2cget &> /dev/null; then
+    #     echo "i2cget not found, please install i2c-tools"
+    #     exit 1
+    # fi
+
+    if pmu_detected; then
         exec /usr/bin/axp2101
-        echo "Starting PMU: OK\n"
-    ;;
-    stop)
+    else
+        echo "No PMU, skip"
+    fi
+}
+
+stop() {
+    if pmu_detected; then
         runlevel=$(cat /run/runlevel | awk '{ print $1 }')
         if [ "$runlevel" = "0" ]; then
-            printf "Stopping PMU\n"
-            value=$(i2cget -y 4 0x34 0x10)
+            echo "Stopping PMU"
+            value=$(i2cget -y "$PMU_BUS" "$PMU_ADDR" 0x10)
             value=$((value | 0x01))
-            i2cset -y 4 0x34 0x10 $value
+            i2cset -y "$PMU_BUS" "$PMU_ADDR" 0x10 $value
         fi
-    ;;
-    esac
-fi
+    else
+        echo "No PMU, skip"
+    fi
+}
+
+case "$1" in
+    start)
+        start
+        ;;
+    stop)
+        stop
+        ;;
+    *)
+        echo "Usage: $0 {start|stop}"
+        exit 1
+        ;;
+esac

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S01fs

@@ -6,7 +6,5 @@ then
 	printf "mounting filesystem : "
 	mkdir -p /boot
 	mount -t vfat /dev/mmcblk0p1 /boot
-	mount -t configfs configfs /sys/kernel/config
-	mount -t debugfs debugfs /sys/kernel/debug
 	echo "OK"
 fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S02devicekey

@@ -0,0 +1,13 @@
+#!/bin/sh
+
+if [ "$1" = "start" ]
+then
+	str_value=$(cat /sys/class/cvi-base/base_uid | awk '{print $2}')
+	first_uint=$(echo $str_value | cut -d'_' -f1)
+	second_uint=$(echo $str_value | cut -d'_' -f2)
+	result="$first_uint$second_uint"
+	echo $result > /device_key
+	# for compatibility with previous network mac addr
+	cat /sys/class/cvi-base/base_uid > /device_key_legacy
+fi
+

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S04backlight

@@ -2,7 +2,7 @@
 
 if [ "$1" = "start" ]
 then
-	. /etc/profile
+	# . /etc/profile
 	if [ ! -e /boot/alpha ]
 	then
 		devmem 0x030010AC 32 0x04 # PINMUX PWM10
@@ -13,17 +13,19 @@ then
 		fi
 		echo 0 > $blpwm/enable
 		echo "10000" > ${blpwm}/period # 100KHZ
-		if [ -e /boot/uEnv.txt ]
+		panel_value=""
+		if [ -e /boot/board ]
 		then
-			hd22800=$(cat /boot/uEnv.txt | grep hd228001c31 | wc -l)
-			if [ "${hd22800}" -ne 0 ]
-			then
-				echo "2000" > ${blpwm}/duty_cycle # 20%
-			else
-				echo "9500" > ${blpwm}/duty_cycle
-			fi
+			panel_value=$(grep '^panel=' /boot/board | cut -d '=' -f 2)
+		elif [ -e /boot/uEnv.txt ]
+		then
+			panel_value=$(grep '^panel=' /boot/uEnv.txt | cut -d '=' -f 2)
+		fi
+		if [ "$panel_value" = "st7701_hd228001c31" ]  || [ "$panel_value" = "st7701_lct024bsi20" ]
+		then
+			echo "2000" > ${blpwm}/duty_cycle # 20%
 		else
-			echo "9500" > ${blpwm}/duty_cycle
+			echo "5000" > ${blpwm}/duty_cycle
 		fi
 		echo 1 > $blpwm/enable
 	fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S05tp

@@ -3,17 +3,24 @@
 if [ "$1" = "start" ]
 then
 	. /etc/profile
-	panel_value=$(grep '^panel=' /boot/uEnv.txt | cut -d '=' -f 2)
-	if [ "$panel_value" = "st7701_lct024bsi20" ]
+	panel_value=""
+	if [ -e /boot/board ]
+	then
+		panel_value=$(grep '^panel=' /boot/board | cut -d '=' -f 2)
+	elif [ -e /boot/uEnv.txt ]
+	then
+		panel_value=$(grep '^panel=' /boot/uEnv.txt | cut -d '=' -f 2)
+	fi
+	if [ "$panel_value" = "st7701_lct024bsi20" ] # MaixCAM-Pro
 	then
 		echo "load cst7xx touchscreen driver"
 		insmod /mnt/system/ko/hynitron_touch_new.ko
-	elif [ "$panel_value" = "st7701_hd228001c31" ]
+	elif [ "$panel_value" = "st7701_hd228001c31" ] # MaixCAM
 	then
 		echo "load cst3xx touchscreen driver"
 		insmod /mnt/system/ko/hynitron_touch.ko
 	fi
-	if [ -e /boot/gt9xx ]
+	elif [ "$panel_value" = "mtd700920b" ] # 7-inch touchscreen
 	then
 		echo "load gt9xx touchscreen driver"
 		insmod /mnt/system/ko/3rd/gt9xx.ko

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S07fs2

@@ -0,0 +1,10 @@
+#!/bin/sh
+
+if [ "$1" = "start" ]
+then
+	. /etc/profile
+	printf "mounting filesystem : "
+	mount -t configfs configfs /sys/kernel/config
+	mount -t debugfs debugfs /sys/kernel/debug
+	echo "OK"
+fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S07kmod2

@@ -0,0 +1,14 @@
+#!/bin/sh
+
+if [ "$1" = "start" ]
+then
+	. /etc/profile
+	printf "load kernel module: "
+	cd /mnt/system/ko/
+	insmod soph_wdt.ko
+	insmod soph_clock_cooling.ko
+	insmod soph_rtc.ko
+	insmod soph_mon.ko
+	echo "OK"
+	exit 0
+fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S08usbdev

@@ -76,6 +76,13 @@ then
 			echo 'licheervnano' > strings/0x409/product
 		fi
 		mkdir -p configs/c.1
+		# uvc
+		if [ -e /boot/usb.uvc ]
+		then
+			/etc/init.d/uvc_tool.sh mount /boot/usb.uvc
+			/etc/init.d/uvc_tool.sh server
+		fi
+
 		if [ -e /boot/usb.GS0 ]
 		then
 			mkdir -p functions/acm.GS0
@@ -161,13 +168,54 @@ then
 			ln -s functions/hid.GS2 configs/c.1
 		fi
 
-		ls /sys/class/udc/ | cat > UDC
+		# adbd
+		if [ -e /boot/usb.adbd ]
+		then
+			echo 0x18d1 > idVendor  # google
+			mkdir -p configs/c.1/strings/0x409
+			echo "" > configs/c.1/strings/0x409/configuration
+			echo 0x80 > configs/c.1/bmAttributes
+			mkdir functions/ffs.adb
+			ln -s functions/ffs.adb configs/c.1/
+			mkdir -p /dev/usb-ffs/adb
+			mount -t functionfs adb /dev/usb-ffs/adb/
+			/usr/bin/adbd &
+			for i in $(seq 1 40); do
+				if [ -e /dev/usb-ffs/adb/ep2 ]; then
+					break
+				fi
+				sleep 0.1
+			done
+		fi
+		while true; do
+			ls /sys/class/udc/ | cat > UDC || true
+			res=$(cat UDC)
+			if [[ "x$res" != "x" ]]; then
+				break
+			fi
+			sleep 0.4
+		done
 		echo device > /proc/cviusb/otg_role
+
+        if [ -e /boot/usb.adbd ]
+        then
+            if [ -z $(ps aux | grep adbd_monitor | grep -v grep) ]; then
+                /etc/adbd_monitor.sh &
+            fi
+        fi
 	fi
 fi
 
 if [ "$1" = "stop" ]
 then
+	echo '' > /sys/kernel/config/usb_gadget/g0/UDC
+	echo host > /proc/cviusb/otg_role
+	# uvc
+	if [ -e /sys/kernel/config/usb_gadget/g0/configs/c.1/uvc.usb0 ]
+	then
+		/etc/init.d/uvc_tool.sh unmount
+	fi
+
 	# rndis
 	if [ -e /sys/kernel/config/usb_gadget/g0/configs/c.1/rndis.usb0 ]
 	then
@@ -181,7 +229,16 @@ then
 		unlink /sys/kernel/config/usb_gadget/g0/configs/c.1/ncm.usb0
 		rmdir /sys/kernel/config/usb_gadget/g0/functions/ncm.usb0
 	fi
-	echo '' > /sys/kernel/config/usb_gadget/g0/UDC
-	echo host > /proc/cviusb/otg_role
+
+    # adbd
+     if [ -e /sys/kernel/config/usb_gadget/g0/configs/c.1/ffs.adb ]
+     then
+        adbd_pid=$(ps aux | grep '/usr/bin/adbd' | grep -v grep | awk '{print $1}')
+        kill -15 $adbd_pid
+        umount /dev/usb-ffs/adb
+        rm /dev/usb-ffs/adb -rf
+        unlink /sys/kernel/config/usb_gadget/g0/configs/c.1/ffs.adb
+        rmdir /sys/kernel/config/usb_gadget/g0/functions/ffs.adb
+     fi
 fi
 

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S10uuid

@@ -19,7 +19,7 @@ then
 		prefix=$(cat /boot/hostname.prefix)
 	fi
 	old_hostname=$(cat /etc/hostname)
-	new_hostname=${prefix}-$(sha512sum /sys/class/cvi-base/base_uid | head -c 4)
+	new_hostname=${prefix}-$(sha512sum /device_key_legacy | head -c 4)
 
 	if [ -e /boot/hostname ]
 	then
@@ -38,7 +38,7 @@ then
 	then
 		new_ethmac=$(cat /boot/ethmac)
 	else
-		new_ethmac=$(hex2mac 48da356f$(sha512sum /sys/class/cvi-base/base_uid | head -c 4))
+		new_ethmac=$(hex2mac 48da356f$(sha512sum /device_key_legacy  | head -c 4))
 	fi
 
 	ifconfig eth0 down

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S30gadget_nic

@@ -0,0 +1,176 @@
+#!/bin/sh
+
+. /etc/profile
+
+gen_udhcpd_conf() {
+	interface=${1}
+	ipv4_prefix=${2}
+	echo "start ${ipv4_prefix}.100"
+	echo "end ${ipv4_prefix}.200"
+	echo "interface ${interface}"
+	echo "pidfile /var/run/udhcpd.${interface}.pid"
+	echo "lease_file /var/lib/misc/udhcpd.${interface}.leases"
+	echo "option subnet 255.255.255.0"
+	echo "option lease 864000"
+}
+
+hex2mac() {
+	MAC=""
+	seq 2 2 12 | while read i
+	do
+		echo -n ${1} | head -c $i | tail -c 2
+		if [ $i != 12 ]
+		then
+			echo -n ':'
+		fi
+	done | tr '[:upper:]' '[:lower:]'
+}
+
+start() {
+	# S03usbdev start first
+	if [ -e /boot/usb.dev ]
+	then
+		rndis_ifname=usb0
+		# RNDIS
+		if [ -e /boot/usb.rndis ]
+		then
+			# mac
+			if [ -e /boot/usb.rndis.mac ]
+			then
+				new_rndismac=$(cat /boot/usb.rndis.mac)
+			else
+				new_rndismac=$(hex2mac 48da356f$(sha512sum /device_key_legacy | head -c 4))
+			fi
+			ip link set $rndis_ifname address ${new_rndismac}
+			ifconfig $rndis_ifname up
+			echo "rndis mac address: ${new_rndismac}"
+
+			# dhcp
+			if [ ! -e /boot/rndis.nodhcpd ]
+			then
+				if [ -e /boot/rndis.ipv4_prefix ]
+				then
+					ipv4_prefix=`cat /boot/rndis.ipv4_prefix`
+				else
+					id2=$(printf "%d" 0x$(sha512sum /device_key_legacy | head -c 2))
+					id3=$(printf "%d" 0x$(sha512sum /device_key_legacy | head -c 4 | tail -c 2))
+					id3=$((id3 + 1))
+					if [ "$id2" = "$id3" ]
+					then
+						id2=$((id2 + 2))
+					fi
+					if [ "$id2" -ge 255 ]
+					then
+						id2=252
+					fi
+					if [ "$id3" -ge 255 ]
+					then
+						id3=251
+					fi
+					ipv4_prefix=10.$id2.$id3
+				fi
+				gen_udhcpd_conf $rndis_ifname "${ipv4_prefix}"  > /etc/udhcpd.${rndis_ifname}.conf
+				ip addr add $ipv4_prefix.1/24 dev $rndis_ifname
+				udhcpd -S /etc/udhcpd.${rndis_ifname}.conf
+			fi
+			echo "RNDIS DHCP OK"
+			rndis_ifname=usb1
+		fi
+
+		# CDC NCM
+		if [ -e /boot/usb.ncm ]
+		then
+			# mac
+			if [ -e /boot/usb.ncm.mac ]
+			then
+				new_mac=$(cat /boot/usb.ncm.mac)
+			else
+				new_mac=$(hex2mac 48da356e$(sha512sum /device_key_legacy | head -c 4))
+			fi
+			ip link set $rndis_ifname address ${new_mac}
+			ifconfig $rndis_ifname up
+			echo "ncm mac address: ${new_mac}"
+
+			# dhcp
+			if [ ! -e /boot/ncm.nodhcpd ]
+			then
+				if [ -e /boot/ncm.ipv4_prefix ]
+				then
+					ipv4_prefix=`cat /boot/ncm.ipv4_prefix`
+				else
+					id2=$(printf "%d" 0x$(sha512sum /device_key_legacy | head -c 2))
+					id3=$(printf "%d" 0x$(sha512sum /device_key_legacy | head -c 4 | tail -c 2))
+					if [ "$id2" = "$id3" ]
+					then
+						id2=$((id2 + 1))
+					fi
+					if [ "$id2" -ge 255 ]
+					then
+						id2=253
+					fi
+					if [ "$id3" -ge 255 ]
+					then
+						id3=254
+					fi
+					ipv4_prefix=10.$id2.$id3
+				fi
+				gen_udhcpd_conf $rndis_ifname "${ipv4_prefix}"  > /etc/udhcpd.${rndis_ifname}.conf
+				ip addr add $ipv4_prefix.1/24 dev $rndis_ifname
+				udhcpd -S /etc/udhcpd.${rndis_ifname}.conf
+			fi
+			echo "CDC NCM DHCP OK"
+		fi
+	fi
+}
+
+stop() {
+	# first card
+	if [ -e /var/run/udhcpd.usb0.pid ]
+	then
+		kill $(cat "/var/run/udhcpd.usb0.pid")
+		rm /var/run/udhcpd.usb0.pid || true
+	fi
+	pnum=$(ps -ef|grep udhcpd|grep -v grep| grep udhcpd.usb0.conf | awk '{print $1}' | wc -l)
+	if [ x$pnum != x0 ]
+	then
+		ps -ef|grep udhcpd|grep -v grep| grep udhcpd.usb0.conf | awk '{print $1}'|xargs kill -2 || true
+	fi
+	usb0_info=$(ip link |grep usb0)
+	if [ -n "$usb0_info" ]
+	then
+		ifconfig usb0 down
+	fi
+
+	# second card
+	if [ -e /var/run/udhcpd.usb1.pid ]
+	then
+		kill $(cat /var/run/udhcpd.usb1.pid)
+		rm /var/run/udhcpd.usb1.pid || true
+	fi
+	pnum=$(ps -ef|grep udhcpd|grep -v grep| grep udhcpd.usb1.conf | awk '{print $1}' | wc -l)
+	if [ x$pnum != x0 ]
+	then
+		ps -ef|grep udhcpd|grep -v grep| grep udhcpd.usb1.conf | awk '{print $1}'|xargs kill -2 || true
+	fi
+	usb0_info=$(ip link |grep usb1)
+	if [ -n "$usb0_info" ]
+	then
+		ifconfig usb1 down
+	fi
+}
+
+restart() {
+	stop
+	start
+}
+
+if [ "${1}" = "start" ]
+then
+	start
+elif [ "${1}" = "stop" ]
+then
+	stop
+elif [ "${1}" = "restart" ]
+then
+	restart
+fi

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S30wifi

@@ -76,8 +76,8 @@ start() {
 		then
 			cp /boot/hostapd.conf /etc/hostapd.conf
 		else
-			id2=$(printf "%d" 0x$(sha512sum /sys/class/cvi-base/base_uid | head -c 2))
-			id3=$(printf "%d" 0x$(sha512sum /sys/class/cvi-base/base_uid | head -c 4 | tail -c 2))
+			id2=$(printf "%d" 0x$(sha512sum /device_key_legacy | head -c 2))
+			id3=$(printf "%d" 0x$(sha512sum /device_key_legacy | head -c 4 | tail -c 2))
 			if [ "$id2" = "$id3" ]
 			then
 				id2=$((id2 + 1))

buildroot/board/cvitek/SG200X/overlay/etc/init.d/S99temptest

@@ -27,8 +27,8 @@ case "$1" in
 	    fi
 	    echo "soc temp: $soc_temp" | fbbar 32 $colorfg $colorbg
 	    colorfg=0xFFFFFFFF
-            echo "soc id: $(cat /sys/class/cvi-base/base_uid)" | fbbar 48 $colorfg $colorbg
-            sleep 1
+      echo "soc id: $(cat /device_key_legacy)" | fbbar 48 $colorfg $colorbg
+      sleep 1
     done
     ) &
     [ $? = 0 ] && echo "OK" || echo "FAIL"

buildroot/board/cvitek/SG200X/overlay/etc/init.d/uvc_tool.sh

@@ -0,0 +1,274 @@
+#! /bin/sh
+
+# 支持的格式，可以通过修改这个变量自定义支持的格式
+# Supported formats, you can customize the list by modifying this variable
+supported_formats="yuyv mjpg"
+
+# 支持的分辨率，可以通过修改这个变量自定义支持的分辨率
+# Supported resolutions, you can customize the list by modifying this variable
+supported_resolutions="480x320 640x360 640x480 1280x720 1920x1080 2560x1440"
+
+
+parse_uvc_config() {
+	input_file="$1"  # 传入的文件路径 / Path to the input file
+	parsed_data=""  # 初始化 parsed_data 为空 / Initialize parsed_data as empty
+
+	# 检查文件是否存在并可读取 / Check if the file exists and is readable
+	if [ -z "$input_file" ]; then
+		# 没有提供文件路径 / No input file provided
+		echo "Warn: No input file provided for config." 1>&2  # 输出到标准错误 / Output to stderr
+	elif [ ! -f "$input_file" ]; then
+		# 文件不存在 / File does not exist
+		echo "Warn: File '$input_file' does not exist." 1>&2  # 输出到标准错误 / Output to stderr
+	elif [ ! -r "$input_file" ]; then
+		# 文件不可读取 / File is not readable
+		echo "Warn: File '$input_file' is not readable." 1>&2  # 输出到标准错误 / Output to stderr
+	else
+		# 使用 awk 处理文件内容 / Using awk to process the file content
+		parsed_data=$(awk -v resolutions="$supported_resolutions" -v formats="$supported_formats" '
+		BEGIN {
+			OFS = " ";
+			split(resolutions, supported_res, " ");  # 将支持的分辨率放入数组 / Split the supported resolutions into an array
+			split(formats, supported_fmt, " ");  # 将支持的格式放入数组 / Split the supported formats into an array
+		}
+		/^[^#]/ {  # 只处理非 # 开头的行 / Process lines that do not start with #
+			fmt = $1;
+			res = $2;
+
+			# 检查格式是否在支持的格式列表中 / Check if the format is in the supported formats list
+			is_supported_fmt = 0;
+			for (i in supported_fmt) {
+				if (fmt == supported_fmt[i]) {
+					is_supported_fmt = 1;
+					break;
+				}
+			}
+			if (!is_supported_fmt) {
+				print "Unsupported format:", fmt > "/dev/stderr";  # 输出不支持的格式到标准错误 / Output unsupported format to stderr
+				next;
+			}
+
+			if (res ~ /^[0-9]+x[0-9]+$/) {  # 匹配 640x360/1280x720 这种格式 / Match the format like 640x360 or 1280x720
+				is_supported_res = 0;
+				for (i in supported_res) {
+					if (res == supported_res[i]) {
+						is_supported_res = 1;
+						break;
+					}
+				}
+				if (!is_supported_res) {
+					print "Unsupported resolution:", res > "/dev/stderr";  # 输出不支持的分辨率到标准错误 / Output unsupported resolution to stderr
+					next;
+				}
+				split(res, dims, "x");  # 将 1280x720 按 "x" 分割成宽高 / Split 1280x720 into width and height
+				w = dims[1];
+				h = dims[2];
+			} else {
+				print "Invalid resolution format:", res > "/dev/stderr";  # 输出无效的分辨率格式到标准错误 / Output invalid resolution format to stderr
+				next;
+			}
+			print fmt, w, h;  # 输出格式 fmt, w, h / Output fmt, w, h
+		}
+		' "$input_file")
+	fi
+
+	# 确保至少包含 'mjpg' 和 'yuyv' 格式 / Ensure at least one 'mjpg' and 'yuyv' format exists
+	has_mjpg=$(echo "$parsed_data" | grep -w "mjpg")
+	has_yuyv=$(echo "$parsed_data" | grep -w "yuyv")
+
+	if [ -z "$has_mjpg" ]; then
+		default_mjpg=$'\nmjpg 480x320\nmjpg 640x360\nmjpg 640x480\nmjpg 1280x720\nmjpg 1920x1080\nmjpg 2560x1440\n'
+        echo "Warn: No 'mjpg' config found, adding default: $default_mjpg" 1>&2
+		parsed_data="$parsed_data""$(echo "$default_mjpg" | sed 's/x/ /g')"
+	fi
+
+	if [ -z "$has_yuyv" ]; then
+		default_yuyv=$'\nyuyv 480x320\nyuyv 640x360\nyuyv 640x480\nyuyv 1280x720\nyuyv 1920x1080\nyuyv 2560x1440\n'
+        echo "Warn: No 'yuyv' config found, adding default: $default_yuyv" 1>&2
+		parsed_data="$parsed_data""$(echo "$default_yuyv" | sed 's/x/ /g')"
+	fi
+
+	parsed_data=$(echo "$parsed_data" | sed '/^$/d')  # 删除空行
+
+	echo "$parsed_data"  # 返回解析的数据 / Return the parsed data
+}
+
+
+
+
+##########################################################################
+# UVC
+
+CONFIGFS_PATH="/sys/kernel/config/usb_gadget/g0"
+ORIGINAL_DIR=$(pwd)  # 记录脚本启动时的目录 / Record the original working directory
+
+create_frame() {
+	# Example usage:
+	# create_frame <width> <height> <format name>
+
+	WIDTH=$1
+	HEIGHT=$2
+	FORMAT=$3
+
+	if [ "$FORMAT" == "yuyv" ]; then
+		wdir=streaming/uncompressed/u/${HEIGHT}p
+	elif [ "$FORMAT" == "mjpg" ]; then
+		wdir=streaming/mjpeg/m/${HEIGHT}p
+	else
+		echo "only support format yuyv/mjpeg!"
+		exit 1
+	fi
+
+	mkdir -p $wdir
+	echo $WIDTH > $wdir/wWidth
+	echo $HEIGHT > $wdir/wHeight
+	echo $(( $WIDTH * $HEIGHT * 2 )) > $wdir/dwMaxVideoFrameBufferSize
+	echo $(( $WIDTH * $HEIGHT * 2 * 8 * 5  )) > $wdir/dwMinBitRate
+	echo $(( $WIDTH * $HEIGHT * 2 * 8 * 60 )) > $wdir/dwMaxBitRate
+
+	cat > $wdir/dwFrameInterval <<EOF
+166666
+333333
+400000
+500000
+666666
+1000000
+2000000
+EOF
+	echo "333333" > $wdir/dwDefaultFrameInterval
+
+<< EOF
+    configure FrameRate
+    dwFrameInterfal is in 100-ns units (fps = 1/(dwFrameInterval * 10000000))
+      166666 -> 60 fps
+      333333 -> 30 fps
+      400000 -> 25 fps
+      500000 -> 20 fps
+      666666 -> 15 fps
+     1000000 -> 10 fps
+     2000000 ->  5 fps
+     5000000 ->  2 fps
+    10000000 ->  1 fps
+EOF
+}
+
+
+# 挂载 UVC ConfigFS / Mount the UVC ConfigFS
+mount_uvc_configfs() {
+	echo "Mounting UVC ConfigFS in $(pwd)"
+
+	# 创建 functions/uvc.usb0 目录 / Create the directory for uvc.usb0
+	mkdir -p functions/uvc.usb0
+	cd functions/uvc.usb0
+
+	# 在 functions/uvc.usb0 目录中创建控制头和符号链接 / Create control header and symlink it in uvc.usb0
+	mkdir -p control/header/h
+		ln -s control/header/h/ control/class/fs/
+		ln -s control/header/h/ control/class/ss/
+
+	# streaming_maxpacket sets wMaxPacketSize. Valid values are 1024/2048/3072
+	echo 1024 > streaming_maxpacket
+	# streaming_interval sets bInterval. Values range from 1..255
+	echo 1 > streaming_interval
+	# streaming_maxburst sets bMaxBurst. Valid values are 1..15
+	echo 1 > streaming_maxburst
+
+	# 在 functions/uvc.usb0 目录中创建流媒体路径 / Create streaming paths in uvc.usb0
+	mkdir -p streaming/uncompressed/u  # YUV 目录 / YUV directory
+	mkdir -p streaming/mjpeg/m         # MJPEG 目录 / MJPEG directory
+		# 执行解析并直接传递给 while 循环进行处理 / Execute parsing and directly pass to while loop for processing
+		parse_uvc_config "$1" | while read fmt w h; do
+			echo "Adding: Format: $fmt, Width: $w, Height: $h"  # 输出格式、宽和高 / Output fmt, width, and height
+			create_frame $w $h $fmt
+		done
+	mkdir -p streaming/header/h
+		# 将 YUV 和 MJPEG 目录链接到流媒体头中 / Link YUV and MJPEG to streaming header
+		ln -s streaming/uncompressed/u/ streaming/header/h/
+		ln -s streaming/mjpeg/m/ streaming/header/h/
+		# 将 header 链接到 class 中 / Link header to classes
+		ln -s streaming/header/h/ streaming/class/fs
+		ln -s streaming/header/h/ streaming/class/hs
+		ln -s streaming/header/h/ streaming/class/ss
+
+	cd ../..
+	ln -s functions/uvc.usb0 configs/c.1
+
+    echo "UVC ConfigFS mounted successfully in $(pwd)"
+}
+
+# 卸载 UVC ConfigFS / Unmount the UVC ConfigFS
+unmount_uvc_configfs() {
+	echo "Unmounting UVC ConfigFS in $(pwd)"
+
+	unlink configs/c.1/uvc.usb0
+
+	cd functions/uvc.usb0
+
+	# 删除流媒体目录 / Remove streaming directories
+	unlink streaming/class/fs/h
+	unlink streaming/class/hs/h
+	unlink streaming/class/ss/h
+
+	unlink streaming/header/h/u
+	unlink streaming/header/h/m
+	rmdir streaming/header/h
+
+	rmdir streaming/uncompressed/u/*p
+	rmdir streaming/mjpeg/m/*p
+	rmdir streaming/uncompressed/u
+	rmdir streaming/mjpeg/m
+
+	unlink control/class/fs/h
+	unlink control/class/ss/h
+	rmdir control/header/h
+
+	cd ../..
+	# 删除 functions/uvc.usb0 目录 / Remove the uvc.usb0 directory
+	rmdir functions/uvc.usb0
+
+	echo UVC ConfigFS unmounted successfully in $(pwd)
+}
+
+# 进入工作目录 / Enter the working directory
+cd "$CONFIGFS_PATH" || return 1
+
+# 处理传入的参数
+# Process the input arguments
+case "$1" in
+	"mount")
+		mount_uvc_configfs "$2"
+        ;;
+	"unmount")
+		unmount_uvc_configfs
+        ;;
+	"server")
+		if [ -z "$(fuser /etc/init.d/uvc-gadget-server.elf)" ]; then
+			(	
+				echo "Waiting for UDC start..."
+				while [ -z "$(cat /sys/kernel/config/usb_gadget/g0/UDC)" ]; do
+					echo -n "."
+					sleep 1
+				done
+				sleep 3	# necessary delay time
+				if [ -z "$(fuser /etc/init.d/uvc-gadget-server.elf)" ]; then
+					echo -e "\nServer is starting..."  # 输出选择了 server 模式 / Output that the server mode is selected
+					echo -e "===============================\n\n\n"
+					# 在这里添加你希望在 server 模式下执行的其他操作 / Add other operations you want to perform in server mode here
+					/etc/init.d/uvc-gadget-server.elf  -u /dev/$(basename /sys/class/udc/*/device/gadget/video4linux/video*)  -d -i /bin/cat_224.jpg 
+				else
+					echo -e "\nServer has started..."
+					echo -e "===============================\n\n\n"
+				fi
+			) >/tmp/uvc-gadget.log 2>&1 &
+		fi
+	;;
+	"stop_server")
+		fuser -k /etc/init.d/uvc-gadget-server.elf
+	;;
+	*)
+		echo "Usage: $0 {mount <file>|unmount|server|stop_server}"  # 提示正确的使用方式 / Prompt the correct usage
+	;;
+esac
+
+# 返回原始目录 / Return to the original directory
+cd "$ORIGINAL_DIR" || return 1

buildroot/package/Config.in

@@ -1252,6 +1252,7 @@ menu "External python modules"
 	source "package/python-pyphen/Config.in"
 	source "package/python-pyqrcode/Config.in"
 	source "package/python-pyqt5/Config.in"
+	source "package/python-pyqt5-sip/Config.in"
 	source "package/python-pyratemp/Config.in"
 	source "package/python-pyroute2/Config.in"
 	source "package/python-pyrsistent/Config.in"

buildroot/package/aic8800-sdio-firmware/aic8800-sdio-firmware.mk

@@ -4,8 +4,8 @@
 #
 ################################################################################
 
-AIC8800_SDIO_FIRMWARE_VERSION = e44a51d3c129bbd7413848a430b8206556e923a5
-AIC8800_SDIO_FIRMWARE_SITE = $(call github,0x754C,aic8800-sdio-firmware,$(AIC8800_SDIO_FIRMWARE_VERSION))
+AIC8800_SDIO_FIRMWARE_VERSION = c56f910044cc854d6c553bcb9a644f3bca5a4c38
+AIC8800_SDIO_FIRMWARE_SITE = $(call github,lxowalle,aic8800-sdio-firmware,$(AIC8800_SDIO_FIRMWARE_VERSION))
 
 define AIC8800_SDIO_FIRMWARE_INSTALL_TARGET_CMDS
 	mkdir -pv $(TARGET_DIR)/usr/lib/firmware/aic8800_sdio/

buildroot/package/axp2101/axp2101.mk

@@ -4,7 +4,7 @@
 #
 ################################################################################
 
-AXP2101_VERSION = 1.0.0
+AXP2101_VERSION = 1.1.0
 AXP2101_SITE = $(TOPDIR)/package/axp2101/src
 AXP2101_SITE_METHOD = local
 AXP2101_CFLAGS = -Iinclude -IXPowersLib -IXPowersLib/REG -Wall -Wextra

buildroot/package/axp2101/src/Makefile

@@ -7,12 +7,10 @@ OBJ_O = $(patsubst %.cpp,${DIR_BIN}/%.o,$(notdir ${OBJ_C}))
 
 TARGET = axp2101
 
-DEBUG = -DXPOWERS_NO_ERROR
-
 $(shell mkdir -p $(DIR_BIN))
 
 MSG = -g -O0 -Wall 
-CFLAGS += $(MSG) $(DEBUG)
+CFLAGS += $(MSG)
 
 ${TARGET}:${OBJ_O}
 	$(CXX) $(CFLAGS) $(OBJ_O) -o $@ $(LIB)

buildroot/package/axp2101/src/XPowersLib/REG/AXP2101Constants.h

@@ -3,6 +3,7 @@
 #define AXP2101_SLAVE_ADDRESS                            (0x34)
 
 #define XPOWERS_AXP2101_CHIP_ID                          (0x4A)
+#define XPOWERS_AXP2101_CHIP_ID_2                        (0x47)
 
 #define XPOWERS_AXP2101_STATUS1                          (0x00)
 #define XPOWERS_AXP2101_STATUS2                          (0x01)

buildroot/package/axp2101/src/XPowersLib/XPowersAXP2101.tpp

@@ -234,7 +234,7 @@ public:
 
     ~XPowersAXP2101()
     {
-        log_i("~XPowersAXP2101");
+        // log_i("~XPowersAXP2101");
         deinit();
     }
 
@@ -3030,7 +3030,7 @@ protected:
 
     bool initImpl()
     {
-        if (getChipID() == XPOWERS_AXP2101_CHIP_ID) {
+        if (getChipID() == XPOWERS_AXP2101_CHIP_ID || getChipID() == XPOWERS_AXP2101_CHIP_ID_2) {
             setChipModel(XPOWERS_AXP2101);
             disableTSPinMeasure();      //Disable NTC temperature detection by default
             return true;
@@ -3045,7 +3045,7 @@ protected:
     {
         int res = 0;
         uint8_t data = 0, value = 0;
-        log_d("%s - HEX:0x%x \n", enable ? "ENABLE" : "DISABLE", opts);
+        // log_d("%s - HEX:0x%x \n", enable ? "ENABLE" : "DISABLE", opts);
         if (opts & 0x0000FF) {
             value = opts & 0xFF;
             // log_d("Write INT0: %x\n", value);

buildroot/package/axp2101/src/XPowersLib/XPowersLibInterface.hpp

@@ -616,6 +616,7 @@ public:
     virtual void setChargerTerminationCurr(uint8_t opt) = 0;
     virtual void disableDieOverTempDetect(void) = 0;
     virtual void resetGauge(void) = 0;
+    virtual void enableLongPressShutdown(void) = 0;
 
     // PMU PEKEY settings
     /**

buildroot/package/axp2101/src/src/main.cpp

@@ -13,6 +13,7 @@
 
 #define I2C_BUS                 (4)
 #define AXP2101_SLAVE_ADDRESS   (0x34)
+#define APP_VERSION             "1.1.0"
 
 int i2c_dev = -1;
 XPowersLibInterface *PMU = NULL;
@@ -44,6 +45,7 @@ static int set_i2c_slave(int file, int addr)
 int main(int argc, char* argv[])
 {
     bool log_enabled = false;
+    bool version_enabled = false;
 
     printf("PMU: Init axp2101 pmu\n");
 
@@ -82,8 +84,19 @@ int main(int argc, char* argv[])
         std::string arg = argv[i];
         if (arg == "--log" || arg == "-l") {
             log_enabled = true;
-            break;
+        } else if (arg == "--version" || arg == "-v") {
+            version_enabled = true;
         }
+        break;
+    }
+
+    if (version_enabled) {
+        std::cout << "version: " << APP_VERSION << std::endl;
+        if (PMU != nullptr) {
+            delete PMU;
+            PMU = NULL;
+        }
+        return 0;
     }
 
     if (log_enabled) {
@@ -222,6 +235,9 @@ int main(int argc, char* argv[])
     PMU->setPowerKeyPressOffTime(XPOWERS_POWEROFF_4S);
     // Set the button power-on press time
     PMU->setPowerKeyPressOnTime(XPOWERS_POWERON_128MS);
+    PMU->enableLongPressShutdown();
+    PMU->enableIRQ(XPOWERS_AXP2101_PKEY_POSITIVE_IRQ);
+    PMU->enableIRQ(XPOWERS_AXP2101_PKEY_NEGATIVE_IRQ);
 
     PMU->disableTSPinMeasure();
     PMU->enableVbusVoltageMeasure();

buildroot/package/python-pyqt5-sip/Config.in

@@ -0,0 +1,7 @@
+config BR2_PACKAGE_PYTHON_PYQT5_SIP
+	bool "python-pyqt5-sip"
+	help
+	  This is the PyQt5.sip module which is needed at runtime for
+	  the PyQt5 module from package python-pyqt5.
+
+	  https://pypi.org/project/PyQt5-sip/

buildroot/package/python-pyqt5-sip/python-pyqt5-sip.hash

@@ -0,0 +1,6 @@
+# From https://pypi.org/pypi/PyQt5-sip/json
+md5  9e0909e79f40619b0f2d3d3c33b4d4f7  PyQt5_sip-12.15.0.tar.gz
+sha256  d23fdfcf363b5cedd9d39f8a9c5710e7d52804f5b08a58e91c638b36eafcb702  PyQt5_sip-12.15.0.tar.gz
+
+# Locally calculated
+sha256  3859cfca971e429d6b79bdfeb1dc9e43aa9592f7295bf28fdd62824097909383  LICENSE

buildroot/package/python-pyqt5-sip/python-pyqt5-sip.mk

@@ -0,0 +1,24 @@
+################################################################################
+#
+# python-sip-qt5
+#
+################################################################################
+
+# Note about the package version:
+# This module version corresponds in fact to the "sip" ABI
+# version (not the version of its generator). See:
+# https://github.com/Python-SIP/sip/blob/6.8.6/sipbuild/module/source/12/sip.h.in#L43
+# The source git repository of this module is located at:
+# https://github.com/Python-SIP/sip/tree/main/sipbuild/module/source
+# The Python-SIP version/tag which generated a given "sip" module is
+# recorded in the PyPI source file "sip.h", in the SIP_VERSION_STR
+# macro. For example, PyQt5-sip 12.15.0 was generated with Python-SIP
+# 6.8.6.
+PYTHON_PYQT5_SIP_VERSION = 12.15.0
+PYTHON_PYQT5_SIP_SITE = https://files.pythonhosted.org/packages/1b/15/78318d50f10062c428e97e7ce387e772616a4673c356018b905f247a6a85
+PYTHON_PYQT5_SIP_SOURCE = PyQt5_sip-$(PYTHON_PYQT5_SIP_VERSION).tar.gz
+PYTHON_PYQT5_SIP_LICENSE = BSD-2-Clause
+PYTHON_PYQT5_SIP_LICENSE_FILES = LICENSE
+PYTHON_PYQT5_SIP_SETUP_TYPE = setuptools
+
+$(eval $(python-package))

host/make_logo.sh

@@ -1,48 +1,44 @@
-#!/bin/sh
+#!/bin/bash
 
-usage() {
-	echo "usage: $0 input output"
-	echo "output image must be logo.jpeg"
-	exit 1
-}
+# Check if the correct number of arguments is provided
+if [ "$#" -eq 2 ]; then
+    # Get input and output file paths
+    input_file="$1"
+    output_file="$2"
 
-src=${1}
-dst=${2}
-rm -rf ${dst}
+    # Use ffmpeg to convert the image to YUV420P format JPEG
+    ffmpeg -i "$input_file" -pix_fmt yuvj420p "$output_file"
+elif [ "$#" -eq 4 ]; then
+    # Get input and output file paths
+    input_file="$1"
+    output_file="$2"
+    output_width="$3"
+    output_height="$4"
 
-if [ -z ${dst} ]
-then
-	usage
+    # Use ffmpeg to convert the image to YUV420P format JPEG
+    ffmpeg -i "$input_file" -vf "scale=$output_width:$output_height" -pix_fmt yuvj420p "$output_file"
+elif [ "$#" -eq 5 ]; then
+    # Get input and output file paths
+    input_file="$1"
+    output_file="$2"
+    output_width="$3"
+    output_height="$4"
+    transpose="$5"
+
+    # Use ffmpeg to convert the image to YUV420P format JPEG
+    ffmpeg -i "$input_file" -vf "transpose=$transpose,scale=$output_width:$output_height" -pix_fmt yuvj420p "$output_file"
+else
+    echo "Usage: $0 <input file path> <output file path> <output width> <output height> <transpose>"
+    echo "example: $0 input.jpg logo.jpeg"
+    echo "example: $0 input.jpg logo.jpeg 640 480"
+    echo "example: $0 input.jpg logo.jpeg 640 480 3"
+    exit 1
 fi
 
-if [ ! -e ${src} ]
-then
-	usage
+# Check if the conversion was successful
+if [ $? -eq 0 ]; then
+    echo "The file has been successfully converted to YUV420P JPEG and saved to $output_file"
+else
+    echo "Conversion failed. Please check the input file path and ensure ffmpeg is installed."
+    exit 1
 fi
-
-
-get_picture_w() {
-	convert "${1}" -print "%w" /dev/null
-}
-
-get_picture_h() {
-	convert "${1}" -print "%h" /dev/null
-}
-
-W=$(get_picture_w ${src})
-H=$(get_picture_h ${src})
-
-echo "picture w : ${W}"
-echo "picture h : ${H}"
-
-picturetoyuv420p() {
-	ffmpeg -i ${1} -pix_fmt yuv420p ${2}
-}
-
-yuv420ptopicture() {
-	ffmpeg -pix_fmt yuv420p -s ${3}x${4} -i ${1} ${2}
-}
-
-picturetoyuv420p $src $dst
-yuv420ptopicture $src $dst $W $H
-

linux_5.10/drivers/i2c/busses/i2c-gpio.c

@@ -7,6 +7,7 @@
 #include <linux/completion.h>
 #include <linux/debugfs.h>
 #include <linux/delay.h>
+#include <linux/gpio.h>
 #include <linux/gpio/consumer.h>
 #include <linux/i2c-algo-bit.h>
 #include <linux/i2c.h>
@@ -18,6 +19,25 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/sysfs.h>
+#include <linux/kobject.h>
+#include <linux/err.h>
+
+#define DEBUG_LOG_TAG 			"[i2c gpio]"
+#define DEBUG_LOG(fmt, ...)		printk(KERN_DEBUG DEBUG_LOG_TAG " " fmt, ##__VA_ARGS__)
+
+static int delay_us = -1;
+volatile int udelay_value = 0;
+struct kobject *udelay_v;
+struct i2c_algo_bit_data *udelay_data = NULL;
+
+static int sda = -1;
+static int scl = -1;
+
+static bool insmod_gpio = false;
+
 struct i2c_gpio_private_data {
 	struct gpio_desc *sda;
 	struct gpio_desc *scl;
@@ -32,6 +52,49 @@ struct i2c_gpio_private_data {
 #endif
 };
 
+static void show_freq(void)
+{
+	switch(udelay_data->udelay) {
+	case 0:
+		DEBUG_LOG("Freq max ~ 750KHz for MaixCAM");
+		break;
+	case 1:
+		DEBUG_LOG("Freq 500KHz ~ 308KHz for MaixCAM");
+		break;
+	case 2:
+		DEBUG_LOG("Freq 250KHz");
+		break;
+	case 5:
+		DEBUG_LOG("Freq 100KHz");
+		break;
+	default:
+		DEBUG_LOG("Freq - Unknown");
+		break;
+	}
+}
+
+static ssize_t __udelay_show(struct kobject *kobj,
+                struct kobj_attribute *attr, char *buf)
+{
+    // DEBUG_LOG("Read udelay value: %d\n", udelay_value);
+	show_freq();
+	udelay_value = udelay_data->udelay;
+    return sprintf(buf, "%d", udelay_value);
+}
+
+static ssize_t __udelay_store(struct kobject *kobj,
+                struct kobj_attribute *attr,const char *buf, size_t count)
+{
+	// int old_value = udelay_value;
+    sscanf(buf,"%d",&udelay_value);
+	udelay_data->udelay = udelay_value;
+	// DEBUG_LOG("Write udelay value: %d --> %d\n", old_value, udelay_value);
+	// show_freq();
+    return count;
+}
+
+struct kobj_attribute sysfs_test_attr = __ATTR(udelay_v, 0664, __udelay_show, __udelay_store);
+
 /*
  * Toggle SDA by changing the output value of the pin. This is only
  * valid for pins configured as open drain (i.e. setting the value
@@ -362,8 +425,10 @@ static int i2c_gpio_probe(struct platform_device *pdev)
 	struct i2c_adapter *adap;
 	struct device *dev = &pdev->dev;
 	struct device_node *np = dev->of_node;
-	enum gpiod_flags gflags;
+	enum gpiod_flags gflags_sda, gflags_scl;
+	unsigned long gf_sda, gf_scl;
 	int ret;
+	struct device *curr_dev;
 
 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv)
@@ -384,6 +449,9 @@ static int i2c_gpio_probe(struct platform_device *pdev)
 			memcpy(pdata, dev_get_platdata(dev), sizeof(*pdata));
 	}
 
+	/* 508 SCL
+		509 SDA */
+
 	/*
 	 * First get the GPIO pins; if it fails, we'll defer the probe.
 	 * If the SCL/SDA lines are marked "open drain" by platform data or
@@ -392,21 +460,67 @@ static int i2c_gpio_probe(struct platform_device *pdev)
 	 * handle them as we handle any other output. Else we enforce open
 	 * drain as this is required for an I2C bus.
 	 */
-	if (pdata->sda_is_open_drain)
-		gflags = GPIOD_OUT_HIGH;
-	else
-		gflags = GPIOD_OUT_HIGH_OPEN_DRAIN;
-	priv->sda = i2c_gpio_get_desc(dev, "sda", 0, gflags);
-	if (IS_ERR(priv->sda))
-		return PTR_ERR(priv->sda);
+	if (sda >= 0 && scl >= 0) {
+		DEBUG_LOG("used sda %d and scl %d without device tree\n", sda, scl);
 
-	if (pdata->scl_is_open_drain)
-		gflags = GPIOD_OUT_HIGH;
-	else
-		gflags = GPIOD_OUT_HIGH_OPEN_DRAIN;
-	priv->scl = i2c_gpio_get_desc(dev, "scl", 1, gflags);
-	if (IS_ERR(priv->scl))
-		return PTR_ERR(priv->scl);
+		if (pdata->sda_is_open_drain) {
+			gf_sda = GPIOF_OUT_INIT_HIGH;
+		} else
+			gf_sda = GPIOF_OUT_INIT_HIGH | GPIOF_OPEN_DRAIN;
+
+		if (pdata->scl_is_open_drain)
+			gf_scl = GPIOF_OUT_INIT_HIGH;
+		else
+			gf_scl = GPIOF_OUT_INIT_HIGH | GPIOF_OPEN_DRAIN;
+
+		/* request sda */
+		ret = gpio_request_one(sda, gf_sda, "sda");
+		if (ret < 0) {
+			DEBUG_LOG("request sda failed!\n");
+			return -1;
+		}
+		priv->sda = gpio_to_desc(sda);
+		if (IS_ERR(priv->sda))
+			return PTR_ERR(priv->sda);
+		
+		DEBUG_LOG("request sda succ!\n");
+
+		/* request scl */
+		ret = gpio_request_one(scl, gf_scl, "scl");
+		if (ret < 0) {
+			DEBUG_LOG("request scl failed!\n");
+			DEBUG_LOG("release sda\n");
+			gpio_free(sda);
+			return -1;
+		}
+		priv->scl = gpio_to_desc(scl);
+		if (IS_ERR(priv->scl))
+			return PTR_ERR(priv->scl);
+
+		DEBUG_LOG("request scl succ!\n");
+
+		insmod_gpio = true;
+	} else {
+		if (pdata->sda_is_open_drain)
+			gflags_sda = GPIOD_OUT_HIGH;
+		else
+			gflags_sda = GPIOD_OUT_HIGH_OPEN_DRAIN;
+
+		if (pdata->scl_is_open_drain)
+			gflags_scl = GPIOD_OUT_HIGH;
+		else
+			gflags_scl = GPIOD_OUT_HIGH_OPEN_DRAIN;
+		DEBUG_LOG("used sda and scl with device tree\n");
+		priv->sda = i2c_gpio_get_desc(dev, "sda", 0, gflags_sda);
+		if (IS_ERR(priv->sda))
+			return PTR_ERR(priv->sda);
+
+		priv->scl = i2c_gpio_get_desc(dev, "scl", 1, gflags_scl);
+		if (IS_ERR(priv->scl))
+			return PTR_ERR(priv->scl);
+		
+		insmod_gpio = false;
+	}
 
 	if (gpiod_cansleep(priv->sda) || gpiod_cansleep(priv->scl))
 		dev_warn(dev, "Slow GPIO pins might wreak havoc into I2C/SMBus bus timing");
@@ -420,6 +534,9 @@ static int i2c_gpio_probe(struct platform_device *pdev)
 		bit_data->getscl = i2c_gpio_getscl;
 	bit_data->getsda = i2c_gpio_getsda;
 
+	udelay_data = bit_data;
+
+	/* Get udelay from device tree */
 	if (pdata->udelay)
 		bit_data->udelay = pdata->udelay;
 	else if (pdata->scl_is_output_only)
@@ -432,6 +549,17 @@ static int i2c_gpio_probe(struct platform_device *pdev)
 	else
 		bit_data->timeout = HZ / 10;		/* 100 ms */
 
+	/* If `insmod ko delay_us=x` (x>=0) */
+	if (delay_us >= 0) {
+		DEBUG_LOG("Get delay_us from insmod: %d\n", delay_us);
+		bit_data->udelay = delay_us;
+	} else {
+		DEBUG_LOG("Get delay_us from device tree: %d\n", bit_data->udelay);
+	}
+
+	DEBUG_LOG("delay us: %d\n", bit_data->udelay);
+	show_freq();
+
 	bit_data->data = priv;
 
 	adap->owner = THIS_MODULE;
@@ -464,6 +592,17 @@ static int i2c_gpio_probe(struct platform_device *pdev)
 
 	i2c_gpio_fault_injector_init(pdev);
 
+	/* Add udelay kobj */
+	curr_dev = &pdev->dev;
+	udelay_v = kobject_create_and_add("udelay_value", &curr_dev->kobj);
+	if(sysfs_create_file(udelay_v, &sysfs_test_attr.attr)){
+		DEBUG_LOG("Create sysfs file failed!\n");
+		kobject_put(udelay_v);
+        sysfs_remove_file(kernel_kobj, &sysfs_test_attr.attr);
+    }
+
+	udelay_value = udelay_data->udelay;
+
 	return 0;
 }
 
@@ -472,6 +611,11 @@ static int i2c_gpio_remove(struct platform_device *pdev)
 	struct i2c_gpio_private_data *priv;
 	struct i2c_adapter *adap;
 
+	if (insmod_gpio) {
+		gpio_free(scl);
+		gpio_free(sda);
+	}
+
 	i2c_gpio_fault_injector_exit(pdev);
 
 	priv = platform_get_drvdata(pdev);
@@ -479,6 +623,10 @@ static int i2c_gpio_remove(struct platform_device *pdev)
 
 	i2c_del_adapter(adap);
 
+	/* Remove udelay kobj */
+	kobject_put(udelay_v);
+    sysfs_remove_file(kernel_kobj, &sysfs_test_attr.attr);
+
 	return 0;
 }
 
@@ -500,6 +648,15 @@ static struct platform_driver i2c_gpio_driver = {
 	.remove		= i2c_gpio_remove,
 };
 
+module_param(delay_us, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(delay_us, "An integer parameter for the i2c udelay");
+
+module_param(sda, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(sda, "sda gpio");
+
+module_param(scl, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(scl, "scl gpio");
+
 static int __init i2c_gpio_init(void)
 {
 	int ret;

linux_5.10/drivers/media/usb/uvc/uvc_ctrl.c

@@ -743,7 +743,7 @@ static const struct uvc_control_mapping uvc_ctrl_mappings[] = {
 
 static inline u8 *uvc_ctrl_data(struct uvc_control *ctrl, int id)
 {
-	return ctrl->uvc_data + id * ctrl->info.size;
+	return ctrl->uvc_data + id * ALIGN(ctrl->info.size, 4);
 }
 
 static inline int uvc_test_bit(const u8 *data, int bit)
@@ -2024,7 +2024,7 @@ static int uvc_ctrl_add_info(struct uvc_device *dev, struct uvc_control *ctrl,
 	INIT_LIST_HEAD(&ctrl->info.mappings);
 
 	/* Allocate an array to save control values (cur, def, max, etc.) */
-	ctrl->uvc_data = kzalloc(ctrl->info.size * UVC_CTRL_DATA_LAST + 1,
+	ctrl->uvc_data = kzalloc(ALIGN(ctrl->info.size, 4) * UVC_CTRL_DATA_LAST + 1,
 				 GFP_KERNEL);
 	if (!ctrl->uvc_data)
 		return -ENOMEM;

linux_5.10/drivers/staging/fbtft/Kconfig

@@ -171,6 +171,16 @@ config FB_TFT_ST7735R
 	help
 	  Generic Framebuffer support for ST7735R
 
+config FB_TFT_ST7789
+	tristate "FB driver for the ST7789 LCD Controller"
+	depends on FB_TFT
+	help
+	  This enables generic framebuffer support for the Sitronix ST7789
+	  display controller. The controller is intended for small color
+	  displays with a resolution of up to 320x240 pixels.
+
+	  Say Y if you have such a display that utilizes this controller.
+
 config FB_TFT_ST7789V
 	tristate "FB driver for the ST7789V LCD Controller"
 	depends on FB_TFT

linux_5.10/drivers/staging/fbtft/Makefile

@@ -31,6 +31,7 @@ obj-$(CONFIG_FB_TFT_SSD1305)     += fb_ssd1325.o
 obj-$(CONFIG_FB_TFT_SSD1331)     += fb_ssd1331.o
 obj-$(CONFIG_FB_TFT_SSD1351)     += fb_ssd1351.o
 obj-$(CONFIG_FB_TFT_ST7735R)     += fb_st7735r.o
+obj-$(CONFIG_FB_TFT_ST7789)      += fb_st7789.o
 obj-$(CONFIG_FB_TFT_ST7789V)     += fb_st7789v.o
 obj-$(CONFIG_FB_TFT_TINYLCD)     += fb_tinylcd.o
 obj-$(CONFIG_FB_TFT_TLS8204)     += fb_tls8204.o

linux_5.10/drivers/staging/fbtft/fb_st7789.c

@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * FB driver for the ST7789 LCD Controller
+ *
+ * Copyright (C) 2015 Dennis Menschel
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <video/mipi_display.h>
+
+#include "fbtft.h"
+
+#define DRVNAME "fb_st7789"
+
+#define DEFAULT_GAMMA \
+	"70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25\n" \
+	"70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25"
+
+#define HSD20_IPS_GAMMA \
+	"D0 05 0A 09 08 05 2E 44 45 0F 17 16 2B 33\n" \
+	"D0 05 0A 09 08 05 2E 43 45 0F 16 16 2B 33"
+
+#define HSD20_IPS 1
+
+/**
+ * enum st7789_command - ST7789 display controller commands
+ *
+ * @PORCTRL: porch setting
+ * @GCTRL: gate control
+ * @VCOMS: VCOM setting
+ * @VDVVRHEN: VDV and VRH command enable
+ * @VRHS: VRH set
+ * @VDVS: VDV set
+ * @VCMOFSET: VCOM offset set
+ * @PWCTRL1: power control 1
+ * @PVGAMCTRL: positive voltage gamma control
+ * @NVGAMCTRL: negative voltage gamma control
+ *
+ * The command names are the same as those found in the datasheet to ease
+ * looking up their semantics and usage.
+ *
+ * Note that the ST7789 display controller offers quite a few more commands
+ * which have been omitted from this list as they are not used at the moment.
+ * Furthermore, commands that are compliant with the MIPI DCS have been left
+ * out as well to avoid duplicate entries.
+ */
+enum st7789_command {
+	PORCTRL = 0xB2,
+	GCTRL = 0xB7,
+	VCOMS = 0xBB,
+	VDVVRHEN = 0xC2,
+	VRHS = 0xC3,
+	VDVS = 0xC4,
+	VCMOFSET = 0xC5,
+	PWCTRL1 = 0xD0,
+	PVGAMCTRL = 0xE0,
+	NVGAMCTRL = 0xE1,
+};
+
+#define MADCTL_BGR BIT(3) /* bitmask for RGB/BGR order */
+#define MADCTL_MV BIT(5) /* bitmask for page/column order */
+#define MADCTL_MX BIT(6) /* bitmask for column address order */
+#define MADCTL_MY BIT(7) /* bitmask for page address order */
+
+/**
+ * init_display() - initialize the display controller
+ *
+ * @par: FBTFT parameter object
+ *
+ * Most of the commands in this init function set their parameters to the
+ * same default values which are already in place after the display has been
+ * powered up. (The main exception to this rule is the pixel format which
+ * would default to 18 instead of 16 bit per pixel.)
+ * Nonetheless, this sequence can be used as a template for concrete
+ * displays which usually need some adjustments.
+ *
+ * Return: 0 on success, < 0 if error occurred.
+ */
+static int init_display(struct fbtft_par *par)
+{
+	par->fbtftops.reset(par);
+    mdelay(120);
+	write_reg(par, 0x11);
+	mdelay(120);
+    write_reg(par, 0x36, 0x00);
+    write_reg(par, 0x3A, 0x65);
+    write_reg(par, 0xB2, 0x0C, 0x0C, 0x00, 0x33, 0x33);
+    write_reg(par, 0xB7, 0x35);
+    write_reg(par, 0xBB, 0x29);
+    write_reg(par, 0xC2, 0x01);
+    write_reg(par, 0xC3, 0x19);
+    write_reg(par, 0xC4, 0x20);
+	write_reg(par, 0xC5, 0x1A);
+    write_reg(par, 0xC6, 0x1F);
+    write_reg(par, 0xD0, 0xA4, 0xA1);
+    write_reg(par, 0xE0, 0xD0, 0x08, 0x0E, 0x09, 0x09, 0x05, 0x31, 0x33, 0x48, 0x17, 0x14, 0x15, 0x31, 0x34);
+    write_reg(par, 0xE1, 0xD0, 0x08, 0x0E, 0x09, 0x09, 0x15, 0x31, 0x33, 0x48, 0x17, 0x14, 0x15, 0x31, 0x34);
+    write_reg(par, 0x21);
+    write_reg(par, 0x11);
+    mdelay(120);
+    write_reg(par, 0x29);
+    mdelay(200);
+    return 0;
+}
+
+/**
+ * set_var() - apply LCD properties like rotation and BGR mode
+ *
+ * @par: FBTFT parameter object
+ *
+ * Return: 0 on success, < 0 if error occurred.
+ */
+static int set_var(struct fbtft_par *par)
+{
+	u8 madctl_par = 0;
+
+	if (par->bgr)
+		madctl_par |= MADCTL_BGR;
+	switch (par->info->var.rotate) {
+	case 0:
+		break;
+	case 90:
+		madctl_par |= (MADCTL_MV | MADCTL_MY);
+		break;
+	case 180:
+		madctl_par |= (MADCTL_MX | MADCTL_MY);
+		break;
+	case 270:
+		madctl_par |= (MADCTL_MV | MADCTL_MX);
+		break;
+	default:
+		return -EINVAL;
+	}
+	write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, madctl_par);
+	return 0;
+}
+
+/**
+ * set_gamma() - set gamma curves
+ *
+ * @par: FBTFT parameter object
+ * @curves: gamma curves
+ *
+ * Before the gamma curves are applied, they are preprocessed with a bitmask
+ * to ensure syntactically correct input for the display controller.
+ * This implies that the curves input parameter might be changed by this
+ * function and that illegal gamma values are auto-corrected and not
+ * reported as errors.
+ *
+ * Return: 0 on success, < 0 if error occurred.
+ */
+static int set_gamma(struct fbtft_par *par, u32 *curves)
+{
+	int i;
+	int j;
+	int c; /* curve index offset */
+
+	/*
+	 * Bitmasks for gamma curve command parameters.
+	 * The masks are the same for both positive and negative voltage
+	 * gamma curves.
+	 */
+	static const u8 gamma_par_mask[] = {
+		0xFF, /* V63[3:0], V0[3:0]*/
+		0x3F, /* V1[5:0] */
+		0x3F, /* V2[5:0] */
+		0x1F, /* V4[4:0] */
+		0x1F, /* V6[4:0] */
+		0x3F, /* J0[1:0], V13[3:0] */
+		0x7F, /* V20[6:0] */
+		0x77, /* V36[2:0], V27[2:0] */
+		0x7F, /* V43[6:0] */
+		0x3F, /* J1[1:0], V50[3:0] */
+		0x1F, /* V57[4:0] */
+		0x1F, /* V59[4:0] */
+		0x3F, /* V61[5:0] */
+		0x3F, /* V62[5:0] */
+	};
+
+	for (i = 0; i < par->gamma.num_curves; i++) {
+		c = i * par->gamma.num_values;
+		for (j = 0; j < par->gamma.num_values; j++)
+			curves[c + j] &= gamma_par_mask[j];
+		write_reg(par, PVGAMCTRL + i,
+			  curves[c + 0],  curves[c + 1],  curves[c + 2],
+			  curves[c + 3],  curves[c + 4],  curves[c + 5],
+			  curves[c + 6],  curves[c + 7],  curves[c + 8],
+			  curves[c + 9],  curves[c + 10], curves[c + 11],
+			  curves[c + 12], curves[c + 13]);
+	}
+	return 0;
+}
+
+/**
+ * blank() - blank the display
+ *
+ * @par: FBTFT parameter object
+ * @on: whether to enable or disable blanking the display
+ *
+ * Return: 0 on success, < 0 if error occurred.
+ */
+static int blank(struct fbtft_par *par, bool on)
+{
+	if (on)
+		write_reg(par, MIPI_DCS_SET_DISPLAY_OFF);
+	else
+		write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
+	return 0;
+}
+
+static struct fbtft_display display = {
+	.regwidth = 8,
+	.width = 240,
+	.height = 320,
+	.gamma_num = 2,
+	.gamma_len = 14,
+	.gamma = HSD20_IPS_GAMMA,
+	.fbtftops = {
+		.init_display = init_display,
+		.set_var = set_var,
+		.set_gamma = set_gamma,
+		.blank = blank,
+	},
+};
+
+FBTFT_REGISTER_DRIVER(DRVNAME, "sitronix,st7789", &display);
+
+MODULE_ALIAS("spi:" DRVNAME);
+MODULE_ALIAS("platform:" DRVNAME);
+MODULE_ALIAS("spi:st7789");
+MODULE_ALIAS("platform:st7789");
+
+MODULE_DESCRIPTION("FB driver for the ST7789 LCD Controller");
+MODULE_AUTHOR("Dennis Menschel");
+MODULE_LICENSE("GPL");

linux_5.10/drivers/staging/fbtft/fbtft-core.c

@@ -24,6 +24,8 @@
 #include <linux/platform_device.h>
 #include <linux/property.h>
 #include <linux/spinlock.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
 
 #include <video/mipi_display.h>
 
@@ -75,21 +77,40 @@ static int fbtft_request_one_gpio(struct fbtft_par *par,
 				  const char *name, int index,
 				  struct gpio_desc **gpiop)
 {
-	struct device *dev = par->info->device;
-	int ret = 0;
+    struct device *dev = par->info->device;
+    struct device_node *node = dev->of_node;
+    int gpio, flags, ret = 0;
+    enum of_gpio_flags of_flags;
 
-	*gpiop = devm_gpiod_get_index_optional(dev, name, index,
-					       GPIOD_OUT_HIGH);
-	if (IS_ERR(*gpiop)) {
-		ret = PTR_ERR(*gpiop);
-		dev_err(dev,
-			"Failed to request %s GPIO: %d\n", name, ret);
-		return ret;
-	}
-	fbtft_par_dbg(DEBUG_REQUEST_GPIOS, par, "%s: '%s' GPIO\n",
-		      __func__, name);
+    if (of_find_property(node, name, NULL)) {
+        gpio = of_get_named_gpio_flags(node, name, index, &of_flags);
+        if (gpio == -ENOENT)
+            return 0;
+        if (gpio == -EPROBE_DEFER)
+            return gpio;
+        if (gpio < 0) {
+            dev_err(dev,
+                "failed to get '%s' from DT\n", name);
+            return gpio;
+        }
 
-	return ret;
+        flags = (of_flags & OF_GPIO_ACTIVE_LOW) ? GPIOF_OUT_INIT_LOW :
+                            GPIOF_OUT_INIT_HIGH;
+        ret = devm_gpio_request_one(dev, gpio, flags,
+                        dev->driver->name);
+        if (ret) {
+            dev_err(dev,
+                "gpio_request_one('%s'=%d) failed with %d\n",
+                name, gpio, ret);
+            return ret;
+        }
+
+        *gpiop = gpio_to_desc(gpio);
+        fbtft_par_dbg(DEBUG_REQUEST_GPIOS, par, "%s: '%s' = GPIO%d\n",
+                            __func__, name, gpio);
+    }
+
+    return ret;
 }
 
 static int fbtft_request_gpios(struct fbtft_par *par)
@@ -228,9 +249,11 @@ static void fbtft_reset(struct fbtft_par *par)
 		return;
 	fbtft_par_dbg(DEBUG_RESET, par, "%s()\n", __func__);
 	gpiod_set_value_cansleep(par->gpio.reset, 1);
-	usleep_range(20, 40);
+	msleep(10);
 	gpiod_set_value_cansleep(par->gpio.reset, 0);
-	msleep(120);
+	msleep(200);
+	gpiod_set_value_cansleep(par->gpio.reset, 1);
+	msleep(10);
 }
 
 static void fbtft_update_display(struct fbtft_par *par, unsigned int start_line,

linux_5.10/kernel/dma/pool.c

@@ -20,6 +20,10 @@ static unsigned long pool_size_dma32;
 static struct gen_pool *atomic_pool_kernel __ro_after_init;
 static unsigned long pool_size_kernel;
 
+#ifndef DEFAULT_DMA_COHERENT_POOL_SIZE
+#define DEFAULT_DMA_COHERENT_POOL_SIZE	SZ_1M
+#endif
+
 /* Size can be defined by the coherent_pool command line */
 static size_t atomic_pool_size;
 
@@ -198,7 +202,7 @@ static int __init dma_atomic_pool_init(void)
 	if (!atomic_pool_size) {
 		unsigned long pages = totalram_pages() / (SZ_1G / SZ_128K);
 		pages = min_t(unsigned long, pages, MAX_ORDER_NR_PAGES);
-		atomic_pool_size = max_t(size_t, pages << PAGE_SHIFT, SZ_128K);
+		atomic_pool_size = max_t(size_t, pages << PAGE_SHIFT, DEFAULT_DMA_COHERENT_POOL_SIZE);
 	}
 	INIT_WORK(&atomic_pool_work, atomic_pool_work_fn);
 

middleware/v2/component/isp/sensor/cv182x/sms_sc035gs/sc035gs_cmos.c

@@ -92,7 +92,7 @@ static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSns
 	pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
 	pstAeSnsDft->u32FlickerFreq = 50 * 256;
 	pstAeSnsDft->u32FullLinesMax = SC035GS_FULL_LINES_MAX;
-	pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 120);
+	pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 240);
 
 	pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR;
 	pstAeSnsDft->stIntTimeAccu.f32Accuracy = 0.0625; /* unit = 1/16 line */
@@ -109,7 +109,7 @@ static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSns
 	pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift;
 
 	if (g_au32LinesPer500ms[ViPipe] == 0)
-		pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 120 / 2;
+		pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 240 / 2;
 	else
 		pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe];
 	pstAeSnsDft->u32SnsStableFrame = 0;
@@ -714,7 +714,7 @@ static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S
 	u8SensorImageMode = pstSnsState->u8ImgMode;
 	pstSnsState->bSyncInit = CVI_FALSE;
 
-	if (pstSensorImageMode->f32Fps <= 120) {
+	if (pstSensorImageMode->f32Fps <= 240) {
 		if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
 			if (SC035GS_RES_IS_480P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) {
 				u8SensorImageMode = SC035GS_MODE_640X480P120;

middleware/v2/component/isp/sensor/cv182x/sms_sc035gs/sc035gs_cmos_param.h

@@ -38,14 +38,18 @@ static const SC035GS_MODE_S g_astSC035GS_mode[SC035GS_MODE_NUM] = {
 				.u32Height = 480,
 			},
 		},
-		.f32MaxFps = 120,
-		.f32MinFps = 1.25, /* 515 * 120 / 0xFFFF */
+		.f32MaxFps = 240,
+		.f32MinFps = 0.31, /* 515 * 120 / 0xFFFF */
 		.u32HtsDef = 1136,	// 0x320c/d 036b=878 0470=1136
-		.u32VtsDef = 528,	// 0x320e/f 02ab=683 0210=528
+		.u32VtsDef = 86,	// 0x320e/f 02ab=683 0210=528
+		// .u32VtsDef = 68,	// 0x320e/f 02ab=683 0210=528
+		// .u32VtsDef = 512,	// 0x320e/f 30fps
+		// .u32VtsDef = 256,	// 0x320e/f 60fps
+		// .u32VtsDef = 128,	// 0x320e/f 120fps
 		.stExp[0] = {
 			.u16Min = 1,
-			.u16Max = 677 << 4,// (vts - 6) * 16
-			.u16Def = 400 << 4,
+			.u16Max = 80 << 4,// (vts - 6) * 16
+			.u16Def = 40 << 4,
 			.u16Step = 1,
 		},
 		.stAgain[0] = {
@@ -101,7 +105,7 @@ struct combo_dev_attr_s sc035gs_rx_attr = {
 	.mac_clk = RX_MAC_CLK_600M,
 	.mipi_attr = {
 		.raw_data_type = RAW_DATA_10BIT,
-		.lane_id = {4, 3, 2, -1, -1},
+		.lane_id = {4, 3, -1, -1, -1},
 		.pn_swap = {0, 0, 0, 0, 0},
 		.wdr_mode = CVI_MIPI_WDR_MODE_NONE,
 		.dphy = {

middleware/v2/component/isp/sensor/cv182x/sms_sc035gs/sc035gs_sensor_ctl.c

@@ -208,138 +208,135 @@ void sc035gs_exit(VI_PIPE ViPipe)
 /* 1296P30 and 1296P25 */
 static void sc035gs_linear_1296P30_init(VI_PIPE ViPipe)
 {
-	printf("###########   PinMux  #######################################################################\n");
-	system("devmem 0x0300116C 32 0x3");
-	system("devmem 0x03001170 32 0x3");
-	system("devmem 0x03001174 32 0x3");
-	system("devmem 0x03001178 32 0x3");
-	system("devmem 0x0300117C 32 0x3");
-	system("devmem 0x03001180 32 0x3");
-	system("devmem 0x03001184 32 0x3");
-	system("devmem 0x03001188 32 0x3");
-	system("devmem 0x0300118C 32 0x5");
-	system("devmem 0x03001190 32 0x3");
-	printf("###########   PinMux End  #######################################################################\n");
-	
 	//=============================================================================================================================================
-	// MTK6739 - 60FPS
-	sc035gs_write_register(ViPipe, 0x0103, 0x01); 
+	// 180FPS
+	sc035gs_write_register(ViPipe, 0x0103, 0x01);
 	delay_ms(33);
-	sc035gs_write_register(ViPipe, 0x0100, 0x00); 
-	sc035gs_write_register(ViPipe, 0x3000, 0x00); 
-	sc035gs_write_register(ViPipe, 0x3001, 0x00); 
-	sc035gs_write_register(ViPipe, 0x300f, 0x0f); 
-	sc035gs_write_register(ViPipe, 0x3018, 0x33); 
-	sc035gs_write_register(ViPipe, 0x3019, 0xfc); 
-	sc035gs_write_register(ViPipe, 0x301c, 0x78); 
-	sc035gs_write_register(ViPipe, 0x301f, 0xa2); 
-	sc035gs_write_register(ViPipe, 0x3031, 0x0a); 
-	sc035gs_write_register(ViPipe, 0x3037, 0x20); 
-	sc035gs_write_register(ViPipe, 0x303f, 0x01); 
+	sc035gs_write_register(ViPipe, 0x0100, 0x00);
 
-	// MTK6739 - 60FPS
-	sc035gs_write_register(ViPipe, 0x320c, 0x03); 	// 852
-	sc035gs_write_register(ViPipe, 0x320d, 0x54); 
-	sc035gs_write_register(ViPipe, 0x320e, 0x02); 	// 2112
-	sc035gs_write_register(ViPipe, 0x320f, 0x0e); 
-	sc035gs_write_register(ViPipe, 0x3252, 0x02); 
-	sc035gs_write_register(ViPipe, 0x3253, 0x08); 
-	sc035gs_write_register(ViPipe, 0x3217, 0x00); 
-	sc035gs_write_register(ViPipe, 0x3218, 0x00); 
-	sc035gs_write_register(ViPipe, 0x3220, 0x10); 
-	sc035gs_write_register(ViPipe, 0x3223, 0x48); 
-	sc035gs_write_register(ViPipe, 0x3226, 0x74); 
-	sc035gs_write_register(ViPipe, 0x3227, 0x07); 
-	sc035gs_write_register(ViPipe, 0x323b, 0x00); 
-	sc035gs_write_register(ViPipe, 0x3250, 0xf0); 
-	sc035gs_write_register(ViPipe, 0x3251, 0x02); 
-	sc035gs_write_register(ViPipe, 0x3254, 0x02); 
-	sc035gs_write_register(ViPipe, 0x3255, 0x07); 
-	sc035gs_write_register(ViPipe, 0x3304, 0x48); 
-	sc035gs_write_register(ViPipe, 0x3305, 0x00); 
-	sc035gs_write_register(ViPipe, 0x3306, 0x60); 
-	sc035gs_write_register(ViPipe, 0x3309, 0x50); 
-	sc035gs_write_register(ViPipe, 0x330a, 0x00); 
-	sc035gs_write_register(ViPipe, 0x330b, 0xc0); 
-	sc035gs_write_register(ViPipe, 0x330c, 0x18); 
-	sc035gs_write_register(ViPipe, 0x330f, 0x40); 
-	sc035gs_write_register(ViPipe, 0x3310, 0x10); 
-	sc035gs_write_register(ViPipe, 0x3314, 0x1e); 
-	sc035gs_write_register(ViPipe, 0x3315, 0x30); 
-	sc035gs_write_register(ViPipe, 0x3316, 0x68); 
-	sc035gs_write_register(ViPipe, 0x3317, 0x1b); 
-	sc035gs_write_register(ViPipe, 0x3329, 0x5c); 
-	sc035gs_write_register(ViPipe, 0x332d, 0x5c); 
-	sc035gs_write_register(ViPipe, 0x332f, 0x60); 
-	sc035gs_write_register(ViPipe, 0x3335, 0x64); 
-	sc035gs_write_register(ViPipe, 0x3344, 0x64); 
-	sc035gs_write_register(ViPipe, 0x335b, 0x80); 
-	sc035gs_write_register(ViPipe, 0x335f, 0x80); 
-	sc035gs_write_register(ViPipe, 0x3366, 0x06); 
-	sc035gs_write_register(ViPipe, 0x3385, 0x31); 
-	sc035gs_write_register(ViPipe, 0x3387, 0x39); 
-	sc035gs_write_register(ViPipe, 0x3389, 0x01); 
-	sc035gs_write_register(ViPipe, 0x33b1, 0x03); 
-	sc035gs_write_register(ViPipe, 0x33b2, 0x06); 
-	sc035gs_write_register(ViPipe, 0x33bd, 0xe0); 
-	sc035gs_write_register(ViPipe, 0x33bf, 0x10); 
-	sc035gs_write_register(ViPipe, 0x3621, 0xa4); 
-	sc035gs_write_register(ViPipe, 0x3622, 0x05); 
-	sc035gs_write_register(ViPipe, 0x3624, 0x47); 
-	sc035gs_write_register(ViPipe, 0x3630, 0x4a); 
-	sc035gs_write_register(ViPipe, 0x3631, 0x58); 
-	sc035gs_write_register(ViPipe, 0x3633, 0x52); 
-	sc035gs_write_register(ViPipe, 0x3635, 0x03); 
-	sc035gs_write_register(ViPipe, 0x3636, 0x25); 
-	sc035gs_write_register(ViPipe, 0x3637, 0x8a); 
-	sc035gs_write_register(ViPipe, 0x3638, 0x0f); 
-	sc035gs_write_register(ViPipe, 0x3639, 0x08); 
-	sc035gs_write_register(ViPipe, 0x363a, 0x00); 
-	sc035gs_write_register(ViPipe, 0x363b, 0x48); 
-	sc035gs_write_register(ViPipe, 0x363c, 0x86); 
-	sc035gs_write_register(ViPipe, 0x363d, 0x00);
-	sc035gs_write_register(ViPipe, 0x363e, 0xf8); 
-	sc035gs_write_register(ViPipe, 0x3640, 0x00); 
-	sc035gs_write_register(ViPipe, 0x3641, 0x01); 
-	sc035gs_write_register(ViPipe, 0x36e9, 0x80); 
-	sc035gs_write_register(ViPipe, 0x36ea, 0x37); 
-	sc035gs_write_register(ViPipe, 0x36eb, 0x0e); 
-	sc035gs_write_register(ViPipe, 0x36ec, 0x1e); 
-	sc035gs_write_register(ViPipe, 0x36ed, 0x23); 
-	sc035gs_write_register(ViPipe, 0x36f9, 0x80); 
-	sc035gs_write_register(ViPipe, 0x36fa, 0x37); 
-	sc035gs_write_register(ViPipe, 0x36fb, 0x00); 
-	sc035gs_write_register(ViPipe, 0x36fc, 0x02); 
-	sc035gs_write_register(ViPipe, 0x36fd, 0x03); 
-	sc035gs_write_register(ViPipe, 0x3908, 0x91); 
-	sc035gs_write_register(ViPipe, 0x391b, 0x81); 
-	sc035gs_write_register(ViPipe, 0x3d08, 0x01); 
-	sc035gs_write_register(ViPipe, 0x3e01, 0x83); 
-	sc035gs_write_register(ViPipe, 0x3e02, 0x80); 
-	sc035gs_write_register(ViPipe, 0x3e03, 0x2b); 
-	sc035gs_write_register(ViPipe, 0x3e06, 0x0c); 
-	sc035gs_write_register(ViPipe, 0x3f04, 0x03); 
-	sc035gs_write_register(ViPipe, 0x3f05, 0x34); 
-	sc035gs_write_register(ViPipe, 0x4500, 0x59); 
-	sc035gs_write_register(ViPipe, 0x4501, 0xc4); 
-	sc035gs_write_register(ViPipe, 0x4603, 0x00); 
-	sc035gs_write_register(ViPipe, 0x4800, 0x64); 
-	sc035gs_write_register(ViPipe, 0x4809, 0x01); 
-	sc035gs_write_register(ViPipe, 0x4810, 0x00); 
-	sc035gs_write_register(ViPipe, 0x4811, 0x01); 
-	sc035gs_write_register(ViPipe, 0x4837, 0x26); 
-	sc035gs_write_register(ViPipe, 0x5011, 0x00); 
-	sc035gs_write_register(ViPipe, 0x5988, 0x02); 
-	sc035gs_write_register(ViPipe, 0x598e, 0x03); 
-	sc035gs_write_register(ViPipe, 0x598f, 0x01); 
-	sc035gs_write_register(ViPipe, 0x36e9, 0x24); 
-	sc035gs_write_register(ViPipe, 0x36f9, 0x20); 
-	sc035gs_write_register(ViPipe, 0x0100, 0x01); 
+	sc035gs_write_register(ViPipe, 0x36e9, 0x80);
+	sc035gs_write_register(ViPipe, 0x36f9, 0x80);
+	sc035gs_write_register(ViPipe, 0x3000, 0x00);
+	sc035gs_write_register(ViPipe, 0x3001, 0x00);
+
+	sc035gs_write_register(ViPipe, 0x300f, 0x0f);
+	sc035gs_write_register(ViPipe, 0x3018, 0x13);
+
+	sc035gs_write_register(ViPipe, 0x3019, 0xfc);
+	sc035gs_write_register(ViPipe, 0x301c, 0x78);
+
+	sc035gs_write_register(ViPipe, 0x301f, 0x87);
+	sc035gs_write_register(ViPipe, 0x3031, 0x0a);
+	sc035gs_write_register(ViPipe, 0x3037, 0x20);
+	sc035gs_write_register(ViPipe, 0x303f, 0x01);
+
+	sc035gs_write_register(ViPipe, 0x320c, 0x03);
+	sc035gs_write_register(ViPipe, 0x320d, 0x6e);
+	sc035gs_write_register(ViPipe, 0x320e, 0x02);
+	sc035gs_write_register(ViPipe, 0x320f, 0x00);
+
+	sc035gs_write_register(ViPipe, 0x3217, 0x00);
+	sc035gs_write_register(ViPipe, 0x3218, 0x00);
+	sc035gs_write_register(ViPipe, 0x3220, 0x10);
+	sc035gs_write_register(ViPipe, 0x3223, 0x48);
+	sc035gs_write_register(ViPipe, 0x3226, 0x74);
+	sc035gs_write_register(ViPipe, 0x3227, 0x07);
+	sc035gs_write_register(ViPipe, 0x323b, 0x00);
+
+	sc035gs_write_register(ViPipe, 0x3250, 0xf0);
+	sc035gs_write_register(ViPipe, 0x3251, 0x02);
+	sc035gs_write_register(ViPipe, 0x3252, 0x02);
+	sc035gs_write_register(ViPipe, 0x3253, 0x08);
+	sc035gs_write_register(ViPipe, 0x3254, 0x02);
+	sc035gs_write_register(ViPipe, 0x3255, 0x07);
+
+	sc035gs_write_register(ViPipe, 0x3304, 0x48);
+	sc035gs_write_register(ViPipe, 0x3305, 0x00);
+	sc035gs_write_register(ViPipe, 0x3306, 0x60);
+	sc035gs_write_register(ViPipe, 0x3309, 0x50);
+	sc035gs_write_register(ViPipe, 0x330a, 0x00);
+	sc035gs_write_register(ViPipe, 0x330b, 0xc0);
+	sc035gs_write_register(ViPipe, 0x330c, 0x18);
+	sc035gs_write_register(ViPipe, 0x330f, 0x40);
+	sc035gs_write_register(ViPipe, 0x3310, 0x10);
+	sc035gs_write_register(ViPipe, 0x3314, 0x1e);
+	sc035gs_write_register(ViPipe, 0x3315, 0x30);
+	sc035gs_write_register(ViPipe, 0x3316, 0x68);
+	sc035gs_write_register(ViPipe, 0x3317, 0x1b);
+	sc035gs_write_register(ViPipe, 0x3329, 0x5c);
+	sc035gs_write_register(ViPipe, 0x332d, 0x5c);
+	sc035gs_write_register(ViPipe, 0x332f, 0x60);
+	sc035gs_write_register(ViPipe, 0x3335, 0x64);
+	sc035gs_write_register(ViPipe, 0x3344, 0x64);
+	sc035gs_write_register(ViPipe, 0x335b, 0x80);
+	sc035gs_write_register(ViPipe, 0x335f, 0x80);
+	sc035gs_write_register(ViPipe, 0x3366, 0x06);
+	sc035gs_write_register(ViPipe, 0x3385, 0x31);
+	sc035gs_write_register(ViPipe, 0x3387, 0x39);
+	sc035gs_write_register(ViPipe, 0x3389, 0x01);
+	sc035gs_write_register(ViPipe, 0x33b1, 0x03);
+	sc035gs_write_register(ViPipe, 0x33b2, 0x06);
+	sc035gs_write_register(ViPipe, 0x33bd, 0xe0);
+	sc035gs_write_register(ViPipe, 0x33bf, 0x10);
+	sc035gs_write_register(ViPipe, 0x3621, 0xa4);
+	sc035gs_write_register(ViPipe, 0x3622, 0x05);
+	sc035gs_write_register(ViPipe, 0x3624, 0x47);
+	sc035gs_write_register(ViPipe, 0x3630, 0x4a);
+	sc035gs_write_register(ViPipe, 0x3631, 0x58);
+	sc035gs_write_register(ViPipe, 0x3633, 0x52);
+	sc035gs_write_register(ViPipe, 0x3635, 0x03);
+	sc035gs_write_register(ViPipe, 0x3636, 0x25);
+	sc035gs_write_register(ViPipe, 0x3637, 0x8a);
+	sc035gs_write_register(ViPipe, 0x3638, 0x0f);
+	sc035gs_write_register(ViPipe, 0x3639, 0x08);
+	sc035gs_write_register(ViPipe, 0x363a, 0x00);
+	sc035gs_write_register(ViPipe, 0x363b, 0x48);
+	sc035gs_write_register(ViPipe, 0x363c, 0x86);
+
+	sc035gs_write_register(ViPipe, 0x363d, 0x10);
+	sc035gs_write_register(ViPipe, 0x363e, 0xf8);
+	sc035gs_write_register(ViPipe, 0x3640, 0x00);
+	sc035gs_write_register(ViPipe, 0x3641, 0x01);
+	sc035gs_write_register(ViPipe, 0x36ea, 0x37);
+	sc035gs_write_register(ViPipe, 0x36eb, 0x0e);
+	sc035gs_write_register(ViPipe, 0x36ec, 0x0e);	//
+	sc035gs_write_register(ViPipe, 0x36ed, 0x23);
+	sc035gs_write_register(ViPipe, 0x36fa, 0x37);
+	sc035gs_write_register(ViPipe, 0x36fb, 0x00);
+	sc035gs_write_register(ViPipe, 0x36fc, 0x02);
+	sc035gs_write_register(ViPipe, 0x36fd, 0x03);
+	sc035gs_write_register(ViPipe, 0x3908, 0x91);
+	sc035gs_write_register(ViPipe, 0x391b, 0x81);
+	sc035gs_write_register(ViPipe, 0x3d08, 0x01);
+
+	sc035gs_write_register(ViPipe, 0x3e01, 0x02);
+	sc035gs_write_register(ViPipe, 0x3e02, 0xD2);
+	sc035gs_write_register(ViPipe, 0x3e03, 0x2b);
+	sc035gs_write_register(ViPipe, 0x3e06, 0x0c);
+	sc035gs_write_register(ViPipe, 0x3e08, 0x00);
+	sc035gs_write_register(ViPipe, 0x3e09, 0x10);
+	sc035gs_write_register(ViPipe, 0x3f04, 0x03);
+	sc035gs_write_register(ViPipe, 0x3f05, 0x34);
+	sc035gs_write_register(ViPipe, 0x4500, 0x59);
+	sc035gs_write_register(ViPipe, 0x4501, 0xc4);
+	sc035gs_write_register(ViPipe, 0x4603, 0x00);
+	sc035gs_write_register(ViPipe, 0x4800, 0x64);
+	sc035gs_write_register(ViPipe, 0x4809, 0x01);
+	sc035gs_write_register(ViPipe, 0x4810, 0x00);
+	sc035gs_write_register(ViPipe, 0x4811, 0x01);
+
+	sc035gs_write_register(ViPipe, 0x4837, 0x13);
+	sc035gs_write_register(ViPipe, 0x5011, 0x00);
+	sc035gs_write_register(ViPipe, 0x5988, 0x02);
+	sc035gs_write_register(ViPipe, 0x598e, 0x03);	//
+	sc035gs_write_register(ViPipe, 0x598f, 0x20);	//
+	sc035gs_write_register(ViPipe, 0x36e9, 0x24);
+	sc035gs_write_register(ViPipe, 0x36f9, 0x20);
+	sc035gs_write_register(ViPipe, 0x0100, 0x01);
 	delay_ms(20);
-	sc035gs_write_register(ViPipe, 0x4418, 0x0a); 
-	sc035gs_write_register(ViPipe, 0x363d, 0x10); 
-	sc035gs_write_register(ViPipe, 0x4419, 0x80); 
+	sc035gs_write_register(ViPipe, 0x4418, 0x0a);
+	sc035gs_write_register(ViPipe, 0x4419, 0x80);
 
 
-	printf("ViPipe:%d,===SC035GS 480P 120fps 12bit LINE Init OK!===\n", ViPipe);
+	printf("ViPipe:%d,===SC035GS 480P 180fps 10bit LINE Init OK!===\n", ViPipe);
 }

middleware/v2/component/panel/sg200x/dsi_d240si31.h

@@ -0,0 +1,167 @@
+#ifndef _MIPI_TX_PARAM_D240SI31_H_
+#define _MIPI_TX_PARAM_D240SI31_H_
+
+#ifndef __UBOOT__
+#include <linux/vo_mipi_tx.h>
+#include <linux/cvi_comm_mipi_tx.h>
+#else
+#include <cvi_mipi.h>
+#endif
+
+/*
+#define D240SI31_VACT	854
+#define D240SI31_VSA		2
+#define D240SI31_VBP		20
+#define D240SI31_VFP		20
+
+#define D240SI31_HACT	480
+#define D240SI31_HSA		10
+#define D240SI31_HBP		40
+#define D240SI31_HFP		40
+*/
+
+#define D240SI31_VACT		640
+#define D240SI31_VSA		10
+#define D240SI31_VBP		30
+#define D240SI31_VFP		30
+
+#define D240SI31_HACT		480
+#define D240SI31_HSA		48
+#define D240SI31_HBP		30
+#define D240SI31_HFP		30
+
+#define DXQ_PIXEL_CLK(x) ((x##_VACT + x##_VSA + x##_VBP + x##_VFP) \
+	* (x##_HACT + x##_HSA + x##_HBP + x##_HFP) * 60 / 1000)
+
+struct combo_dev_cfg_s dev_cfg_d240si31 = {
+	.devno = 0,
+	.lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_CLK, MIPI_TX_LANE_1, -1, -1},
+	.lane_pn_swap = {false, false, false, false, false},
+	.output_mode = OUTPUT_MODE_DSI_VIDEO,
+	.video_mode = BURST_MODE,
+	.output_format = OUT_FORMAT_RGB_24_BIT,
+	.sync_info = {
+		.vid_hsa_pixels = D240SI31_HSA,
+		.vid_hbp_pixels = D240SI31_HBP,
+		.vid_hfp_pixels = D240SI31_HFP,
+		.vid_hline_pixels = D240SI31_HACT,
+		.vid_vsa_lines = D240SI31_VSA,
+		.vid_vbp_lines = D240SI31_VBP,
+		.vid_vfp_lines = D240SI31_VFP,
+		.vid_active_lines = D240SI31_VACT,
+		.vid_vsa_pos_polarity = true,
+		.vid_hsa_pos_polarity = false,
+	},
+	.pixel_clk = DXQ_PIXEL_CLK(D240SI31),
+};
+
+const struct hs_settle_s hs_timing_cfg_d240si31 = { .prepare = 6, .zero = 32, .trail = 1 };
+
+#ifndef CVI_U8
+#define CVI_U8 unsigned char
+#endif
+
+static CVI_U8 data_d240si31_0[] = {0xff, 0x77, 0x01, 0x00, 0x00, 0x13};
+static CVI_U8 data_d240si31_1[] = {0xef, 0x08};
+static CVI_U8 data_d240si31_2[] = {0xff, 0x77, 0x01, 0x00, 0x00, 0x10};
+static CVI_U8 data_d240si31_3[] = {0xc0, 0x4f, 0x00};
+static CVI_U8 data_d240si31_4[] = {0xc1, 0x10, 0x0c};
+static CVI_U8 data_d240si31_5[] = {0xc2, 0x01, 0x14};
+static CVI_U8 data_d240si31_6[] = {0xcc, 0x10};
+static CVI_U8 data_d240si31_7[] = {0xb0, 0x00, 0x0b, 0x13, 0x0d, 0x10, 0x07, 0x02, 0x08, 0x07, 0x1f, 0x04, 0x11, 0x0f, 0x28, 0x2f, 0x1f};
+static CVI_U8 data_d240si31_8[] = {0xb1, 0x00, 0x0c, 0x13, 0x0c, 0x10, 0x05, 0x02, 0x08, 0x08, 0x1e, 0x05, 0x13, 0x11, 0x27, 0x30, 0x1f};
+static CVI_U8 data_d240si31_9[] = {0xff, 0x77, 0x01, 0x00, 0x00, 0x11};
+static CVI_U8 data_d240si31_10[] = {0xb0, 0x4d};
+static CVI_U8 data_d240si31_11[] = {0xb1, 0x6A};
+static CVI_U8 data_d240si31_12[] = {0xb2, 0x87};
+static CVI_U8 data_d240si31_13[] = {0xb3, 0x80};
+static CVI_U8 data_d240si31_14[] = {0xb5, 0x45};
+static CVI_U8 data_d240si31_15[] = {0xb7, 0x85};
+static CVI_U8 data_d240si31_16[] = {0xb8, 0x20};
+static CVI_U8 data_d240si31_17[] = {0xc1, 0x78};
+static CVI_U8 data_d240si31_18[] = {0xc2, 0x78};
+static CVI_U8 data_d240si31_19[] = {0xd0, 0x88};
+//delay 100 ms
+static CVI_U8 data_d240si31_20[] = {0xe0, 0x00, 0x00, 0x02};
+static CVI_U8 data_d240si31_21[] = {0xe1, 0x04, 0xb0, 0x06, 0xb0, 0x05, 0xb0, 0x07, 0xb0, 0x00, 0x44, 0x44};
+static CVI_U8 data_d240si31_22[] = {0xe2, 0x20, 0x20, 0x44, 0x44, 0x96, 0xa0, 0x00, 0x00, 0x96, 0xa0, 0x00, 0x00};
+static CVI_U8 data_d240si31_23[] = {0xe3, 0x00, 0x00, 0x22, 0x22};
+static CVI_U8 data_d240si31_24[] = {0xe4, 0x44, 0x44};
+static CVI_U8 data_d240si31_25[] = {0xe5, 0x0c, 0x90, 0xb0, 0xa0, 0x0e, 0x92, 0xb0, 0xa0, 0x08, 0x8c, 0xb0, 0xa0, 0x0a, 0x8e, 0xb0, 0xa0};
+static CVI_U8 data_d240si31_26[] = {0xe6, 0x00, 0x00, 0x22, 0x22};
+static CVI_U8 data_d240si31_27[] = {0xe7, 0x44, 0x44};
+static CVI_U8 data_d240si31_28[] = {0xe8, 0x0d, 0x91, 0xb0, 0xa0, 0x0f, 0x93, 0xb0, 0xa0, 0x09, 0x8d, 0xb0, 0xa0, 0x0b, 0x8f, 0xb0, 0xa0};
+static CVI_U8 data_d240si31_29[] = {0xe9, 0x36, 0x00};
+static CVI_U8 data_d240si31_30[] = {0xeb, 0x00, 0x00, 0xe4, 0xe4, 0x44, 0x88, 0x40};
+static CVI_U8 data_d240si31_31[] = {0xed, 0xf1, 0xb2, 0xac, 0x0f, 0x67, 0x45, 0xff, 0xff, 0xff, 0xff, 0x54, 0x76, 0xf0, 0xca, 0x2b, 0x1f};
+static CVI_U8 data_d240si31_32[] = {0xef, 0x10, 0x0d, 0x04, 0x08, 0x3f, 0x1f};
+static CVI_U8 data_d240si31_33[] = {0xff, 0x77, 0x01, 0x00, 0x00, 0x13};
+static CVI_U8 data_d240si31_34[] = {0xe8, 0x00, 0x0e};
+static CVI_U8 data_d240si31_35[] = {0xff, 0x77, 0x01, 0x00, 0x00, 0x00};
+static CVI_U8 data_d240si31_36[] = {0x11};
+//delay 120 ms
+static CVI_U8 data_d240si31_37[] = {0xff, 0x77, 0x01, 0x00, 0x00, 0x13};
+static CVI_U8 data_d240si31_38[] = {0x11, 0xe8, 0x00, 0x0c};
+//delay 10 ms
+static CVI_U8 data_d240si31_39[] = {0xe8, 0x00, 0x00};
+static CVI_U8 data_d240si31_40[] = {0xff, 0x77, 0x01, 0x00, 0x00, 0x00};
+static CVI_U8 data_d240si31_41[] = {0x36, 0x10};
+static CVI_U8 data_d240si31_42[] = {0x29};
+//delay 20 ms
+
+// len == 1 , type 0x05
+// len == 2 , type 0x15 or type 23
+// len >= 3 , type 0x29 or type 0x39
+#define TYPE1_DCS_SHORT_WRITE 0x05
+#define TYPE2_DCS_SHORT_WRITE 0x15
+#define TYPE3_DCS_LONG_WRITE 0x39
+#define TYPE3_GENERIC_LONG_WRITE 0x29
+const struct dsc_instr dsi_init_cmds_d240si31[] = {
+	{.delay = 60, .data_type = TYPE3_DCS_LONG_WRITE, .size = 6, .data = data_d240si31_0 },
+	{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_d240si31_1 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 6, .data = data_d240si31_2 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 3, .data = data_d240si31_3 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 3, .data = data_d240si31_4 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 3, .data = data_d240si31_5 },
+	{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_d240si31_6 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 17, .data = data_d240si31_7 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 17, .data = data_d240si31_8 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 6, .data = data_d240si31_9 },
+	{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_d240si31_10 },
+	{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_d240si31_11 },
+	{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_d240si31_12 },
+	{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_d240si31_13 },
+	{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_d240si31_14 },
+	{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_d240si31_15 },
+	{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_d240si31_16 },
+	{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_d240si31_17 },
+	{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_d240si31_18 },
+	{.delay = 100, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_d240si31_19 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 5, .data = data_d240si31_20 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 12, .data = data_d240si31_21 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 13, .data = data_d240si31_22 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 5, .data = data_d240si31_23 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 3, .data = data_d240si31_24 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 17, .data = data_d240si31_25 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 5, .data = data_d240si31_26 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 3, .data = data_d240si31_27 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 17, .data = data_d240si31_28 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 3, .data = data_d240si31_29 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 8, .data = data_d240si31_30 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 17, .data = data_d240si31_31 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 7, .data = data_d240si31_32 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 6, .data = data_d240si31_33 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 3, .data = data_d240si31_34 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 6, .data = data_d240si31_35 },
+	{.delay = 120, .data_type = TYPE1_DCS_SHORT_WRITE, .size = 1, .data = data_d240si31_36 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 6, .data = data_d240si31_37 },
+	{.delay = 10, .data_type = TYPE3_DCS_LONG_WRITE, .size = 4, .data = data_d240si31_38 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 3, .data = data_d240si31_39 },
+	{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 6, .data = data_d240si31_40 },
+	{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_d240si31_41 },
+	{.delay = 20, .data_type = TYPE1_DCS_SHORT_WRITE, .size = 1, .data = data_d240si31_42 },
+};
+
+#else
+#error "MIPI_TX_PARAM multi-delcaration!!"
+#endif

middleware/v2/component/panel/sg200x/dsi_lt9611.h

@@ -5,7 +5,8 @@
 
 static struct combo_dev_cfg_s dev_cfg_lt9611_1920x1080_60Hz = {
 	.devno = 0,
-	.lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3},
+	// .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3},
+	.lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_CLK, MIPI_TX_LANE_1, -1, -1},
 	.lane_pn_swap = {false, false, false, false, false},
 	.output_mode = OUTPUT_MODE_DSI_VIDEO,
 	.video_mode = BURST_MODE,
@@ -27,7 +28,8 @@ static struct combo_dev_cfg_s dev_cfg_lt9611_1920x1080_60Hz = {
 
 static struct combo_dev_cfg_s dev_cfg_lt9611_1920x1080_30Hz = {
 	.devno = 0,
-	.lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3},
+	// .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3},
+	.lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_CLK, MIPI_TX_LANE_1, -1, -1},
 	.lane_pn_swap = {false, false, false, false, false},
 	.output_mode = OUTPUT_MODE_DSI_VIDEO,
 	.video_mode = BURST_MODE,
@@ -49,7 +51,8 @@ static struct combo_dev_cfg_s dev_cfg_lt9611_1920x1080_30Hz = {
 
 static struct combo_dev_cfg_s dev_cfg_lt9611_1280x720_60Hz = {
 	.devno = 0,
-	.lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3},
+	// .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3},
+	.lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_CLK, MIPI_TX_LANE_1, -1, -1},
 	.lane_pn_swap = {false, false, false, false, false},
 	.output_mode = OUTPUT_MODE_DSI_VIDEO,
 	.video_mode = BURST_MODE,
@@ -71,7 +74,8 @@ static struct combo_dev_cfg_s dev_cfg_lt9611_1280x720_60Hz = {
 
 static struct combo_dev_cfg_s dev_cfg_lt9611_1024x768_60Hz = {
 	.devno = 0,
-	.lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3},
+	// .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3},
+	.lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_CLK, MIPI_TX_LANE_1, -1, -1},
 	.lane_pn_swap = {false, false, false, false, false},
 	.output_mode = OUTPUT_MODE_DSI_VIDEO,
 	.video_mode = BURST_MODE,
@@ -93,7 +97,8 @@ static struct combo_dev_cfg_s dev_cfg_lt9611_1024x768_60Hz = {
 
 static struct combo_dev_cfg_s dev_cfg_lt9611_1280x1024_60Hz = {
 	.devno = 0,
-	.lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3},
+	// .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3},
+	.lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_CLK, MIPI_TX_LANE_1, -1, -1},
 	.lane_pn_swap = {false, false, false, false, false},
 	.output_mode = OUTPUT_MODE_DSI_VIDEO,
 	.video_mode = BURST_MODE,
@@ -115,7 +120,8 @@ static struct combo_dev_cfg_s dev_cfg_lt9611_1280x1024_60Hz = {
 
 static struct combo_dev_cfg_s dev_cfg_lt9611_1600x1200_60Hz = {
 	.devno = 0,
-	.lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3},
+	// .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3},
+	.lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_CLK, MIPI_TX_LANE_1, -1, -1},
 	.lane_pn_swap = {false, false, false, false, false},
 	.output_mode = OUTPUT_MODE_DSI_VIDEO,
 	.video_mode = BURST_MODE,

middleware/v2/modules/vpu/src/cvi_vi.c

@@ -1466,7 +1466,11 @@ CVI_S32 CVI_VI_EnableChn(VI_PIPE ViPipe, VI_CHN ViChn)
 			pthread_attr_setschedparam(&attr, &param);
 			pthread_attr_setinheritsched(&attr, PTHREAD_EXPLICIT_SCHED);
 
-			pthread_create(&gViDbgTH.vi_dbg_thread, &attr, (void *)vi_dbg_handler, NULL);
+			setenv("VI_DBG_HANDLER_ENABLE", "0", 0);
+			char *value = getenv("VI_DBG_HANDLER_ENABLE");
+			if (atoi(value)) {
+				pthread_create(&gViDbgTH.vi_dbg_thread, &attr, (void *)vi_dbg_handler, NULL);
+			}
 		}
 	}
 
@@ -1516,7 +1520,10 @@ CVI_S32 CVI_VI_DisableChn(VI_PIPE ViPipe, VI_CHN ViChn)
 				return CVI_ERR_VI_FAILED_NOT_ENABLED;
 			}
 
-			pthread_join(gViDbgTH.vi_dbg_thread, NULL);
+			char *value = getenv("VI_DBG_HANDLER_ENABLE");
+			if (atoi(value)) {
+				pthread_join(gViDbgTH.vi_dbg_thread, NULL);
+			}
 
 			s32Ret = _cvi_vi_freeIonBuf();
 			if (s32Ret != CVI_SUCCESS) {

middleware/v2/sample/mipi_tx/sample_dsi.c

@@ -62,6 +62,7 @@ typedef enum
 	DSI_PANEL_ST7701_HD228001C31_ALT0,
 	DSI_PANEL_ST7789V,
 	DSI_PANEL_ST7785M,
+	DSI_PANEL_D240SI31,
 	DSI_PANEL_MAX
 } DSI_PANEL_MODEL;
 
@@ -129,6 +130,7 @@ static const char* s_panel_model_type_arr[] = {
 	"ST7701_HD228001C31_ALT0",
 	"ST7789V",
 	"ST7785M",
+	"D240SI31",
 };
 
 int dsi_init(int devno, const struct dsc_instr *cmds, int size)
@@ -408,20 +410,20 @@ void SAMPLE_MIPI_SET_PANEL_DESC()
 			g_panel_desc.dsi_init_cmds = dsi_init_cmds_st7701_480x800;
 			g_panel_desc.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_st7701_480x800);
 			break;
-                case DSI_PANEL_ST7701_HD228001C31:
-                        g_panel_desc.panel_name = "ST7701-368x552";
-                        g_panel_desc.dev_cfg = &dev_cfg_st7701_368x552;
-                        g_panel_desc.hs_timing_cfg = &hs_timing_cfg_st7701_368x552;
-                        g_panel_desc.dsi_init_cmds = dsi_init_cmds_st7701_368x552;
-                        g_panel_desc.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_st7701_368x552);
-                        break;
-	case DSI_PANEL_ST7701_HD228001C31_ALT0:
-                        g_panel_desc.panel_name = "ST7701-368x552-alt0";
-                        g_panel_desc.dev_cfg = &dev_cfg_st7701_368x552_alt0;
-                        g_panel_desc.hs_timing_cfg = &hs_timing_cfg_st7701_368x552_alt0;
-                        g_panel_desc.dsi_init_cmds = dsi_init_cmds_st7701_368x552_alt0;
-                        g_panel_desc.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_st7701_368x552_alt0);
-                        break;
+		case DSI_PANEL_ST7701_HD228001C31:
+			g_panel_desc.panel_name = "ST7701-368x552";
+			g_panel_desc.dev_cfg = &dev_cfg_st7701_368x552;
+			g_panel_desc.hs_timing_cfg = &hs_timing_cfg_st7701_368x552;
+			g_panel_desc.dsi_init_cmds = dsi_init_cmds_st7701_368x552;
+			g_panel_desc.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_st7701_368x552);
+			break;
+		case DSI_PANEL_ST7701_HD228001C31_ALT0:
+			g_panel_desc.panel_name = "ST7701-368x552-alt0";
+			g_panel_desc.dev_cfg = &dev_cfg_st7701_368x552_alt0;
+			g_panel_desc.hs_timing_cfg = &hs_timing_cfg_st7701_368x552_alt0;
+			g_panel_desc.dsi_init_cmds = dsi_init_cmds_st7701_368x552_alt0;
+			g_panel_desc.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_st7701_368x552_alt0);
+			break;
 		case DSI_PANEL_ST7785M:
 			g_panel_desc.panel_name = "ST77825M-240x320";
 			g_panel_desc.dev_cfg = &dev_cfg_st7785m_240x320;
@@ -430,12 +432,12 @@ void SAMPLE_MIPI_SET_PANEL_DESC()
 			g_panel_desc.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_st7785m_240x320);
 			break;
 		case DSI_PANEL_ZCT2133V1:
-                        g_panel_desc.panel_name = "ZCT2133V1-800x1280";
-                        g_panel_desc.dev_cfg = &dev_cfg_zct2133v1_800x1280;
-                        g_panel_desc.hs_timing_cfg = &hs_timing_cfg_zct2133v1_800x1280;
-                        g_panel_desc.dsi_init_cmds = dsi_init_cmds_zct2133v1_800x1280;
-                        g_panel_desc.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_zct2133v1_800x1280);
-                        break;
+			g_panel_desc.panel_name = "ZCT2133V1-800x1280";
+			g_panel_desc.dev_cfg = &dev_cfg_zct2133v1_800x1280;
+			g_panel_desc.hs_timing_cfg = &hs_timing_cfg_zct2133v1_800x1280;
+			g_panel_desc.dsi_init_cmds = dsi_init_cmds_zct2133v1_800x1280;
+			g_panel_desc.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_zct2133v1_800x1280);
+			break;
 		case DSI_PANEL_HX8399_1080P:
 			g_panel_desc.panel_name = "HX8399_1080x1920";
 			g_panel_desc.dev_cfg = &dev_cfg_hx8399_1080x1920;
@@ -499,6 +501,13 @@ void SAMPLE_MIPI_SET_PANEL_DESC()
 			g_panel_desc.dsi_init_cmds = dsi_init_cmds_st7701_480x854dxq;
 			g_panel_desc.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_st7701_480x854dxq);
 			break;
+		case DSI_PANEL_D240SI31:
+			g_panel_desc.panel_name = "D240SI31";
+			g_panel_desc.dev_cfg = &dev_cfg_d240si31;
+			g_panel_desc.hs_timing_cfg = &hs_timing_cfg_d240si31;
+			g_panel_desc.dsi_init_cmds = dsi_init_cmds_d240si31;
+			g_panel_desc.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_d240si31);
+			break;
 		case DSI_PANEL_HX8394_EVB:
 		default:
 			printf("default\n");

middleware/v2/sample/mipi_tx/sample_dsi_panel.h

@@ -33,6 +33,7 @@ extern "C" {
 #include "dsi_lt9611.h"
 #include "dsi_st7785m.h"
 #include "dsi_zct2133v1.h"
+#include "dsi_d240si31.h"
 
 struct panel_desc_s {
 	char *panel_name;

middleware/v2/sample/scene_auto/Makefile

@@ -34,7 +34,7 @@ LIBS += -lnanomsg
 endif
 
 EXTRA_CFLAGS = $(INCS) $(DEFS)
-EXTRA_LDFLAGS = $(LIBS) -lpthread -lm -lini
+EXTRA_LDFLAGS = $(LIBS) -lpthread -lm -lini -latomic
 
 .PHONY : clean all
 all: $(TARGET)

osdrv/extdrv/wireless/aic8800/.gitignore

@@ -1,3 +1,5 @@
 *.symvers
 *.order
+*.symvers.cmd
+*.order.cmd
 .tmp_versions/

osdrv/extdrv/wireless/aic8800/Kconfig

@@ -8,7 +8,7 @@ config AIC_FW_PATH
 	depends on AIC_WLAN_SUPPORT
 	string "Firmware & config file path"
 	#default "/vendor/etc/firmware"
-	default "/lib/firmware/aic8800_sdio/aic8800"
+	default "/usr/lib/firmware/aic8800_sdio/aic8800_and_aic8800D80"
 	help
 	  Path to the firmware & config file.
 

osdrv/extdrv/wireless/aic8800/Makefile

@@ -6,51 +6,54 @@ obj-$(CONFIG_AIC8800_BTLPM_SUPPORT) += aic8800_btlpm/
 obj-$(CONFIG_AIC8800_WLAN_SUPPORT) += aic8800_fdrv/
 obj-$(CONFIG_AIC_WLAN_SUPPORT) += aic8800_bsp/
 
+MAKEFLAGS +=-j$(shell nproc)
 
-# Platform support list
-CONFIG_PLATFORM_ROCKCHIP = n
-CONFIG_PLATFORM_ROCKCHIP2 = n
-CONFIG_PLATFORM_ALLWINNER = n
-CONFIG_PLATFORM_AMLOGIC = n
-CONFIG_PLATFORM_UBUNTU = y
+########## config option ##########
+export CONFIG_USE_FW_REQUEST = n
+export CONFIG_PREALLOC_RX_SKB = y
+export CONFIG_PREALLOC_TXQ = y
+export CONFIG_OOB = n
+export CONFIG_GPIO_WAKEUP = n
+export CONFIG_RESV_MEM_SUPPORT = y
+###################################
 
+########## Platform support list ##########
+export CONFIG_PLATFORM_ROCKCHIP = n
+export CONFIG_PLATFORM_ROCKCHIP2 = n
+export CONFIG_PLATFORM_ALLWINNER = n
+export CONFIG_PLATFORM_AMLOGIC = n
+export CONFIG_PLATFORM_UBUNTU = y
 
 ifeq ($(CONFIG_PLATFORM_ROCKCHIP), y)
-#KDIR = /home/yaya/E/Rockchip/3229/Android7/RK3229_ANDROID7.1_v1.01_20170914/rk3229_Android7.1_v1.01_xml0914/kernel
-#ARCH = arm
-#CROSS_COMPILE = /home/yaya/E/Rockchip/3229/Android7/RK3229_ANDROID7.1_v1.01_20170914/rk3229_Android7.1_v1.01_xml0914/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
-KDIR  = /home/yaya/E/Rockchip/3229/Android9/rk3229_android9.0_box/kernel
-ARCH = arm
-CROSS_COMPILE = /home/yaya/E/Rockchip/3229/Android9/rk3229_android9.0_box/prebuilts/gcc/linux-x86/arm/gcc-linaro-6.3.1-2017.05-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-
-#KDIR  = /home/yaya/E/Rockchip/3399/rk3399-android-10/kernel
-#ARCH = arm64
-#CROSS_COMPILE = /home/yaya/E/Rockchip/3399/rk3399-android-10/prebuilts/gcc/linux-x86/aarch64/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
+ARCH = arm64
+KDIR = /home/yaya/E/Rockchip/3566/firefly/Android11.0/Firefly-RK356X_Android11.0_git_20210824/RK356X_Android11.0/kernel
+CROSS_COMPILE = /home/yaya/E/Rockchip/3566/firefly/Android11.0/Firefly-RK356X_Android11.0_git_20210824/RK356X_Android11.0/prebuilts/gcc/linux-x86/aarch64/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
 ccflags-y += -DANDROID_PLATFORM
 ccflags-y += -DCONFIG_PLATFORM_ROCKCHIP
 endif
 
 ifeq ($(CONFIG_PLATFORM_ROCKCHIP2), y)
-ARCH = arm64
-KDIR = /home/yaya/E/Rockchip/3566/firefly/Android11.0/Firefly-RK356X_Android11.0_git_20210824/RK356X_Android11.0/kernel
-CROSS_COMPILE = /home/yaya/E/Rockchip/3566/firefly/Android11.0/Firefly-RK356X_Android11.0_git_20210824/RK356X_Android11.0/prebuilts/gcc/linux-x86/aarch64/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
+KDIR := /home/yaya/E/Rockchip/3126/Android6/kernel
+ARCH ?= arm
+CROSS_COMPILE ?= /home/yaya/E/Rockchip/3288/Android5/rk3288_JHY/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
 ccflags-y += -DANDROID_PLATFORM
 ccflags-y += -DCONFIG_PLATFORM_ROCKCHIP2
 endif
 
-
 ifeq ($(CONFIG_PLATFORM_ALLWINNER), y)
-KDIR  = /home/yaya/E/Allwinner/R818/R818/AndroidQ/lichee/kernel/linux-4.9
+KDIR  = /home/yaya/E/Allwinner/A133/Android10/linux-4.9
 ARCH = arm64
-CROSS_COMPILE = /home/yaya/E/Allwinner/R818/R818/AndroidQ/lichee/out/gcc-linaro-5.3.1-2016.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
+CROSS_COMPILE = /home/yaya/E/Allwinner/r818/Android10/lichee/out/gcc-linaro-5.3.1-2016.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
+export CONFIG_SUPPORT_LPM = y
 ccflags-y += -DANDROID_PLATFORM
 endif
 
 ifeq ($(CONFIG_PLATFORM_AMLOGIC), y)
-ccflags-y += -DANDROID_PLATFORM
 ARCH = arm
 CROSS_COMPILE = /home/yaya/D/Workspace/CyberQuantum/JinHaoYue/amls905x3/SDK/20191101-0tt-asop/android9.0/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.9/bin/arm-linux-androidkernel-
 KDIR = /home/yaya/D/Workspace/CyberQuantum/JinHaoYue/amls905x3/SDK/20191101-0tt-asop/android9.0/out/target/product/u202/obj/KERNEL_OBJ/
-
+ccflags-y += -DANDROID_PLATFORM
+export CONFIG_SUPPORT_LPM = y
 endif
 
 ifeq ($(CONFIG_PLATFORM_UBUNTU), y)
@@ -58,9 +61,12 @@ KDIR  = /lib/modules/$(shell uname -r)/build
 PWD   = $(shell pwd)
 KVER = $(shell uname -r)
 MODDESTDIR = /lib/modules/$(KVER)/kernel/drivers/net/wireless/aic8800
-ARCH = x86_64
-CROSS_COMPILE =
+SUBARCH = $(shell uname -m | sed -e s/i.86/i386/ -e s/armv.l/arm/ -e s/aarch64/arm64/)
+ARCH ?= $(SUBARCH)
+CROSS_COMPILE ?=
 endif
+###########################################
+
 all: modules
 modules:
 	make -C $(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
@@ -82,5 +88,5 @@ clean:
 	cd aic8800_bsp/;make clean;cd ..
 	cd aic8800_fdrv/;make clean;cd ..
 	cd aic8800_btlpm/;make clean;cd ..
-	rm -rf modules.order Module.symvers .tmp_versions/
+	rm -rf modules.order Module.symvers .modules.order.cmd .Module.symvers.cmd .tmp_versions/
 

osdrv/extdrv/wireless/aic8800/aic8800_bsp/Makefile

@@ -1,8 +1,8 @@
 CONFIG_SDIO_SUPPORT := y
-CONFIG_SDIO_PWRCTRL := y
+CONFIG_SDIO_PWRCTRL := n
 #CONFIG_AIC_FW_PATH = "/vendor/etc/firmware"
-CONFIG_AIC_FW_PATH ?= "/lib/firmware/aic8800_sdio/aic8800"
-
+#CONFIG_AIC_FW_PATH = "/lib/firmware/aic8800D80"
+CONFIG_AIC_FW_PATH = "/usr/lib/firmware/aic8800_sdio/aic8800_and_aic8800D80"
 export CONFIG_AIC_FW_PATH
 ccflags-y += -DCONFIG_AIC_FW_PATH=\"$(CONFIG_AIC_FW_PATH)\"
 
@@ -12,24 +12,36 @@ ccflags-y += -DAICWF_SDIO_SUPPORT
 ccflags-$(CONFIG_SDIO_PWRCTRL) += -DCONFIG_SDIO_PWRCTRL
 endif
 
-CONFIG_GPIO_WAKEUP = n
+CONFIG_GPIO_WAKEUP ?= n
 CONFIG_M2D_OTA_AUTO_SUPPORT = n
 CONFIG_M2D_OTA_LZMA_SUPPORT = n
 CONFIG_LINK_DET_5G = y
 CONFIG_MCU_MESSAGE = n
 CONFIG_FIRMWARE_ARRAY = n
 # Need to set fw path in BOARD_KERNEL_CMDLINE
-CONFIG_USE_FW_REQUEST = n
+CONFIG_USE_FW_REQUEST ?= n
 CONFIG_FDRV_NO_REG_SDIO = n
 CONFIG_VRF_DCDC_MODE = y
-CONFIG_OOB = n
+CONFIG_OOB ?= n
 CONFIG_PREALLOC_TXQ = y
-CONFIG_ONE_TXQ = n
 CONFIG_DPD = y
 CONFIG_FORCE_DPD_CALIB = y
-CONFIG_RESV_MEM_SUPPORT = y
-CONFIG_AMSDU_RX ?=n
+CONFIG_LOFT_CALIB = n
+CONFIG_EXT_FEM_8800DCDW = n
+CONFIG_RESV_MEM_SUPPORT ?= y
+CONFIG_AMSDU_RX = y
 CONFIG_IRQ_FALL ?= n
+CONFIG_SDIO_BT = y
+CONFIG_RADAR_OR_IR_DETECT =n
+CONFIG_FOR_IPCAM = n
+CONFIG_BAND_STEERING = n
+CONFIG_PRBREQ_REPORT = n
+
+ifeq ($(CONFIG_EXT_FEM_8800DCDW), y)
+CONFIG_DPD = n
+CONFIG_FORCE_DPD_CALIB = n
+CONFIG_LOFT_CALIB = y
+endif
 
 ccflags-$(CONFIG_GPIO_WAKEUP) += -DCONFIG_GPIO_WAKEUP
 ccflags-$(CONFIG_M2D_OTA_AUTO_SUPPORT) += -DCONFIG_M2D_OTA_AUTO_SUPPORT
@@ -42,17 +54,25 @@ ccflags-$(CONFIG_FDRV_NO_REG_SDIO) += -DCONFIG_FDRV_NO_REG_SDIO
 ccflags-$(CONFIG_VRF_DCDC_MODE) += -DCONFIG_VRF_DCDC_MODE
 ccflags-$(CONFIG_OOB) += -DCONFIG_OOB
 ccflags-$(CONFIG_PREALLOC_TXQ) += -DCONFIG_PREALLOC_TXQ
-ccflags-$(CONFIG_ONE_TXQ)  += -DCONFIG_ONE_TXQ
 ccflags-$(CONFIG_DPD)  += -DCONFIG_DPD
 ccflags-$(CONFIG_FORCE_DPD_CALIB) += -DCONFIG_FORCE_DPD_CALIB -DCONFIG_DPD
+ccflags-$(CONFIG_LOFT_CALIB) += -DCONFIG_LOFT_CALIB
+ccflags-$(CONFIG_EXT_FEM_8800DCDW) += -DCONFIG_EXT_FEM_8800DCDW
 ccflags-$(CONFIG_RESV_MEM_SUPPORT) += -DCONFIG_RESV_MEM_SUPPORT
 ccflags-$(CONFIG_AMSDU_RX) += -DCONFIG_AMSDU_RX
 ccflags-$(CONFIG_IRQ_FALL) += -DCONFIG_IRQ_FALL
+ccflags-$(CONFIG_SDIO_BT) += -DCONFIG_SDIO_BT
+ccflags-$(CONFIG_RADAR_OR_IR_DETECT) += -DCONFIG_RADAR_OR_IR_DETECT
+ccflags-$(CONFIG_FOR_IPCAM) += -DCONFIG_FOR_IPCAM
+ccflags-$(CONFIG_BAND_STEERING) += -DCONFIG_BAND_STEERING
+ccflags-$(CONFIG_PRBREQ_REPORT) += -DCONFIG_PRBREQ_REPORT
+
 
 obj-m := $(MODULE_NAME).o
 $(MODULE_NAME)-y := \
 	aic8800dc_compat.o \
 	aic8800d80_compat.o \
+	aic8800d80x2_compat.o \
 	aic_bsp_main.o \
 	aic_bsp_driver.o \
 	aicsdio.o \
@@ -65,7 +85,7 @@ ifeq ($(CONFIG_FIRMWARE_ARRAY),y)
 $(MODULE_NAME)-y +=	aicwf_firmware_array.o
 endif
 
-# Platform support list
+########## Platform support list ##########
 CONFIG_PLATFORM_ROCKCHIP ?= n
 CONFIG_PLATFORM_ROCKCHIP2 ?= n
 CONFIG_PLATFORM_ALLWINNER ?=n
@@ -75,26 +95,6 @@ CONFIG_PLATFORM_UBUNTU ?= y
 
 ifeq ($(CONFIG_PLATFORM_ROCKCHIP), y)
 ccflags-$(CONFIG_PLATFORM_ROCKCHIP) += -DCONFIG_PLATFORM_ROCKCHIP
-#KDIR  ?= /home/yaya/E/Rockchip/3399/rk3399-android-10/kernel
-#ARCH ?= arm64
-#CROSS_COMPILE ?= /home/yaya/E/Rockchip/3399/rk3399-android-10/prebuilts/gcc/linux-x86/aarch64/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
-#KDIR  ?= /home/yaya/E/Rockchip/3288/Android10/kernel/kernel/
-#ARCH ?= arm
-#CROSS_COMPILE ?= /home/yaya/E/Rockchip/3288/Android10/tool/gcc-linaro-6.3.1-2017.05-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-
-#KDIR ?= /home/yaya/E/Rockchip/3229/Android7/RK3229_ANDROID7.1_v1.01_20170914/rk3229_Android7.1_v1.01_xml0914/kernel
-#ARCH ?= arm
-#CROSS_COMPILE ?= /home/yaya/E/Rockchip/3229/Android7/RK3229_ANDROID7.1_v1.01_20170914/rk3229_Android7.1_v1.01_xml0914/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
-#KDIR  ?= /home/yaya/E/Rockchip/3229/Android9/rk3229_android9.0_box/kernel
-#ARCH ?= arm
-#CROSS_COMPILE ?= /home/yaya/E/Rockchip/3229/Android9/rk3229_android9.0_box/prebuilts/gcc/linux-x86/arm/gcc-linaro-6.3.1-2017.05-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-
-#KDIR ?= /home/yaya/E/Rockchip/3566/firefly/Android11.0/Firefly-RK356X_Android11.0_git_20210824/RK356X_Android11.0/kernel
-#KDIR ?= /home/yaya/E/Rockchip/3566/oudu/kernel
-#KDIR ?= /home/yaya/E/Rockchip/3566/shengteng/kernel
-#ARCH ?= arm64
-#CROSS_COMPILE ?= ~/E/Rockchip/3566/Android11/rk3566_rk3568_android11_oranth/prebuilts/gcc/linux-x86/aarch64/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
-#KDIR ?= /home/yaya/E/Rockchip/3328/Android9/SDK/kernel/
-#ARCH ?= arm64
-#CROSS_COMPILE ?= /home/yaya/E/Rockchip/3328/Android9/SDK/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
 KDIR ?= /home/yaya/E/Rockchip/3566/firefly/Android11.0/Firefly-RK356X_Android11.0_git_20210824/RK356X_Android11.0/kernel
 ARCH ?= arm64
 CROSS_COMPILE ?= /home/yaya/E/Rockchip/3566/Android11/rk3566_rk3568_android11_oranth/prebuilts/gcc/linux-x86/aarch64/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
@@ -109,9 +109,6 @@ endif
 
 ifeq ($(CONFIG_PLATFORM_ALLWINNER), y)
 ccflags-$(CONFIG_PLATFORM_ALLWINNER) += -DCONFIG_PLATFORM_ALLWINNER
-#KDIR  ?= /home/yaya/E/Allwinner/A133/a133-sdk/android/longan/out/kernel/build/
-#ARCH ?= arm64
-#CROSS_COMPILE ?= /home/yaya/E/Allwinner/A133/a133-sdk/android/longan/out/gcc-linaro-5.3.1-2016.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
 KDIR  ?= /home/yaya/E/Allwinner/r818/Android10/lichee/kernel/linux-4.9/
 ARCH ?= arm64
 CROSS_COMPILE ?= /home/yaya/E/Allwinner/r818/Android10/android/prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9/bin/aarch64-linux-android-
@@ -140,7 +137,7 @@ MODDESTDIR ?= /lib/modules/$(KVER)/kernel/drivers/net/wireless/
 ARCH ?= x86_64
 CROSS_COMPILE ?=
 endif
-
+###########################################
 
 all: modules
 modules:

osdrv/extdrv/wireless/aic8800/aic8800_bsp/aic8800d80_compat.c

@@ -47,6 +47,27 @@ u32 adaptivity_patch_tbl_8800d80[][2] = {
 	{0x0168, 0x00010000}, //tx_adaptivity_en
 };
 
+#define USER_PWROFST_COVER_CALIB_FLAG	0x01U
+#define USER_CHAN_MAX_TXPWR_EN_FLAG     (0x01U << 1)
+#define USER_TX_USE_ANA_F_FLAG          (0x01U << 2)
+#define USER_APM_PRBRSP_OFFLOAD_DISABLE_FLAG    (0x01U << 3)
+#define USER_HE_MU_EDCA_UPDATE_DISABLE_FLAG     (0x01U << 4)
+#define USER_LOFT_CALIB_DISABLE_FLAG    (0x01U << 6)
+#define USER_CAPA_CALIB_DISABLE_FLAG    (0x01U << 7)
+#define USER_PWR_CALIB_DISABLE_FLAG     (0x01U << 8)
+
+#define CFG_PWROFST_COVER_CALIB     1
+#define CFG_USER_CHAN_MAX_TXPWR_EN  1
+#define CFG_USER_TX_USE_ANA_F       0
+#ifdef CONFIG_PRBREQ_REPORT
+#define CFG_USER_APM_PRBRSP_OFFLOAD_DISABLE 1
+#else
+#define CFG_USER_APM_PRBRSP_OFFLOAD_DISABLE 0
+#endif
+
+
+#define CFG_USER_EXT_FLAGS_EN   (CFG_PWROFST_COVER_CALIB || CFG_USER_CHAN_MAX_TXPWR_EN || CFG_USER_TX_USE_ANA_F || CFG_USER_APM_PRBRSP_OFFLOAD_DISABLE)
+
 u32 patch_tbl_8800d80[][2] = {
 	#ifdef USE_5G
 	{0x00b4, 0xf3010001},
@@ -54,11 +75,33 @@ u32 patch_tbl_8800d80[][2] = {
 	{0x00b4, 0xf3010000},
 	#endif
 #if defined(CONFIG_AMSDU_RX)
-        {0x170, 0x0100000a}
+        {0x170, 0x0100000a},
 #endif
 #ifdef CONFIG_IRQ_FALL
 	{0x00000170, 0x0000010a}, //irqf
 #endif
+
+	#if CFG_USER_EXT_FLAGS_EN
+	{0x0188, 0x00000000
+	#if CFG_PWROFST_COVER_CALIB
+		| USER_PWROFST_COVER_CALIB_FLAG
+	#endif
+	#if CFG_USER_CHAN_MAX_TXPWR_EN
+		| USER_CHAN_MAX_TXPWR_EN_FLAG
+	#endif
+	#if CFG_USER_TX_USE_ANA_F
+		| USER_TX_USE_ANA_F_FLAG
+	#endif
+	#if CFG_USER_APM_PRBRSP_OFFLOAD_DISABLE
+		| USER_APM_PRBRSP_OFFLOAD_DISABLE_FLAG
+	#endif
+        //| USER_CAPA_CALIB_DISABLE_FLAG
+	}, // user_ext_flags
+	#endif
+
+#ifdef CONFIG_RADAR_OR_IR_DETECT
+	{0x019c, 0x00000900}, //enable radar detect
+#endif
 };
 
 #ifdef CONFIG_OOB
@@ -90,11 +133,16 @@ int aicwifi_sys_config_8800d80(struct aic_sdio_dev *sdiodev)
 	return 0;
 }
 
+#define NEW_PATCH_BUFFER_MAP    1
+
 int aicwifi_patch_config_8800d80(struct aic_sdio_dev *sdiodev)
 {
 	const u32 rd_patch_addr = RAM_FMAC_FW_ADDR + 0x0198;
 	u32 aic_patch_addr;
 	u32 config_base, aic_patch_str_base;
+	#if (NEW_PATCH_BUFFER_MAP)
+	u32 patch_buff_addr, patch_buff_base, rd_version_addr, rd_version_val;
+	#endif
 	uint32_t start_addr = 0x0016F800;
 	u32 patch_addr = start_addr;
 	u32 patch_cnt = sizeof(patch_tbl_8800d80)/sizeof(u32)/2;
@@ -126,6 +174,27 @@ int aicwifi_patch_config_8800d80(struct aic_sdio_dev *sdiodev)
 	}
 	aic_patch_str_base = rd_patch_addr_cfm.memdata;
 
+	#if (NEW_PATCH_BUFFER_MAP)
+	rd_version_addr = RAM_FMAC_FW_ADDR + 0x01C;
+	if ((ret = rwnx_send_dbg_mem_read_req(sdiodev, rd_version_addr, &rd_patch_addr_cfm))) {
+		printk("version val[0x%x] rd fail: %d\n", rd_version_addr, ret);
+		return ret;
+	}
+	rd_version_val = rd_patch_addr_cfm.memdata;
+	printk("rd_version_val=%08X\n", rd_version_val);
+	sdiodev->fw_version_uint = rd_version_val;
+	if (rd_version_val > 0x06090100) {
+		patch_buff_addr = rd_patch_addr + 12;
+		ret = rwnx_send_dbg_mem_read_req(sdiodev, patch_buff_addr, &rd_patch_addr_cfm);
+		if (ret) {
+			printk("patch buf rd fail\n");
+			return ret;
+		}
+		patch_buff_base = rd_patch_addr_cfm.memdata;
+		patch_addr = start_addr = patch_buff_base;
+	}
+	#endif
+
 	ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(magic_num), AIC_PATCH_MAGIG_NUM);
 	if (ret) {
 		printk("0x%x write fail\n", AIC_PATCH_ADDR(magic_num));

osdrv/extdrv/wireless/aic8800/aic8800_bsp/aic8800d80x2_compat.c

@@ -0,0 +1,199 @@
+#include "aic8800d80x2_compat.h"
+#include "aic_bsp_driver.h"
+
+#define USER_PWROFST_COVER_CALIB_FLAG           (0x01U << 0)
+#define USER_CHAN_MAX_TXPWR_EN_FLAG             (0x01U << 1)
+#define USER_TX_USE_ANA_F_FLAG                  (0x01U << 2)
+#define USER_APM_PRBRSP_OFFLOAD_DISABLE_FLAG    (0x01U << 3)
+#define USER_HE_MU_EDCA_UPDATE_DISABLE_FLAG     (0x01U << 4)
+
+#define RAM_FMAC_FW_ADDR_8800D80X2           0x120000
+#define RAM_FMAC_RF_FW_ADDR_8800D80X2        0x120000
+
+#define CFG_USER_CHAN_MAX_TXPWR_EN  1
+#define CFG_USER_TX_USE_ANA_F       0
+#ifdef CONFIG_PRBREQ_REPORT
+#define CFG_USER_APM_PRBRSP_OFFLOAD_DISABLE 1
+#else
+#define CFG_USER_APM_PRBRSP_OFFLOAD_DISABLE 0
+#endif
+
+extern int adap_test;
+#define NEW_PATCH_BUFFER_MAP    1
+#define AIC_PATCH_MAGIG_NUM     0x48435450 // "PTCH"
+#define AIC_PATCH_MAGIG_NUM_2   0x50544348 // "HCTP"
+#define AIC_PATCH_BLOCK_MAX     4
+extern struct aicbsp_info_t aicbsp_info;
+extern int adap_test;
+
+typedef u32 (*array2_tbl_t)[2];
+
+typedef struct {
+    uint32_t magic_num;
+    uint32_t pair_start;
+    uint32_t magic_num_2;
+    uint32_t pair_count;
+    uint32_t block_dst[AIC_PATCH_BLOCK_MAX];
+    uint32_t block_src[AIC_PATCH_BLOCK_MAX];
+    uint32_t block_size[AIC_PATCH_BLOCK_MAX]; // word count
+} aic_patch_t;
+
+#define AIC_PATCH_OFST(mem) ((size_t) &((aic_patch_t *)0)->mem)
+#define AIC_PATCH_ADDR(mem) ((u32) (aic_patch_str_base + AIC_PATCH_OFST(mem)))
+
+
+u32 patch_tbl_d80x2[][2] =
+{
+    {0x021c, 0x04000000},//hs amsdu
+    {0x0220, 0x04010101},//ss amsdu
+    {0x0224, 0x50000a01},//hs aggr
+    {0x0228, 0x50000a00},//ss aggr
+
+    {0x01f0, 0x00000001
+        #if CFG_USER_CHAN_MAX_TXPWR_EN
+        | USER_CHAN_MAX_TXPWR_EN_FLAG
+        #endif
+        #if CFG_USER_TX_USE_ANA_F
+        | USER_TX_USE_ANA_F_FLAG
+        #endif
+        #if CFG_USER_APM_PRBRSP_OFFLOAD_DISABLE
+        | USER_APM_PRBRSP_OFFLOAD_DISABLE_FLAG
+        #endif
+    }, // user_ext_flags
+};
+
+//adap test
+u32 adaptivity_patch_tbl_d80x2[][2] = {
+    {0x000C, 0x0000320A}, //linkloss_thd
+    {0x009C, 0x00000000}, //ac_param_conf
+    {0x01D0, 0x00010000}, //tx_adaptivity_en
+};
+
+
+int aicwifi_patch_config_8800d80x2(struct aic_sdio_dev *sdiodev)
+{
+    u32 rd_patch_addr;
+    u32 aic_patch_addr;
+    u32 config_base, aic_patch_str_base;
+    #if (NEW_PATCH_BUFFER_MAP)
+    u32 patch_buff_addr, patch_buff_base, rd_version_addr, rd_version_val;
+    #endif
+    uint32_t start_addr;
+    u32 patch_addr;
+    u32 patch_cnt = sizeof(patch_tbl_d80x2) / 4 / 2;
+    struct dbg_mem_read_cfm rd_patch_addr_cfm;
+    int ret = 0;
+    int cnt = 0;
+    //adap test
+    int adap_patch_cnt = 0;
+
+    if (adap_test) {
+        AICWFDBG(LOGINFO, "%s adap test \r\n", __func__);
+        adap_patch_cnt = sizeof(adaptivity_patch_tbl_d80x2)/sizeof(u32)/2;
+    }
+
+    rd_patch_addr = RAM_FMAC_FW_ADDR_8800D80X2 + 0x01A8;
+    aic_patch_addr = rd_patch_addr + 8;
+
+    AICWFDBG(LOGINFO, "Read FW mem: %08x\n", rd_patch_addr);
+    if ((ret = rwnx_send_dbg_mem_read_req(sdiodev, rd_patch_addr, &rd_patch_addr_cfm))) {
+        AICWFDBG(LOGERROR, "setting base[0x%x] rd fail: %d\n", rd_patch_addr, ret);
+        return ret;
+    }
+    AICWFDBG(LOGINFO, "rd_patch_addr_cfm %x=%x\n", rd_patch_addr_cfm.memaddr, rd_patch_addr_cfm.memdata);
+    config_base = rd_patch_addr_cfm.memdata;
+
+    if ((ret = rwnx_send_dbg_mem_read_req(sdiodev, aic_patch_addr, &rd_patch_addr_cfm))) {
+        AICWFDBG(LOGERROR, "patch_str_base[0x%x] rd fail: %d\n", aic_patch_addr, ret);
+        return ret;
+    }
+    AICWFDBG(LOGINFO, "rd_patch_addr_cfm %x=%x\n", rd_patch_addr_cfm.memaddr, rd_patch_addr_cfm.memdata);
+    aic_patch_str_base = rd_patch_addr_cfm.memdata;
+
+    #if (NEW_PATCH_BUFFER_MAP)
+    rd_version_addr = RAM_FMAC_FW_ADDR_8800D80X2 + 0x01C;
+    if ((ret = rwnx_send_dbg_mem_read_req(sdiodev, rd_version_addr, &rd_patch_addr_cfm))) {
+        AICWFDBG(LOGERROR, "version val[0x%x] rd fail: %d\n", rd_version_addr, ret);
+        return ret;
+    }
+    rd_version_val = rd_patch_addr_cfm.memdata;
+    AICWFDBG(LOGINFO, "rd_version_val=%08X\n", rd_version_val);
+    sdiodev->fw_version_uint = rd_version_val;
+    patch_buff_addr = rd_patch_addr + 12;
+    ret = rwnx_send_dbg_mem_read_req(sdiodev, patch_buff_addr, &rd_patch_addr_cfm);
+    if (ret) {
+        AICWFDBG(LOGERROR, "patch buf rd fail\n");
+        return ret;
+    }
+    AICWFDBG(LOGINFO, "rd_patch_addr_cfm %x=%x\n", rd_patch_addr_cfm.memaddr, rd_patch_addr_cfm.memdata);
+    patch_buff_base = rd_patch_addr_cfm.memdata;
+    patch_addr = start_addr = patch_buff_base;
+    #endif
+
+    if ((ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(magic_num), AIC_PATCH_MAGIG_NUM))) {
+        AICWFDBG(LOGERROR, "maigic_num[0x%x] write fail: %d\n", AIC_PATCH_ADDR(magic_num), ret);
+        return ret;
+    }
+
+    if ((ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(magic_num_2), AIC_PATCH_MAGIG_NUM_2))) {
+        AICWFDBG(LOGERROR, "maigic_num[0x%x] write fail: %d\n", AIC_PATCH_ADDR(magic_num_2), ret);
+        return ret;
+    }
+
+    if ((ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(pair_start), patch_addr))) {
+        AICWFDBG(LOGERROR, "pair_start[0x%x] write fail: %d\n", AIC_PATCH_ADDR(pair_start), ret);
+        return ret;
+    }
+
+    if ((ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(pair_count), patch_cnt + adap_patch_cnt))) {
+        AICWFDBG(LOGERROR, "pair_count[0x%x] write fail: %d\n", AIC_PATCH_ADDR(pair_count), ret);
+        return ret;
+    }
+
+    for (cnt = 0; cnt < patch_cnt; cnt++) {
+        if ((ret = rwnx_send_dbg_mem_write_req(sdiodev, start_addr+8*cnt, patch_tbl_d80x2[cnt][0]+config_base))) {
+            AICWFDBG(LOGERROR, "%x write fail\n", start_addr+8*cnt);
+            return ret;
+        }
+        if ((ret = rwnx_send_dbg_mem_write_req(sdiodev, start_addr+8*cnt+4, patch_tbl_d80x2[cnt][1]))) {
+            AICWFDBG(LOGERROR, "%x write fail\n", start_addr+8*cnt+4);
+            return ret;
+        }
+    }
+
+    if (adap_test){
+        int tmp_cnt = patch_cnt + adap_patch_cnt;
+        AICWFDBG(LOGINFO, "%s set adap_test patch \r\n", __func__);
+        for (cnt = patch_cnt; cnt < tmp_cnt; cnt++) {
+            int tbl_idx = cnt - patch_cnt;
+            if ((ret = rwnx_send_dbg_mem_write_req(sdiodev, start_addr+8*cnt, adaptivity_patch_tbl_d80x2[tbl_idx][0]+config_base))) {
+                AICWFDBG(LOGERROR, "%x write fail\n", start_addr+8*cnt);
+            return ret;
+            }
+            if ((ret = rwnx_send_dbg_mem_write_req(sdiodev, start_addr+8*cnt+4, adaptivity_patch_tbl_d80x2[tbl_idx][1]))) {
+                AICWFDBG(LOGERROR, "%x write fail\n", start_addr+8*cnt+4);
+            return ret;
+            }
+        }
+    }
+
+    if ((ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(block_size[0]), 0))) {
+        AICWFDBG(LOGERROR, "block_size[0x%x] write fail: %d\n", AIC_PATCH_ADDR(block_size[0]), ret);
+        return ret;
+    }
+    if ((ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(block_size[1]), 0))) {
+        AICWFDBG(LOGERROR, "block_size[0x%x] write fail: %d\n", AIC_PATCH_ADDR(block_size[1]), ret);
+        return ret;
+    }
+    if ((ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(block_size[2]), 0))) {
+        AICWFDBG(LOGERROR, "block_size[0x%x] write fail: %d\n", AIC_PATCH_ADDR(block_size[2]), ret);
+        return ret;
+    }
+    if ((ret = rwnx_send_dbg_mem_write_req(sdiodev, AIC_PATCH_ADDR(block_size[3]), 0))) {
+        AICWFDBG(LOGERROR, "block_size[0x%x] write fail: %d\n", AIC_PATCH_ADDR(block_size[3]), ret);
+        return ret;
+    }
+
+    return 0;
+}
+

osdrv/extdrv/wireless/aic8800/aic8800_bsp/aic8800d80x2_compat.h

@@ -0,0 +1,12 @@
+#ifndef _AIC8800D80x2_COMPAT_H_
+#define _AIC8800D80x2_COMPAT_H_
+
+#include "aicsdio.h"
+
+
+int aicwifi_patch_config_8800d80x2(struct aic_sdio_dev *sdiodev);
+
+
+
+#endif
+

osdrv/extdrv/wireless/aic8800/aic8800_bsp/aic8800dc_compat.c

@@ -52,6 +52,7 @@ u32 syscfg_tbl_masked_8800dc[][3] = {
     {0x700010A0, (0x1 << 11), (0x1 << 11)},
     {0x70001034, ((0x1 << 20) | (0x7 << 26)), ((0x0 << 20) | (0x2 << 26))},
     {0x70001038, (0x1 << 8), (0x1 << 8)},
+    {0x70001084, (0x3 << 13), (0x0 << 13)},
     {0x70001094, (0x3 << 2), (0x0 << 2)},
     {0x700021D0, ((0x1 << 5) | (0x1 << 6)), ((0x1 << 5) | (0x1 << 6))},
     {0x70001000, ((0x1 << 0) | (0x1 << 20) | (0x1 << 22)),
@@ -69,6 +70,7 @@ u32 syscfg_tbl_masked_8800dc[][3] = {
     {0x700010A0, (0x1 << 11), (0x1 << 11)},
     {0x70001034, ((0x1 << 20) | (0x7 << 26)), ((0x0 << 20) | (0x2 << 26))},
     {0x70001038, (0x1 << 8), (0x1 << 8)},
+    {0x70001084, (0x3 << 13), (0x0 << 13)},
     {0x70001094, (0x3 << 2), (0x0 << 2)},
     {0x700021D0, ((0x1 << 5) | (0x1 << 6)), ((0x1 << 5) | (0x1 << 6))},
     {0x70001000, ((0x1 << 0) | (0x1 << 20) | (0x1 << 22)),
@@ -94,6 +96,7 @@ u32 syscfg_tbl_masked_8800dc_h[][3] = {
     {0x700010A0, (0x1 << 11), (0x1 << 11)},
     //{0x70001034, ((0x1 << 20) | (0x7 << 26)), ((0x0 << 20) | (0x2 << 26))},
     {0x70001038, (0x1 << 8), (0x1 << 8)},
+    {0x70001084, (0x3 << 13), (0x0 << 13)},
     {0x70001094, (0x3 << 2), (0x0 << 2)},
     {0x700021D0, ((0x1 << 5) | (0x1 << 6)), ((0x1 << 5) | (0x1 << 6))},
     #if defined(CONFIG_VRF_DCDC_MODE)
@@ -128,6 +131,9 @@ u32 patch_tbl_wifisetting_8800dc_u02[][2] =
 #else
 	{0x0124,0x01001E01}
 #endif
+#ifdef CONFIG_PRBREQ_REPORT
+	{0x0138, 0x00010a00}, //apm probe resp offload en
+#endif
 };
 
 
@@ -1323,7 +1329,7 @@ uint32_t agc_cfg_ram[] = {
     0x00000000
 };
 
-
+#if !defined(CONFIG_EXT_FEM_8800DCDW)
 uint32_t txgain_map[96] =  {
 #ifdef CONFIG_FPGA_VERIFICATION
     0x20c0c971,
@@ -1461,8 +1467,8 @@ uint32_t txgain_map[96] =  {
     0x00ffc88b,
     0x00ffc979,
     0x00ffc989,
-    0x00ffca7d,
-    0x00ffca88,
+    0x00ffcc4b,
+    0x00ffcc54,
     0x00ffcc5e,
     0x00ffcc69,
     0x00ffcc78,
@@ -1494,8 +1500,8 @@ uint32_t txgain_map[96] =  {
     0x00ffc88b,
     0x00ffc979,
     0x00ffc989,
-    0x00ffca7d,
-    0x00ffca88,
+    0x00ffcc4b,
+    0x00ffcc54,
     0x00ffcc5e,
     0x00ffcc69,
     0x00ffcc78,
@@ -1503,9 +1509,9 @@ uint32_t txgain_map[96] =  {
     0x00ffcd70,
     0x00ffcd80,
     0x00ffcd90,
-    0x00ffce80,
-    0x00ffce93,
-    0x00ffcf90,
+    0x00ffcf68,
+    0x00ffcf75,
+    0x00ffcf83,
     0x00ffc080,
     0x00ffc090,
     0x00ffc180,
@@ -1564,8 +1570,8 @@ const uint32_t txgain_map_h[96] =
     0xffc879, //8
     0xffc96b, //9
     0xffc979, //10
-    0xffca6b, //11
-    0xffca79, //12
+    0xffcc45, //11
+    0xffcc4d, //12
     0xffcc56, //13
     0xffcc60, //14
     0xffcc6b, //15
@@ -1597,15 +1603,15 @@ const uint32_t txgain_map_h[96] =
     0xffc879, //8
     0xffc96b, //9
     0xffc979, //10
-    0xffca6b, //11
-    0xffca79, //12
+    0xffcc45, //11
+    0xffcc4d, //12
     0xffcc56, //13
     0xffcc60, //14
     0xffcc6b, //15
     0xffcc79, //16
     0xffcd72, //17
-    0xffce60, //18
-    0xffce72, //19
+    0xffcf5b, //18
+    0xffcf66, //19
     0xffcf72, //20
     0xffcf80, //21
     0xffcf90, //22
@@ -1628,6 +1634,213 @@ const uint32_t txgain_map_h[96] =
     0xffc86b, //7
 };
 
+#else /* #ifdef CONFIG_EXT_FEM_8800DCDW */
+const uint32_t txgain_map_femkct[96] =
+{
+    //11b
+    0x00ffd780,//15
+    0x00ffd872,//16
+    0x00ffd880,//17
+    0x00ffd972,//18
+    0x00ffd980,//19
+    0x00ffda72,//20
+    0x00ffda80,//21
+    0x00ffdb72,//22
+    0x00ffdb80,//23
+    0x00ffdc72,//24
+    0x00ffdc80,//25
+    0x00ffdd72,//26
+    0x00ffdd80,//27
+    0x00ffde72,//28
+    0x00ffde80,//29
+    0x00ffdf72,//30
+    0x00ffd072,//-1
+    0x00ffd072,//0
+    0x00ffd080,//1
+    0x00ffd172,//2
+    0x00ffd180,//3
+    0x00ffd272,//4
+    0x00ffd280,//5
+    0x00ffd36d,//6
+    0x00ffd379,//7
+    0x00ffd46d,//8
+    0x00ffd479,//9
+    0x00ffd572,//10
+    0x00ffd580,//11
+    0x00ffd672,//12
+    0x00ffd680,//13
+    0x00ffd772,//14
+    //high
+    0x00ffc872,//11
+    0x00ffc880,//12
+    0x00ffc972,//13
+    0x00ffc980,//14
+    0x00ffca72,//15
+    0x00ffca80,//16
+    0x00ffcb72,//17
+    0x00ffcb80,//18
+    0x00ffcc72,//19
+    0x00ffcc80,//20
+    0x00ffcd72,//21
+    0x00ffcd80,//22
+    0x00ffce72,//23
+    0x00ffce80,//24
+    0x00ffcf72,//25
+    0x00ffcf80,//26
+    0x00ffc072,//-5
+    0x00ffc080,//-4
+    0x00ffc172,//-3
+    0x00ffc180,//-2
+    0x00ffc272,//-1
+    0x00ffc280,//0
+    0x00ffc372,//1
+    0x00ffc380,//2
+    0x00ffc472,//3
+    0x00ffc480,//4
+    0x00ffc572,//5
+    0x00ffc580,//6
+    0x00ffc672,//7
+    0x00ffc680,//8
+    0x00ffc772,//9
+    0x00ffc780,//10
+    //low
+    0x00ffc872,//11
+    0x00ffc880,//12
+    0x00ffc972,//13
+    0x00ffc980,//14
+    0x00ffca72,//15
+    0x00ffca80,//16
+    0x00ffcb72,//17
+    0x00ffcb80,//18
+    0x00ffcc72,//19
+    0x00ffcc80,//20
+    0x00ffcd72,//21
+    0x00ffcd80,//22
+    0x00ffce72,//23
+    0x00ffce80,//24
+    0x00ffcf72,//26
+    0x00ffcf80,//27
+    0x00ffc072,//-5
+    0x00ffc080,//-4
+    0x00ffc172,//-3
+    0x00ffc180,//-2
+    0x00ffc272,//-1
+    0x00ffc280,//0
+    0x00ffc372,//1
+    0x00ffc380,//2
+    0x00ffc472,//3
+    0x00ffc480,//4
+    0x00ffc572,//5
+    0x00ffc580,//6
+    0x00ffc672,//7
+    0x00ffc680,//8
+    0x00ffc772,//9
+    0x00ffc780,//10
+};
+
+const uint32_t txgain_map_femkct_h[96] =
+{
+    //11b
+    0x00ffd86c,//15
+    0x00ffd879,//16
+    0x00ffd96c,//17
+    0x00ffd979,//18
+    0x00ffd988,//19
+    0x00ffda6c,//20
+    0x00ffda79,//21
+    0x00ffdb6c,//22
+    0x00ffdb79,//23
+    0x00ffdc6c,//24
+    0x00ffdc79,//25
+    0x00ffdd6c,//26
+    0x00ffdd79,//27
+    0x00ffde6c,//28
+    0x00ffde79,//29
+    0x00ffdf6c,//30
+    0x00ffd06c,//-1
+    0x00ffd06c,//0
+    0x00ffd079,//1
+    0x00ffd16c,//2
+    0x00ffd179,//3
+    0x00ffd26c,//4
+    0x00ffd279,//5
+    0x00ffd372,//6
+    0x00ffd467,//7
+    0x00ffd472,//8
+    0x00ffd56c,//9
+    0x00ffd579,//10
+    0x00ffd66c,//11
+    0x00ffd679,//12
+    0x00ffd76c,//13
+    0x00ffd779,//14
+    //high
+    0x00ffc879,//11
+    0x00ffc96c,//12
+    0x00ffc979,//13
+    0x00ffca6c,//14
+    0x00ffca79,//15
+    0x00ffcb6c,//16
+    0x00ffcb79,//17
+    0x00ffcc6c,//18
+    0x00ffcc79,//19
+    0x00ffcc88,//20
+    0x00ffcd6c,//21
+    0x00ffcd79,//22
+    0x00ffce6c,//23
+    0x00ffce79,//24
+    0x00ffcf6c,//25
+    0x00ffcf79,//26
+    0x00ffc079,//-5
+    0x00ffc16c,//-4
+    0x00ffc179,//-3
+    0x00ffc26c,//-2
+    0x00ffc279,//-1
+    0x00ffc36c,//0
+    0x00ffc379,//1
+    0x00ffc46c,//2
+    0x00ffc479,//3
+    0x00ffc56c,//4
+    0x00ffc579,//5
+    0x00ffc66c,//6
+    0x00ffc679,//7
+    0x00ffc76c,//8
+    0x00ffc779,//9
+    0x00ffc86c,//10
+    //low
+    0x00ffc879,//11
+    0x00ffc96c,//12
+    0x00ffc979,//13
+    0x00ffca6c,//14
+    0x00ffca79,//15
+    0x00ffcb6c,//16
+    0x00ffcb79,//17
+    0x00ffcc6c,//18
+    0x00ffcc79,//19
+    0x00ffcc88,//20
+    0x00ffcd6c,//21
+    0x00ffcd79,//22
+    0x00ffce6c,//23
+    0x00ffce79,//24
+    0x00ffcf6c,//25
+    0x00ffcf79,//26
+    0x00ffc079,//-5
+    0x00ffc16c,//-4
+    0x00ffc179,//-3
+    0x00ffc26c,//-2
+    0x00ffc279,//-1
+    0x00ffc36c,//0
+    0x00ffc379,//1
+    0x00ffc46c,//2
+    0x00ffc479,//3
+    0x00ffc56c,//4
+    0x00ffc579,//5
+    0x00ffc66c,//6
+    0x00ffc679,//7
+    0x00ffc76c,//8
+    0x00ffc779,//9
+    0x00ffc86c,//10
+};
+#endif
 
 u32 jump_tbl[][2] =
 {
@@ -1689,10 +1902,61 @@ u32 patch_tbl_rf_func[][2] =
     {0x00110bf0, 0x00180001},
 };
 
+
+//adap test
+u32 adaptivity_patch_tbl_8800dc[][2] = {
+    {0x000C, 0x0000320A}, //linkloss_thd
+    {0x009C, 0x00000000}, //ac_param_conf
+    {0x0128, 0xF6140001}, //tx_adaptivity_en
+};
+//adap test
+
+
 static u8 chip_id = 0;
 #define CHIP_ID_H_MASK  0xC0
 #define IS_CHIP_ID_H()  ((chip_id & CHIP_ID_H_MASK) == CHIP_ID_H_MASK)
 
+//Crystal provided by CPU (start)
+int set_bbpll_config(struct aic_sdio_dev *rwnx_hw){
+//    {0x40505010, 0x7C301010},//bbpll
+	int ret = 0;
+	struct dbg_mem_read_cfm rd_mem_addr_cfm;
+
+	//Read crystal provided by CPU or not.
+    ret = rwnx_send_dbg_mem_read_req(rwnx_hw, 0x40500148, &rd_mem_addr_cfm);
+    if (ret) {
+		AICWFDBG(LOGERROR, "%x rd fail: %d\n", 0x40500148, ret);
+        return -1;
+    }
+
+	AICWFDBG(LOGDEBUG, "%s rd_mem_addr_cfm.memdata:%x \r\n", __func__, rd_mem_addr_cfm.memdata);
+
+	if(!(rd_mem_addr_cfm.memdata & 0x01)){
+		AICWFDBG(LOGINFO, "%s Crystal not provided by CPU \r\n", __func__);
+		return 0;
+	}else{
+		AICWFDBG(LOGINFO, "%s Crystal provided by CPU \r\n", __func__);
+		//Read 0x40505010 value to check bbpll set or not.
+		ret = rwnx_send_dbg_mem_read_req(rwnx_hw, 0x40505010, &rd_mem_addr_cfm);
+		if(ret < 0){
+			AICWFDBG(LOGERROR, "%s error ret_val:%d\r\n", __func__, ret);
+			return -1;
+		}
+
+		if((rd_mem_addr_cfm.memdata >> 29) == 3){
+			AICWFDBG(LOGERROR, "%s Not need to set \r\n", __func__);
+			return 0;
+		}else{
+			rd_mem_addr_cfm.memdata |= ((0x1 << 29) | (0x1 << 30));
+			rd_mem_addr_cfm.memdata &= (~(0x1 << 31));
+			rwnx_send_dbg_mem_write_req(rwnx_hw, 0x40505010, rd_mem_addr_cfm.memdata);
+		}
+	}
+	return 0;
+}
+//Crystal provided by CPU (end)
+
+
 void system_config_8800dc(struct aic_sdio_dev *rwnx_hw)
 {
     int syscfg_num;
@@ -1724,6 +1988,14 @@ void system_config_8800dc(struct aic_sdio_dev *rwnx_hw)
     //printk("%x=%x\n", rd_mem_addr_cfm.memaddr, rd_mem_addr_cfm.memdata);
 	AICWFDBG(LOGINFO, "chip_id=%x, chip_sub_id=%x!!\n", chip_id, chip_sub_id);
 
+	//Crystal provided by CPU (start)
+	ret = set_bbpll_config(rwnx_hw);
+    if (ret) {
+		AICWFDBG(LOGERROR, "set_bbpll_config fail: %d\n", ret);
+        return;
+    }
+	//Crystal provided by CPU (end)
+
 
 	ret = rwnx_send_dbg_mem_read_req(rwnx_hw, 0x40500010, &rd_mem_addr_cfm);
 	AICWFDBG(LOGDEBUG, "[0x40500010]=%x\n", rd_mem_addr_cfm.memdata);
@@ -1816,6 +2088,7 @@ void system_config_8800dc(struct aic_sdio_dev *rwnx_hw)
 
 }
 
+extern int adap_test;
 
 void aicwf_patch_config_8800dc(struct aic_sdio_dev *rwnx_hw)
 {
@@ -1838,6 +2111,11 @@ void aicwf_patch_config_8800dc(struct aic_sdio_dev *rwnx_hw)
         u32 jump_tbl_size = 0;
         u32 patch_tbl_func_num = 0;
 
+	//adap test
+	int adap_patch_num = 0;
+	//adap test
+
+
         array2_tbl_t jump_tbl_base = NULL;
         array2_tbl_t patch_tbl_func_base = NULL;
 		array2_tbl_t patch_tbl_wifisetting_8800dc_base = NULL;
@@ -1895,6 +2173,19 @@ void aicwf_patch_config_8800dc(struct aic_sdio_dev *rwnx_hw)
 			}
 		}
 
+//adap test
+		if(adap_test){
+            AICWFDBG(LOGINFO, "%s for adaptivity test \r\n", __func__);
+			adap_patch_num = sizeof(adaptivity_patch_tbl_8800dc)/sizeof(u32)/2;
+			for(cnt = 0; cnt < adap_patch_num; cnt++)
+			{
+				if((ret = rwnx_send_dbg_mem_write_req(rwnx_hw, wifisetting_cfg_addr + adaptivity_patch_tbl_8800dc[cnt][0], adaptivity_patch_tbl_8800dc[cnt][1]))) {
+					AICWFDBG(LOGERROR, "%x write fail\n", wifisetting_cfg_addr + adaptivity_patch_tbl_8800dc[cnt][0]);
+				}
+			}
+		}
+//adap test
+
         if (ldpc_cfg_size > 512) {// > 0.5KB data
             for (i = 0; i < (ldpc_cfg_size - 512); i += 512) {//each time write 0.5KB
                 ret = rwnx_send_dbg_mem_block_write_req(rwnx_hw, ldpc_cfg_addr + i, 512, ldpc_cfg_ram + i / 4);
@@ -1931,11 +2222,21 @@ void aicwf_patch_config_8800dc(struct aic_sdio_dev *rwnx_hw)
 
         #if !defined(CONFIG_FPGA_VERIFICATION)
         if ((IS_CHIP_ID_H())) {
+            #if defined(CONFIG_EXT_FEM_8800DCDW)
+            txgain_cfg_size = sizeof(txgain_map_femkct_h);
+            txgain_cfg_array = (u32 *)txgain_map_femkct_h;
+            #else
             txgain_cfg_size = sizeof(txgain_map_h);
             txgain_cfg_array = (u32 *)txgain_map_h;
+            #endif
         } else {
+            #if defined(CONFIG_EXT_FEM_8800DCDW)
+            txgain_cfg_size = sizeof(txgain_map_femkct);
+            txgain_cfg_array = (u32 *)txgain_map_femkct;
+            #else
             txgain_cfg_size = sizeof(txgain_map);
             txgain_cfg_array = (u32 *)txgain_map;
+            #endif
         }
         ret = rwnx_send_dbg_mem_block_write_req(rwnx_hw, txgain_cfg_addr, txgain_cfg_size, txgain_cfg_array);
         if (ret) {
@@ -2223,4 +2524,116 @@ int aicwf_dpd_result_write_8800dc(void *buf, int buf_len)
 #endif /* !CONFIG_FORCE_DPD_CALIB */
 #endif
 
+#ifdef CONFIG_LOFT_CALIB
+int aicwf_loft_calib_8800dc(struct aic_sdio_dev *sdiodev, rf_misc_ram_lite_t *loft_res)
+{
+    int ret = 0;
+    uint32_t fw_addr, boot_type;
+    int valid_flag;
 
+    printk("%s\n", __func__);
+
+    ret = aicwf_misc_ram_valid_check_8800dc(sdiodev, &valid_flag);
+    if (ret) {
+        AICWFDBG(LOGINFO, "misc ram check fail: %d\n", ret);
+        return ret;
+    }
+    if (valid_flag) {
+        AICWFDBG(LOGINFO, "misc ram valid, skip calib process\n");
+        return ret;
+    }
+    ret = aicwf_plat_calib_load_8800dc(sdiodev);
+    if (ret) {
+        AICWFDBG(LOGINFO, "load calib bin fail: %d\n", ret);
+        return ret;
+    }
+    /* fw start */
+    fw_addr = 0x00130009;
+    boot_type = HOST_START_APP_FNCALL;
+    AICWFDBG(LOGINFO, "Start app: %08x, %d\n", fw_addr, boot_type);
+    ret = rwnx_send_dbg_start_app_req(sdiodev, fw_addr, boot_type, NULL);
+    if (ret) {
+        AICWFDBG(LOGINFO, "start app fail: %d\n", ret);
+        return ret;
+    }
+    { // read loft res
+        const uint32_t cfg_base = 0x10164;
+        struct dbg_mem_read_cfm cfm;
+        uint32_t misc_ram_addr;
+        uint32_t ram_base_addr, ram_word_cnt;
+        int i;
+        ret = rwnx_send_dbg_mem_read_req(sdiodev, cfg_base + 0x14, &cfm);
+        if (ret) {
+            AICWFDBG(LOGERROR, "rf misc ram[0x%x] rd fail: %d\n", cfg_base + 0x14, ret);
+            return ret;
+        }
+        misc_ram_addr = cfm.memdata;
+        // bit_mask
+        ram_base_addr = misc_ram_addr + offsetof(rf_misc_ram_t, bit_mask);
+        ram_word_cnt = (MEMBER_SIZE(rf_misc_ram_t, bit_mask) + MEMBER_SIZE(rf_misc_ram_t, reserved)) / 4;
+        for (i = 0; i < ram_word_cnt; i++) {
+            ret = rwnx_send_dbg_mem_read_req(sdiodev, ram_base_addr + i * 4, &cfm);
+            if (ret) {
+                AICWFDBG(LOGERROR, "bit_mask[0x%x] rd fail: %d\n",  ram_base_addr + i * 4, ret);
+                return ret;
+            }
+            loft_res->bit_mask[i] = cfm.memdata;
+        }
+        // loft_res
+        ram_base_addr = misc_ram_addr + offsetof(rf_misc_ram_t, loft_res);
+        ram_word_cnt = MEMBER_SIZE(rf_misc_ram_t, loft_res) / 4;
+        for (i = 0; i < ram_word_cnt; i++) {
+            ret = rwnx_send_dbg_mem_read_req(sdiodev, ram_base_addr + i * 4, &cfm);
+            if (ret) {
+                AICWFDBG(LOGERROR, "loft_res[0x%x] rd fail: %d\n",  ram_base_addr + i * 4, ret);
+                return ret;
+            }
+            loft_res->loft_res[i] = cfm.memdata;
+        }
+    }
+    return ret;
+}
+
+int aicwf_loft_result_apply_8800dc(struct aic_sdio_dev *sdiodev, rf_misc_ram_lite_t *loft_res)
+{
+    int ret = 0;
+    uint32_t cfg_base = 0x10164;
+    struct dbg_mem_read_cfm cfm;
+    uint32_t misc_ram_addr;
+    uint32_t ram_base_addr, ram_byte_cnt;
+    AICWFDBG(LOGINFO, "bit_mask[1]=%x\n", loft_res->bit_mask[1]);
+    if (loft_res->bit_mask[1] == 0) {
+        AICWFDBG(LOGERROR, "void loft_res, bypass it.\n");
+        return 0;
+    }
+    if (testmode == FW_RFTEST_MODE) {
+        cfg_base = RAM_LMAC_FW_ADDR + 0x0164;
+    }
+    if ((ret = rwnx_send_dbg_mem_read_req(sdiodev, cfg_base + 0x14, &cfm))) {
+        AICWFDBG(LOGERROR, "rf misc ram[0x%x] rd fail: %d\n", cfg_base + 0x14, ret);
+        return ret;
+    }
+    misc_ram_addr = cfm.memdata;
+    AICWFDBG(LOGINFO, "misc_ram_addr: %x\n", misc_ram_addr);
+    /* Copy loft_res on the Embedded side */
+    // bit_mask
+    AICWFDBG(LOGINFO, "bit_mask[0]=%x\n", loft_res->bit_mask[0]);
+    ram_base_addr = misc_ram_addr + offsetof(rf_misc_ram_t, bit_mask);
+    ram_byte_cnt = MEMBER_SIZE(rf_misc_ram_t, bit_mask) + MEMBER_SIZE(rf_misc_ram_t, reserved);
+    ret = rwnx_send_dbg_mem_block_write_req(sdiodev, ram_base_addr, ram_byte_cnt, (u32 *)&loft_res->bit_mask[0]);
+    if (ret) {
+        AICWFDBG(LOGERROR, "bit_mask wr fail: %x, ret:%d\r\n", ram_base_addr, ret);
+        return ret;
+    }
+    // loft_res
+    AICWFDBG(LOGINFO, "loft_res[0]=%x\n", loft_res->loft_res[0]);
+    ram_base_addr = misc_ram_addr + offsetof(rf_misc_ram_t, loft_res);
+    ram_byte_cnt = MEMBER_SIZE(rf_misc_ram_t, loft_res);
+    ret = rwnx_send_dbg_mem_block_write_req(sdiodev, ram_base_addr, ram_byte_cnt, (u32 *)&loft_res->loft_res[0]);
+    if (ret) {
+        AICWFDBG(LOGERROR, "loft_res wr fail: %x, ret:%d\r\n", ram_base_addr, ret);
+        return ret;
+    }
+    return ret;
+}
+#endif

osdrv/extdrv/wireless/aic8800/aic8800_bsp/aic8800dc_compat.h

@@ -30,6 +30,10 @@ int aicwf_dpd_result_load_8800dc(struct aic_sdio_dev *sdiodev, rf_misc_ram_lite_
 int aicwf_dpd_result_write_8800dc(void *buf, int buf_len);
 #endif/* !CONFIG_FORCE_DPD_CALIB */
 #endif
+#ifdef CONFIG_LOFT_CALIB
+int aicwf_loft_calib_8800dc(struct aic_sdio_dev *sdiodev, rf_misc_ram_lite_t *loft_res);
+int aicwf_loft_result_apply_8800dc(struct aic_sdio_dev *sdiodev, rf_misc_ram_lite_t *loft_res);
+#endif
 
 #endif
 

osdrv/extdrv/wireless/aic8800/aic8800_bsp/aic_bsp_driver.c

@@ -27,6 +27,7 @@
 #include "md5.h"
 #include "aic8800dc_compat.h"
 #include "aic8800d80_compat.h"
+#include "aic8800d80x2_compat.h"
 #include "aicwf_firmware_array.h"
 #define FW_PATH_MAX 200
 
@@ -242,9 +243,12 @@ void rwnx_cmd_mgr_init(struct rwnx_cmd_mgr *cmd_mgr)
 
 void rwnx_cmd_mgr_deinit(struct rwnx_cmd_mgr *cmd_mgr)
 {
-	cmd_mgr->print(cmd_mgr);
-	cmd_mgr->drain(cmd_mgr);
-	cmd_mgr->print(cmd_mgr);
+	if(cmd_mgr->print)
+		cmd_mgr->print(cmd_mgr);
+	if(cmd_mgr->drain)
+		cmd_mgr->drain(cmd_mgr);
+	if(cmd_mgr->print)
+		cmd_mgr->print(cmd_mgr);
 	memset(cmd_mgr, 0, sizeof(*cmd_mgr));
 }
 
@@ -262,7 +266,7 @@ void rwnx_set_cmd_tx(void *dev, struct lmac_msg *msg, uint len)
     if (sdiodev->chipid == PRODUCT_ID_AIC8801 || sdiodev->chipid == PRODUCT_ID_AIC8800DC ||
         sdiodev->chipid == PRODUCT_ID_AIC8800DW)
         buffer[3] = 0x0;
-    else if (sdiodev->chipid == PRODUCT_ID_AIC8800D80)
+    else if (sdiodev->chipid == PRODUCT_ID_AIC8800D80 || sdiodev->chipid == PRODUCT_ID_AIC8800D80X2)
 	    buffer[3] = crc8_ponl_107(&buffer[0], 3); // crc8
 	index += 4;
 	//there is a dummy word
@@ -984,7 +988,7 @@ int aicwf_plat_rftest_load_8800dc(struct aic_sdio_dev *sdiodev)
     return ret;
 }
 
-#ifdef CONFIG_DPD
+#if defined(CONFIG_DPD) || defined(CONFIG_LOFT_CALIB)
 int aicwf_misc_ram_valid_check_8800dc(struct aic_sdio_dev *sdiodev, int *valid_out)
 {
     int ret = 0;
@@ -998,7 +1002,7 @@ int aicwf_misc_ram_valid_check_8800dc(struct aic_sdio_dev *sdiodev, int *valid_o
         *valid_out = 0;
     }
     if (testmode == FW_RFTEST_MODE) {
-		
+
 	    uint32_t vect1 = 0;
 	    uint32_t vect2 = 0;
 	    cfg_base = RAM_LMAC_FW_ADDR + 0x0004;
@@ -1061,19 +1065,21 @@ int aicwf_plat_calib_load_8800dc(struct aic_sdio_dev *sdiodev)
     if (chip_sub_id == 1) {
         ret = rwnx_plat_bin_fw_upload_android(sdiodev, ROM_FMAC_CALIB_ADDR, RWNX_MAC_CALIB_NAME_8800DC_U02);
         if (ret) {
-            AICWFDBG(LOGINFO, "load rftest bin fail: %d\n", ret);
+            AICWFDBG(LOGINFO, "load calib bin fail: %d\n", ret);
             return ret;
         }
     } else if (chip_sub_id == 2) {
         ret = rwnx_plat_bin_fw_upload_android(sdiodev, ROM_FMAC_CALIB_ADDR, RWNX_MAC_CALIB_NAME_8800DC_H_U02);
         if (ret) {
-            AICWFDBG(LOGINFO, "load rftest bin fail: %d\n", ret);
+            AICWFDBG(LOGINFO, "load calib bin fail: %d\n", ret);
             return ret;
         }
     }
     return ret;
 }
+#endif
 
+#ifdef CONFIG_DPD
 #ifndef CONFIG_FORCE_DPD_CALIB
 int is_file_exist(char* name)
 {
@@ -1111,6 +1117,11 @@ rf_misc_ram_lite_t dpd_res = {{0},};
 EXPORT_SYMBOL(dpd_res);
 #endif
 
+#ifdef CONFIG_LOFT_CALIB
+rf_misc_ram_lite_t loft_res_local = {{0},};
+EXPORT_SYMBOL(loft_res_local);
+#endif
+
 static int rwnx_plat_patch_load(struct aic_sdio_dev *sdiodev)
 {
 	int ret = 0;
@@ -1168,6 +1179,15 @@ static int rwnx_plat_patch_load(struct aic_sdio_dev *sdiodev)
                 }
                 #endif
                 else
+                #elif defined(CONFIG_LOFT_CALIB)
+                if (1) {
+                    AICWFDBG(LOGINFO, "loft calib\n");
+                    ret = aicwf_loft_calib_8800dc(sdiodev, &loft_res_local);
+                    if (ret) {
+                        AICWFDBG(LOGINFO, "loft calib fail: %d\n", ret);
+                        return ret;
+                    }
+                } else
                 #endif
                 {
                     ret = aicwf_misc_ram_init_8800dc(sdiodev);
@@ -1193,8 +1213,23 @@ static int rwnx_plat_patch_load(struct aic_sdio_dev *sdiodev)
                         return ret;
                     }
                 }
-                #endif
-                #endif
+                #endif/*CONFIG_FORCE_DPD_CALIB*/
+                #elif defined(CONFIG_LOFT_CALIB)
+                {
+                    AICWFDBG(LOGINFO, "patch load\n");
+                    ret = aicwf_plat_patch_load_8800dc(sdiodev);
+                    if (ret) {
+                        AICWFDBG(LOGINFO, "load patch bin fail: %d\n", ret);
+                        return ret;
+                    }
+                    AICWFDBG(LOGINFO, "loft calib\n");
+                    ret = aicwf_loft_calib_8800dc(sdiodev, &loft_res_local);
+                    if (ret) {
+                        AICWFDBG(LOGINFO, "loft calib fail: %d\n", ret);
+                        return ret;
+                    }
+                }
+                #endif/*CONFIG_DPD*/
                 ret = aicwf_plat_rftest_load_8800dc(sdiodev);
                 if (ret) {
                     AICWFDBG(LOGINFO, "load rftest bin fail: %d\n", ret);
@@ -1360,14 +1395,89 @@ err:
 }
 int aicbt_patch_info_unpack(struct aicbt_patch_info_t *patch_info, struct aicbt_patch_table *head_t)
 {
+    uint8_t *patch_info_array = (uint8_t*)patch_info;
+    int base_len = 0;
+    int memcpy_len = 0;
+    
     if (AICBT_PT_INF == head_t->type) {
-        patch_info->info_len = head_t->len;
-        if(patch_info->info_len == 0)
+        base_len = ((offsetof(struct aicbt_patch_info_t,  ext_patch_nb_addr) - offsetof(struct aicbt_patch_info_t,  adid_addrinf) )/sizeof(uint32_t))/2;
+        AICWFDBG(LOGDEBUG, "%s head_t->len:%d base_len:%d \r\n", __func__, head_t->len, base_len);
+
+        if (head_t->len > base_len){
+            patch_info->info_len = base_len;
+            memcpy_len = patch_info->info_len + 1;//include ext patch nb     
+        } else{
+            patch_info->info_len = head_t->len;
+            memcpy_len = patch_info->info_len;
+        }
+	head_t->len = patch_info->info_len;
+        AICWFDBG(LOGDEBUG, "%s memcpy_len:%d \r\n", __func__, memcpy_len);   
+
+        if (patch_info->info_len == 0)
             return 0;
-        memcpy(&patch_info->adid_addrinf, head_t->data, patch_info->info_len * sizeof(uint32_t) * 2);
+       
+        memcpy(((patch_info_array) + sizeof(patch_info->info_len)), 
+            head_t->data, 
+            memcpy_len * sizeof(uint32_t) * 2);
+        AICWFDBG(LOGDEBUG, "%s adid_addrinf:%x addr_adid:%x \r\n", __func__, 
+            ((struct aicbt_patch_info_t *)patch_info_array)->adid_addrinf,
+            ((struct aicbt_patch_info_t *)patch_info_array)->addr_adid);
+
+        if (patch_info->ext_patch_nb > 0){
+            int index = 0;
+            patch_info->ext_patch_param = (uint32_t *)(head_t->data + ((memcpy_len) * 2));
+            
+            for(index = 0; index < patch_info->ext_patch_nb; index++){
+                AICWFDBG(LOGDEBUG, "%s id:%x addr:%x \r\n", __func__, 
+                    *(patch_info->ext_patch_param + (index * 2)),
+                    *(patch_info->ext_patch_param + (index * 2) + 1));
+            }
+        }
+
     }
     return 0;
 }
+
+int aicbt_ext_patch_data_load(struct aic_sdio_dev *sdiodev, struct aicbt_patch_info_t *patch_info)
+{
+    int ret = 0;
+    uint32_t ext_patch_nb = patch_info->ext_patch_nb;
+    char ext_patch_file_name[50];
+    int index = 0;
+    uint32_t id = 0;
+    uint32_t addr = 0;
+
+    
+    if (ext_patch_nb > 0){
+        if (sdiodev->chipid == PRODUCT_ID_AIC8800DC) {
+			AICWFDBG(LOGDEBUG, "[0x40506004]: 0x04318000\n");
+			ret = rwnx_send_dbg_mem_write_req(sdiodev, 0x40506004, 0x04318000);
+			AICWFDBG(LOGDEBUG, "[0x40506004]: 0x04338000\n");
+			ret = rwnx_send_dbg_mem_write_req(sdiodev, 0x40506004, 0x04338000);
+        } else if (sdiodev->chipid == PRODUCT_ID_AIC8800D80X2) {
+			AICWFDBG(LOGDEBUG, "[0x40580000]: 0x00040220\n");
+			ret = rwnx_send_dbg_mem_write_req(sdiodev, 0x40580000, 0x00040220);
+        }
+        for (index = 0; index < patch_info->ext_patch_nb; index++){
+            id = *(patch_info->ext_patch_param + (index * 2));
+            addr = *(patch_info->ext_patch_param + (index * 2) + 1); 
+            memset(ext_patch_file_name, 0, sizeof(ext_patch_file_name));
+            sprintf(ext_patch_file_name,"%s%d.bin",
+                aicbsp_firmware_list[aicbsp_info.cpmode].bt_ext_patch,
+                id);
+            AICWFDBG(LOGDEBUG, "%s ext_patch_file_name:%s ext_patch_id:%x ext_patch_addr:%x \r\n",
+                __func__,ext_patch_file_name, id, addr);
+            
+            if (rwnx_plat_bin_fw_upload_android(sdiodev, addr, ext_patch_file_name)) {
+                ret = -1;
+                break;
+            }
+        }
+    }
+    return ret;
+}
+
+
 int aicbt_patch_trap_data_load(struct aic_sdio_dev *sdiodev, struct aicbt_patch_table *head)
 {
 	struct aicbt_patch_info_t patch_info = {
@@ -1380,6 +1490,8 @@ int aicbt_patch_trap_data_load(struct aic_sdio_dev *sdiodev, struct aicbt_patch_
         .reset_val         = 0,
         .adid_flag_addr    = 0,
         .adid_flag         = 0,
+        .ext_patch_nb_addr = 0,
+        .ext_patch_nb      = 0,
 	};
     if(head == NULL){
         return -1;
@@ -1420,12 +1532,20 @@ int aicbt_patch_trap_data_load(struct aic_sdio_dev *sdiodev, struct aicbt_patch_
             printk("%s, aicbt_patch_info_unpack fail\n", __func__);
             return -1;
         }
+	} else if(sdiodev->chipid == PRODUCT_ID_AIC8800D80X2){
+        aicbt_patch_info_unpack(&patch_info, head);
+        if(patch_info.info_len == 0) {
+            printk("%s, aicbt_patch_info_unpack fail\n", __func__);
+            return -1;
+        }
 	}
 
 	if (rwnx_plat_bin_fw_upload_android(sdiodev, patch_info.addr_adid, aicbsp_firmware_list[aicbsp_info.cpmode].bt_adid))
 		return -1;
 	if (rwnx_plat_bin_fw_upload_android(sdiodev, patch_info.addr_patch, aicbsp_firmware_list[aicbsp_info.cpmode].bt_patch))
 		return -1;
+	if (aicbt_ext_patch_data_load(sdiodev, &patch_info))
+		return -1;
 	return 0;
 
 }
@@ -1462,7 +1582,16 @@ static struct aicbt_info_t aicbt_info[]={
         .uart_flowctrl = AICBT_UART_FC_DEFAULT,
         .lpm_enable    = AICBT_LPM_ENABLE_DEFAULT,
         .txpwr_lvl     = AICBT_TXPWR_LVL_DEFAULT_8800d80,
-    }//PRODUCT_ID_AIC8800D80
+    },//PRODUCT_ID_AIC8800D80
+    {
+        .btmode        = AICBT_BTMODE_DEFAULT_8800d80x2,
+        .btport        = AICBT_BTPORT_DEFAULT,
+        .uart_baud     = AICBT_UART_BAUD_DEFAULT,
+        .uart_flowctrl = AICBT_UART_FC_DEFAULT,
+        .lpm_enable    = AICBT_LPM_ENABLE_DEFAULT,
+        .txpwr_lvl     = AICBT_TXPWR_LVL_DEFAULT_8800d80x2,
+    }//PRODUCT_ID_AIC8800D80x2
+
 };
 
 
@@ -1738,6 +1867,12 @@ int aicwifi_init(struct aic_sdio_dev *sdiodev)
 			printk("download wifi fw fail\n");
 			return -1;
 		}
+		if (testmode == FW_NORMAL_MODE) {
+			if (rwnx_plat_bin_fw_upload_android(sdiodev, RAM_FMAC_FW_PATCH_ADDR, RAM_FMAC_FW_PATCH_NAME)) {
+				printk("download wifi fw patch fail\n");
+				return -1;
+			}
+		}
 
 		if (aicwifi_patch_config(sdiodev)) {
 			printk("aicwifi_patch_config fail\n");
@@ -1792,9 +1927,24 @@ int aicwifi_init(struct aic_sdio_dev *sdiodev)
 			printk("8800d80 wifi start fail\n");
 			return -1;
 		}
+	}else if(sdiodev->chipid == PRODUCT_ID_AIC8800D80X2){
+		if (rwnx_plat_bin_fw_upload_android(sdiodev, RAM_FMAC_FW_ADDR, aicbsp_firmware_list[aicbsp_info.cpmode].wl_fw)) {
+			printk("8800d80x2 download wifi fw fail\n");
+			return -1;
+		}
+
+		if (aicwifi_patch_config_8800d80x2(sdiodev)) {
+			printk("aicwifi_patch_config_8800d80x2 fail\n");
+			return -1;
+		}
+
+		if (aicwifi_start_from_bootrom(sdiodev)) {
+			printk("8800d80x2 wifi start fail\n");
+			return -1;
+		}
 	}
 
-#ifdef CONFIG_GPIO_WAKEUP
+#if (defined(CONFIG_GPIO_WAKEUP) || defined(CONFIG_SDIO_PWRCTRL))
 	if (aicwf_sdio_writeb(sdiodev, sdiodev->sdio_reg.wakeup_reg, 4)) {
 		sdio_err("reg:%d write failed!\n", sdiodev->sdio_reg.wakeup_reg);
 		return -1;
@@ -1920,16 +2070,34 @@ int aicbsp_driver_fw_init(struct aic_sdio_dev *sdiodev)
 		if (rwnx_send_dbg_mem_read_req(sdiodev, mem_addr, &rd_mem_addr_cfm))
 			return -1;
 
-		aicbsp_info.chip_rev = (u8)(rd_mem_addr_cfm.memdata >> 16);
+		aicbsp_info.chip_rev = (u8)((rd_mem_addr_cfm.memdata >> 16) & 0x3F);
+		is_chip_id_h = (u8)(((rd_mem_addr_cfm.memdata >> 16) & 0xC0) == 0xC0);
 		btenable = 1;
-
-		if (aicbsp_info.chip_rev == CHIP_REV_U01)
-            aicbsp_firmware_list = fw_8800d80_u01;
-        if (aicbsp_info.chip_rev == CHIP_REV_U02 || aicbsp_info.chip_rev == CHIP_REV_U03)
-            aicbsp_firmware_list = fw_8800d80_u02;
+		if (is_chip_id_h) {
+			AICWFDBG(LOGINFO, "IS_CHIP_ID_H \n");
+			aicbsp_firmware_list = fw_8800d80_h_u02;
+		} else {
+			if (aicbsp_info.chip_rev == CHIP_REV_U01)
+				aicbsp_firmware_list = fw_8800d80_u01;
+			if (aicbsp_info.chip_rev == CHIP_REV_U02 || aicbsp_info.chip_rev == CHIP_REV_U03)
+				aicbsp_firmware_list = fw_8800d80_u02;
+		}
         if (aicbsp_system_config_8800d80(sdiodev))
             return -1;
 	}
+	else if(sdiodev->chipid == PRODUCT_ID_AIC8800D80X2){
+        btenable = 1;
+		if (rwnx_send_dbg_mem_read_req(sdiodev, mem_addr, &rd_mem_addr_cfm))
+			return -1;
+
+		aicbsp_info.chip_rev = (u8)((rd_mem_addr_cfm.memdata >> 16) & 0x3F);
+			if (aicbsp_info.chip_rev >= (CHIP_REV_U04 + 8))
+				aicbsp_firmware_list = fw_8800d80x2;
+			else{
+					pr_err("aicbsp: %s, unsupport chip rev: %d\n", __func__, aicbsp_info.chip_rev);
+					return -1;
+			}
+	}
 
 	AICWFDBG(LOGINFO, "aicbsp: %s, chip rev: %d\n", __func__, aicbsp_info.chip_rev);
 
@@ -1955,7 +2123,7 @@ int aicbsp_get_feature(struct aicbsp_feature_t *feature, char *fw_path)
         aicbsp_sdiodev->chipid == PRODUCT_ID_AIC8800DC ||
         aicbsp_sdiodev->chipid == PRODUCT_ID_AIC8800DW){
 	    feature->sdio_clock = FEATURE_SDIO_CLOCK;
-	}else if (aicbsp_sdiodev->chipid == PRODUCT_ID_AIC8800D80){
+	}else if (aicbsp_sdiodev->chipid == PRODUCT_ID_AIC8800D80 || aicbsp_sdiodev->chipid == PRODUCT_ID_AIC8800D80X2){
         feature->sdio_clock = FEATURE_SDIO_CLOCK_V3;
 	}
 	feature->sdio_phase = FEATURE_SDIO_PHASE;
@@ -1965,9 +2133,11 @@ int aicbsp_get_feature(struct aicbsp_feature_t *feature, char *fw_path)
 	if(fw_path != NULL){
 		sprintf(fw_path,"%s", AICBSP_FW_PATH);
 	}
+    
     sdio_dbg("%s, set FEATURE_SDIO_CLOCK %d MHz\n", __func__, feature->sdio_clock/1000000);
 	return 0;
 }
+
 EXPORT_SYMBOL_GPL(aicbsp_get_feature);
 
 #ifdef CONFIG_RESV_MEM_SUPPORT

osdrv/extdrv/wireless/aic8800/aic8800_bsp/aic_bsp_driver.h

@@ -16,7 +16,7 @@
 #include <linux/module.h>
 #include "aic_bsp_export.h"
 
-#define RWNX_80211_CMD_TIMEOUT_MS    3000//500//300
+#define RWNX_80211_CMD_TIMEOUT_MS    6000//500//300
 
 #define RWNX_CMD_FLAG_NONBLOCK      BIT(0)
 #define RWNX_CMD_FLAG_REQ_CFM       BIT(1)
@@ -310,7 +310,7 @@ struct dbg_start_app_cfm {
 
 int aicwf_plat_patch_load_8800dc(struct aic_sdio_dev *sdiodev);
 int aicwf_plat_rftest_load_8800dc(struct aic_sdio_dev *sdiodev);
-#ifdef CONFIG_DPD
+#if defined(CONFIG_DPD) || defined(CONFIG_LOFT_CALIB)
 int aicwf_misc_ram_valid_check_8800dc(struct aic_sdio_dev *sdiodev, int *valid_out);
 int aicwf_plat_calib_load_8800dc(struct aic_sdio_dev *sdiodev);
 #endif
@@ -343,6 +343,7 @@ int aicbsp_resv_mem_deinit(void);
 #define AICBSP_FW_PATH_MAX          200
 
 #define RAM_FMAC_FW_ADDR                    0x00120000
+#define RAM_FMAC_FW_PATCH_ADDR              0x00190000
 #define FW_RAM_ADID_BASE_ADDR               0x00161928
 #define FW_RAM_ADID_BASE_ADDR_U03           0x00161928
 #define FW_RAM_PATCH_BASE_ADDR              0x00100000
@@ -369,12 +370,19 @@ int aicbsp_resv_mem_deinit(void);
 #define ROM_FMAC_FW_ADDR               0x00010000
 #define ROM_FMAC_PATCH_ADDR            0x00180000
 
-#define RWNX_MAC_CALIB_BASE_NAME_8800DC        "fmacfw_calib_8800dc"
+#define RAM_FMAC_FW_PATCH_NAME      			"fmacfw_patch.bin"
+#define RWNX_MAC_CALIB_BASE_NAME_8800DC         "fmacfw_calib_8800dc"
 #define RWNX_MAC_CALIB_NAME_8800DC_U02          RWNX_MAC_CALIB_BASE_NAME_8800DC"_u02.bin"
+#ifdef CONFIG_SDIO_BT
+#define RWNX_MAC_CALIB_NAME_8800DC_H_U02        RWNX_MAC_CALIB_BASE_NAME_8800DC"_hbt_u02.bin"
+#else
 #define RWNX_MAC_CALIB_NAME_8800DC_H_U02        RWNX_MAC_CALIB_BASE_NAME_8800DC"_h_u02.bin"
+#endif
 
-#ifdef CONFIG_DPD
+#if defined(CONFIG_DPD) || defined(CONFIG_LOFT_CALIB)
 #define ROM_FMAC_CALIB_ADDR            0x00130000
+#endif
+#ifdef CONFIG_DPD
 #ifndef CONFIG_FORCE_DPD_CALIB
 #define FW_DPDRESULT_NAME_8800DC        "aic_dpdresult_lite_8800dc.bin"
 #endif
@@ -389,13 +397,21 @@ int aicbsp_resv_mem_deinit(void);
 #define RWNX_MAC_PATCH_BASE_NAME_8800DC        "fmacfw_patch_8800dc"
 #define RWNX_MAC_PATCH_NAME2_8800DC RWNX_MAC_PATCH_BASE_NAME_8800DC".bin"
 #define RWNX_MAC_PATCH_NAME2_8800DC_U02 RWNX_MAC_PATCH_BASE_NAME_8800DC"_u02.bin"
+#ifdef CONFIG_SDIO_BT
+#define RWNX_MAC_PATCH_NAME2_8800DC_H_U02 RWNX_MAC_PATCH_BASE_NAME_8800DC"_hbt_u02.bin"
+#else
 #define RWNX_MAC_PATCH_NAME2_8800DC_H_U02 RWNX_MAC_PATCH_BASE_NAME_8800DC"_h_u02.bin"
 #endif
+#endif
 
 #define RWNX_MAC_PATCH_TABLE_NAME_8800DC "fmacfw_patch_tbl_8800dc"
 #define RWNX_MAC_PATCH_TABLE_8800DC RWNX_MAC_PATCH_TABLE_NAME_8800DC ".bin"
 #define RWNX_MAC_PATCH_TABLE_8800DC_U02 RWNX_MAC_PATCH_TABLE_NAME_8800DC "_u02.bin"
+#ifdef CONFIG_SDIO_BT
+#define RWNX_MAC_PATCH_TABLE_8800DC_H_U02 RWNX_MAC_PATCH_TABLE_NAME_8800DC "_hbt_u02.bin"
+#else
 #define RWNX_MAC_PATCH_TABLE_8800DC_H_U02 RWNX_MAC_PATCH_TABLE_NAME_8800DC "_h_u02.bin"
+#endif
 
 #define RWNX_MAC_RF_PATCH_BASE_NAME_8800DC     "fmacfw_rf_patch_8800dc"
 #define RWNX_MAC_RF_PATCH_NAME_8800DC RWNX_MAC_RF_PATCH_BASE_NAME_8800DC".bin"
@@ -485,27 +501,32 @@ enum chip_rev {
 #define AICBT_TXPWR_LVL            0x00006020
 #define AICBT_TXPWR_LVL_8800dc            0x00006f2f
 #define AICBT_TXPWR_LVL_8800d80           0x00006f2f
+#define AICBT_TXPWR_LVL_8800d80x2           0x00006f2f
+
 
 #define AICBSP_HWINFO_DEFAULT       (-1)
 #define AICBSP_CPMODE_DEFAULT       AICBSP_CPMODE_WORK
 #define AICBSP_FWLOG_EN_DEFAULT     0
 
+#define AICBT_BTMODE_DEFAULT_8800d80x2    AICBT_BTMODE_BT_ONLY_COANT
 #define AICBT_BTMODE_DEFAULT_8800d80    AICBT_BTMODE_BT_ONLY_COANT
 #define AICBT_BTMODE_DEFAULT            AICBT_BTMODE_BT_ONLY_SW
+#ifdef CONFIG_SDIO_BT
+#define AICBT_BTPORT_DEFAULT            AICBT_BTPORT_MB
+#else
 #define AICBT_BTPORT_DEFAULT            AICBT_BTPORT_UART
+#endif
 #define AICBT_UART_BAUD_DEFAULT         AICBT_UART_BAUD_1_5M
 #define AICBT_UART_FC_DEFAULT           AICBT_UART_FLOWCTRL_ENABLE
 #define AICBT_LPM_ENABLE_DEFAULT 	    0
 #define AICBT_TXPWR_LVL_DEFAULT         AICBT_TXPWR_LVL
 #define AICBT_TXPWR_LVL_DEFAULT_8800dc  AICBT_TXPWR_LVL_8800dc
 #define AICBT_TXPWR_LVL_DEFAULT_8800d80 AICBT_TXPWR_LVL_8800d80
+#define AICBT_TXPWR_LVL_DEFAULT_8800d80x2 AICBT_TXPWR_LVL_8800d80x2
 
 
-//#define FEATURE_SDIO_CLOCK          50000000 // 0: default, other: target clock rate
-//#define FEATURE_SDIO_CLOCK_V3       150000000 // 0: default, other: target clock rate
-// some noise on sdio line
 #define FEATURE_SDIO_CLOCK          25000000 // 0: default, other: target clock rate
-#define FEATURE_SDIO_CLOCK_V3       25000000 // 0: default, other: target clock rate
+#define FEATURE_SDIO_CLOCK_V3       150000000 // 0: default, other: target clock rate
 #define FEATURE_SDIO_PHASE          2        // 0: default, 2: 180°
 
 struct aicbt_patch_table {
@@ -526,15 +547,21 @@ struct aicbt_info_t {
 };
 
 struct aicbt_patch_info_t {
-       uint32_t info_len;
-       uint32_t adid_addrinf;
-	uint32_t addr_adid;
-       uint32_t patch_addrinf;
-	uint32_t addr_patch;
-	uint32_t reset_addr;
-	uint32_t reset_val;
-	uint32_t adid_flag_addr;
-	uint32_t adid_flag;
+    uint32_t info_len;
+//base len start
+    uint32_t adid_addrinf;
+    uint32_t addr_adid;
+    uint32_t patch_addrinf;
+    uint32_t addr_patch;
+    uint32_t reset_addr;
+    uint32_t reset_val;
+    uint32_t adid_flag_addr;
+    uint32_t adid_flag;
+//base len end
+//ext patch nb
+    uint32_t ext_patch_nb_addr;
+    uint32_t ext_patch_nb;
+    uint32_t *ext_patch_param;
 };
 
 struct aicbsp_firmware {
@@ -543,6 +570,7 @@ struct aicbsp_firmware {
 	const char *bt_patch;
 	const char *bt_table;
 	const char *wl_fw;
+    const char *bt_ext_patch;
 };
 
 struct aicbsp_info_t {
@@ -564,5 +592,7 @@ extern const struct aicbsp_firmware fw_8800dc_u02[];
 extern const struct aicbsp_firmware fw_8800dc_h_u02[];
 extern const struct aicbsp_firmware fw_8800d80_u01[];
 extern const struct aicbsp_firmware fw_8800d80_u02[];
+extern const struct aicbsp_firmware fw_8800d80_h_u02[];
+extern const struct aicbsp_firmware fw_8800d80x2[];
 
 #endif

osdrv/extdrv/wireless/aic8800/aic8800_bsp/aic_bsp_export.h

@@ -31,7 +31,7 @@ struct aicbsp_feature_t {
 	uint8_t  irqf;
 };
 
-#ifdef CONFIG_DPD
+#if defined(CONFIG_DPD) || defined(CONFIG_LOFT_CALIB)
 typedef struct {
     uint32_t bit_mask[3];
     uint32_t reserved;
@@ -53,10 +53,16 @@ typedef struct {
 
 #define MEMBER_SIZE(type, member)   sizeof(((type *)0)->member)
 #define DPD_RESULT_SIZE_8800DC      sizeof(rf_misc_ram_lite_t)
+#endif
 
+#ifdef CONFIG_DPD
 extern rf_misc_ram_lite_t dpd_res;
 #endif
 
+#ifdef CONFIG_LOFT_CALIB
+extern rf_misc_ram_lite_t loft_res_local;
+#endif
+
 int aicbsp_set_subsys(int, int);
 int aicbsp_get_feature(struct aicbsp_feature_t *feature, char *fw_path);
 struct sk_buff *aicbsp_resv_mem_alloc_skb(unsigned int length, uint32_t id);

osdrv/extdrv/wireless/aic8800/aic8800_bsp/aic_bsp_main.c

@@ -15,8 +15,9 @@
 #define DRV_AUTHOR            "AICSemi"
 #define DRV_VERS_MOD          "1.0"
 
-//int aicwf_dbg_level_bsp = LOGERROR|LOGINFO|LOGDEBUG|LOGTRACE;
-int aicwf_dbg_level_bsp = LOGERROR;
+int aicwf_dbg_level_bsp = LOGERROR|LOGINFO|LOGDEBUG|LOGTRACE;
+
+struct semaphore aicbsp_probe_semaphore;
 
 static struct platform_device *aicbsp_pdev;
 
@@ -28,7 +29,11 @@ const struct aicbsp_firmware fw_u02[] = {
 		.bt_adid       = "fw_adid.bin",
 		.bt_patch      = "fw_patch.bin",
 		.bt_table      = "fw_patch_table.bin",
+		#ifdef CONFIG_SDIO_BT
+		.wl_fw         = "fmacfwbt.bin"
+		#else
 		.wl_fw         = "fmacfw.bin"
+		#endif
 	},
 	[AICBSP_CPMODE_TEST] = {
 		.desc          = "rf test mode(sdio u02)",
@@ -47,6 +52,8 @@ const struct aicbsp_firmware fw_u03[] = {
 		.bt_table      = "fw_patch_table_u03.bin",
 		#ifdef CONFIG_MCU_MESSAGE
 		.wl_fw         = "fmacfw_8800m_custmsg.bin"
+		#elif defined(CONFIG_SDIO_BT)
+		.wl_fw         = "fmacfwbt.bin"
 		#else
 		.wl_fw         = "fmacfw.bin"
 		#endif
@@ -86,6 +93,7 @@ const struct aicbsp_firmware fw_8800dc_u02[] = {
 		.bt_adid       = "fw_adid_8800dc_u02.bin",
 		.bt_patch      = "fw_patch_8800dc_u02.bin",
 		.bt_table      = "fw_patch_table_8800dc_u02.bin",
+		.bt_ext_patch  = "fw_patch_8800dc_u02_ext",
 		.wl_fw         = "fmacfw_patch_8800dc_u02.bin"
 	},
 
@@ -94,6 +102,7 @@ const struct aicbsp_firmware fw_8800dc_u02[] = {
 		.bt_adid       = "fw_adid_8800dc_u02.bin",
 		.bt_patch      = "fw_patch_8800dc_u02.bin",
 		.bt_table      = "fw_patch_table_8800dc_u02.bin",
+		.bt_ext_patch  = "fw_patch_8800dc_u02_ext",
 		.wl_fw         = "lmacfw_rf_8800dc.bin" //u01,u02 lmacfw load same bin
 	},
 };
@@ -104,6 +113,7 @@ const struct aicbsp_firmware fw_8800dc_h_u02[] = {
 		.bt_adid       = "fw_adid_8800dc_u02h.bin",
 		.bt_patch      = "fw_patch_8800dc_u02h.bin",
 		.bt_table      = "fw_patch_table_8800dc_u02h.bin",
+		.bt_ext_patch  = "fw_patch_8800dc_u02h_ext",
 		.wl_fw         = "fmacfw_patch_8800dc_h_u02.bin"
 	},
 
@@ -112,6 +122,7 @@ const struct aicbsp_firmware fw_8800dc_h_u02[] = {
 		.bt_adid       = "fw_adid_8800dc_u02h.bin",
 		.bt_patch      = "fw_patch_8800dc_u02h.bin",
 		.bt_table      = "fw_patch_table_8800dc_u02h.bin",
+		.bt_ext_patch  = "fw_patch_8800dc_u02h_ext",
 		.wl_fw         = "lmacfw_rf_8800dc.bin" //u01,u02 lmacfw load same bin
 	},
 };
@@ -141,7 +152,14 @@ const struct aicbsp_firmware fw_8800d80_u02[] = {
 		.bt_adid       = "fw_adid_8800d80_u02.bin",
 		.bt_patch      = "fw_patch_8800d80_u02.bin",
 		.bt_table      = "fw_patch_table_8800d80_u02.bin",
-		.wl_fw         = "fmacfw_8800d80_u02.bin"
+	#if defined CONFIG_SDIO_BT
+		.wl_fw         = "fmacfwbt_8800d80_u02.bin",
+	#elif defined CONFIG_FOR_IPCAM
+		.wl_fw		   = "fmacfw_8800d80_u02_ipc.bin",
+	#else
+		.wl_fw         = "fmacfw_8800d80_u02.bin",
+	#endif
+        .bt_ext_patch  = "fw_patch_8800d80_u02_ext"
 	},
 
 	[AICBSP_CPMODE_TEST] = {
@@ -149,7 +167,58 @@ const struct aicbsp_firmware fw_8800d80_u02[] = {
 		.bt_adid       = "fw_adid_8800d80_u02.bin",
 		.bt_patch      = "fw_patch_8800d80_u02.bin",
 		.bt_table      = "fw_patch_table_8800d80_u02.bin",
-		.wl_fw         = "lmacfw_rf_8800d80_u02.bin"
+		.wl_fw         = "lmacfw_rf_8800d80_u02.bin",
+		.bt_ext_patch  = "fw_patch_8800d80_u02_ext"
+	},
+};
+
+const struct aicbsp_firmware fw_8800d80_h_u02[] = {
+	[AICBSP_CPMODE_WORK] = {
+		.desc          = "normal work mode(8800d80 sdio h_u02)",
+		.bt_adid       = "fw_adid_8800d80_u02.bin",
+		.bt_patch      = "fw_patch_8800d80_u02.bin",
+		.bt_table      = "fw_patch_table_8800d80_u02.bin",
+	#if defined CONFIG_SDIO_BT
+		.wl_fw         = "fmacfwbt_8800d80_h_u02.bin",
+	#elif defined CONFIG_FOR_IPCAM
+		.wl_fw         = "fmacfw_8800d80_h_u02_ipc.bin",
+	#else
+		.wl_fw         = "fmacfw_8800d80_h_u02.bin",
+	#endif
+        .bt_ext_patch  = "fw_patch_8800d80_u02_ext"
+	},
+
+	[AICBSP_CPMODE_TEST] = {
+		.desc          = "rf test mode(8800d80 sdio u02)",
+		.bt_adid       = "fw_adid_8800d80_u02.bin",
+		.bt_patch      = "fw_patch_8800d80_u02.bin",
+		.bt_table      = "fw_patch_table_8800d80_u02.bin",
+		.wl_fw         = "lmacfw_rf_8800d80_u02.bin",
+		.bt_ext_patch  = "fw_patch_8800d80_u02_ext"
+	},
+};
+
+const struct aicbsp_firmware fw_8800d80x2[] = {
+	[AICBSP_CPMODE_WORK] = {
+		.desc          = "normal work mode(8800d80x2 sdio)",
+		.bt_adid       = "fw_adid_8800d80x2_u05.bin",
+		.bt_patch      = "fw_patch_8800d80x2_u05.bin",
+		.bt_table      = "fw_patch_table_8800d80x2_u05.bin",
+	#ifdef CONFIG_SDIO_BT
+		.wl_fw         = "fmacfwbt_8800d80_h_u02.bin",
+	#else
+		.wl_fw         = "fmacfw_8800d80x2.bin",
+	#endif
+        .bt_ext_patch  = "fw_patch_8800d80x2_u05_ext"
+	},
+
+	[AICBSP_CPMODE_TEST] = {
+		.desc          = "rf test mode(8800d80x2 sdio)",
+		.bt_adid       = "fw_adid_8800d80x2_u05.bin",
+		.bt_patch      = "fw_patch_8800d80x2_u05.bin",
+		.bt_table      = "fw_patch_table_8800d80x2_u05.bin",
+		.wl_fw         = "lmacfw_rf_8800d80x2.bin",
+		.bt_ext_patch  = "fw_patch_8800d80x2_u05_ext"
 	},
 };
 
@@ -328,6 +397,9 @@ static int __init aicbsp_init(void)
 	aicbsp_info.cpmode = testmode;
 
 	aicbsp_resv_mem_init();
+    
+    sema_init(&aicbsp_probe_semaphore, 0);
+    
 	ret = platform_driver_register(&aicbsp_driver);
 	if (ret) {
 		pr_err("register platform driver failed: %d\n", ret);
@@ -348,7 +420,7 @@ static int __init aicbsp_init(void)
 	}
 
 	mutex_init(&aicbsp_power_lock);
-#ifdef CONFIG_PLATFORM_ROCKCHIP
+#if defined CONFIG_PLATFORM_ROCKCHIP || defined CONFIG_PLATFORM_ROCKCHIP2
 	aicbsp_set_subsys(AIC_BLUETOOTH, AIC_PWR_ON);
 #endif
 	return 0;
@@ -359,7 +431,7 @@ extern struct aic_sdio_dev *aicbsp_sdiodev;
 
 static void __exit aicbsp_exit(void)
 {
-#ifdef CONFIG_PLATFORM_ROCKCHIP
+#if defined CONFIG_PLATFORM_ROCKCHIP || defined CONFIG_PLATFORM_ROCKCHIP2
     if(aicbsp_sdiodev){
     	aicbsp_sdio_exit();
     }

osdrv/extdrv/wireless/aic8800/aic8800_bsp/aicsdio.c

@@ -48,6 +48,8 @@ static void aicbsp_platform_power_off(void);
 
 struct aic_sdio_dev *aicbsp_sdiodev = NULL;
 static struct semaphore *aicbsp_notify_semaphore;
+extern struct semaphore aicbsp_probe_semaphore;
+
 static const struct sdio_device_id aicbsp_sdmmc_ids[];
 static bool aicbsp_load_fw_in_fdrv = false;
 
@@ -75,10 +77,12 @@ extern int testmode;
 #define SDIO_VENDOR_ID_AIC8801              0x5449
 #define SDIO_VENDOR_ID_AIC8800DC            0xc8a1
 #define SDIO_VENDOR_ID_AIC8800D80           0xc8a1
+#define SDIO_VENDOR_ID_AIC8800D80X2         0xc8a1
 
 #define SDIO_DEVICE_ID_AIC8801				0x0145
 #define SDIO_DEVICE_ID_AIC8800DC			0xc08d
 #define SDIO_DEVICE_ID_AIC8800D80           0x0082
+#define SDIO_DEVICE_ID_AIC8800D80X2         0x2082
 
 
 static int aicbsp_dummy_probe(struct sdio_func *func, const struct sdio_device_id *id)
@@ -242,6 +246,10 @@ static int aicwf_sdio_chipmatch(struct aic_sdio_dev *sdio_dev, uint16_t vid, uin
 		sdio_dev->chipid = PRODUCT_ID_AIC8800D80;
 		AICWFDBG(LOGINFO, "%s USE AIC8800D80\r\n", __func__);
 		return 0;
+	}else if(vid == SDIO_VENDOR_ID_AIC8800D80X2 && did == SDIO_DEVICE_ID_AIC8800D80X2){
+		sdio_dev->chipid = PRODUCT_ID_AIC8800D80X2;
+		AICWFDBG(LOGINFO, "%s USE AIC8800D80X2\r\n", __func__);
+		return 0;
 	}else{
 		return -1;
 	}
@@ -264,6 +272,11 @@ static int aicbsp_sdio_probe(struct sdio_func *func,
 	struct aicwf_bus *bus_if;
 	int err = -ENODEV;
 
+	if (func == NULL) {
+		sdio_err("%s func is null\n", __func__);
+		return err;
+	}
+
 	sdio_dbg("%s:%d vid:0x%04X  did:0x%04X\n", __func__, func->num,
 		func->vendor, func->device);
 
@@ -283,8 +296,11 @@ static int aicbsp_sdio_probe(struct sdio_func *func,
 		return err;
 	}
 
-	func = func->card->sdio_func[1 - 1]; //replace 2 with 1
 	host = func->card->host;
+	host->caps |= MMC_CAP_NONREMOVABLE;
+
+	func = func->card->sdio_func[1 - 1]; //replace 2 with 1
+
 	sdio_dbg("%s after replace:%d\n", __func__, func->num);
 
 	bus_if = kzalloc(sizeof(struct aicwf_bus), GFP_KERNEL);
@@ -317,7 +333,7 @@ static int aicbsp_sdio_probe(struct sdio_func *func,
 	dev_set_drvdata(&func->dev, bus_if);
 	sdiodev->dev = &func->dev;
 
-    if (sdiodev->chipid != PRODUCT_ID_AIC8800D80) {
+    if (sdiodev->chipid != PRODUCT_ID_AIC8800D80 && sdiodev->chipid != PRODUCT_ID_AIC8800D80X2) {
 	    err = aicwf_sdio_func_init(sdiodev);
     } else {
         err = aicwf_sdiov3_func_init(sdiodev);
@@ -331,9 +347,11 @@ static int aicbsp_sdio_probe(struct sdio_func *func,
 		sdio_err("sdio bus init err\r\n");
 		goto fail;
 	}
-	host->caps |= MMC_CAP_NONREMOVABLE;
+
 	aicbsp_platform_init(sdiodev);
 
+	up(&aicbsp_probe_semaphore);
+
 	return 0;
 fail:
 	aicwf_sdio_func_deinit(sdiodev);
@@ -343,33 +361,37 @@ fail:
 	return err;
 }
 
+
 static void aicbsp_sdio_remove(struct sdio_func *func)
 {
 	struct mmc_host *host;
 	struct aicwf_bus *bus_if = NULL;
 	struct aic_sdio_dev *sdiodev = NULL;
 
-	sdio_dbg("%s\n", __func__);
+	AICWFDBG(LOGINFO, "%s\n", __func__);
 	if (aicbsp_sdiodev == NULL) {
-		sdio_dbg("%s: allready unregister\n", __func__);
-		return;
+		AICWFDBG(LOGERROR, "%s: allready unregister\n", __func__);
+		goto done;
+	}
+	if (func == NULL) {
+		AICWFDBG(LOGERROR, "%s, sdio func is null\n", __func__);
+		goto done;
 	}
 
-    bus_if = aicbsp_get_drvdata(&func->dev);
-
-	if (!bus_if) {
-        AICWFDBG(LOGERROR, "%s bus_if is NULL \r\n", __func__);
-		return;
-	}
-
-	func = aicbsp_sdiodev->func;
 	host = func->card->host;
 	host->caps &= ~MMC_CAP_NONREMOVABLE;
 
+	bus_if = aicbsp_get_drvdata(&func->dev);
+
+	if (!bus_if) {
+		AICWFDBG(LOGERROR, "%s bus_if is NULL \r\n", __func__);
+		goto done;
+	}
+
 	sdiodev = bus_if->bus_priv.sdio;
 	if (!sdiodev) {
-        AICWFDBG(LOGERROR, "%s sdiodev is NULL \r\n", __func__);
-		return;
+		AICWFDBG(LOGERROR, "%s sdiodev is NULL \r\n", __func__);
+		goto done;
 	}
 
 	aicwf_sdio_release(sdiodev);
@@ -377,29 +399,26 @@ static void aicbsp_sdio_remove(struct sdio_func *func)
 
 	dev_set_drvdata(&sdiodev->func->dev, NULL);
 	kfree(sdiodev);
-	kfree(bus_if);
+
+done:
+	if (bus_if)
+		kfree(bus_if);
 	aicbsp_sdiodev = NULL;
 	sdio_dbg("%s done\n", __func__);
 }
 
+
 static int aicbsp_sdio_suspend(struct device *dev)
 {
 	struct sdio_func *func = dev_to_sdio_func(dev);
 	int err;
 	mmc_pm_flag_t sdio_flags;
 
-#ifdef CONFIG_PLATFORM_ROCKCHIP
+#if defined(CONFIG_PLATFORM_ROCKCHIP) || defined(CONFIG_PLATFORM_ROCKCHIP2)
 #ifdef CONFIG_GPIO_WAKEUP
     //BT_SLEEP:true,BT_WAKEUP:false
     rfkill_rk_sleep_bt(false);
 #endif
-#endif
-
-#ifdef CONFIG_PLATFORM_ROCKCHIP2
-#ifdef CONFIG_GPIO_WAKEUP
-        //BT_SLEEP:true,BT_WAKEUP:false
-        rfkill_rk_sleep_bt(false);
-#endif
 #endif
 
 	sdio_dbg("%s, func->num = %d\n", __func__, func->num);
@@ -419,7 +438,7 @@ static int aicbsp_sdio_suspend(struct device *dev)
 		return err;
 	}
 
-#ifdef CONFIG_PLATFORM_ROCKCHIP
+#if defined(CONFIG_PLATFORM_ROCKCHIP) || defined(CONFIG_PLATFORM_ROCKCHIP2)
 #ifdef CONFIG_GPIO_WAKEUP
 		//BT_SLEEP:true,BT_WAKEUP:false
 		rfkill_rk_sleep_bt(true);
@@ -427,15 +446,6 @@ static int aicbsp_sdio_suspend(struct device *dev)
 #endif
 #endif
 
-#ifdef CONFIG_PLATFORM_ROCKCHIP2
-#ifdef CONFIG_GPIO_WAKEUP
-            //BT_SLEEP:true,BT_WAKEUP:false
-            rfkill_rk_sleep_bt(true);
-            printk("%s BT wake to SLEEP\r\n", __func__);
-#endif
-#endif
-
-
 	return 0;
 }
 
@@ -443,6 +453,13 @@ static int aicbsp_sdio_resume(struct device *dev)
 {
 	sdio_dbg("%s\n", __func__);
 
+#if defined(CONFIG_PLATFORM_ROCKCHIP) || defined(CONFIG_PLATFORM_ROCKCHIP2)
+#ifdef CONFIG_GPIO_WAKEUP
+		//BT_SLEEP:true,BT_WAKEUP:false
+		rfkill_rk_sleep_bt(false);
+#endif
+#endif
+
 	return 0;
 }
 
@@ -570,11 +587,18 @@ static void aicbsp_platform_power_off(void)
 
 int aicbsp_sdio_init(void)
 {
+
 	if (sdio_register_driver(&aicbsp_sdio_driver)) {
 		return -1;
 	} else {
 		//may add mmc_rescan here
 	}
+	if (down_timeout(&aicbsp_probe_semaphore, msecs_to_jiffies(2000)) != 0){
+		printk("%s aicbsp_sdio_probe fail\r\n", __func__);
+		return -1;
+	}
+
+	
 	return 0;
 }
 
@@ -733,7 +757,7 @@ int aicwf_sdio_wakeup(struct aic_sdio_dev *sdiodev)
         sdiodev->chipid == PRODUCT_ID_AIC8800DC ||
         sdiodev->chipid == PRODUCT_ID_AIC8800DW) {
         wakeup_reg_val = 1;
-    } else if (sdiodev->chipid == PRODUCT_ID_AIC8800D80) {
+    } else if (sdiodev->chipid == PRODUCT_ID_AIC8800D80 || sdiodev->chipid == PRODUCT_ID_AIC8800D80X2) {
         wakeup_reg_val = 0x11;
     }
 
@@ -953,7 +977,8 @@ static int aicwf_sdio_tx_msg(struct aic_sdio_dev *sdiodev)
 	} else
 		len = payload_len;
 
-	if(sdiodev->chipid == PRODUCT_ID_AIC8801 || sdiodev->chipid == PRODUCT_ID_AIC8800D80){
+	if(sdiodev->chipid == PRODUCT_ID_AIC8801 || sdiodev->chipid == PRODUCT_ID_AIC8800D80 || 
+		sdiodev->chipid == PRODUCT_ID_AIC8800D80X2){
 		buffer_cnt = aicwf_sdio_flow_ctrl(sdiodev);
 		while ((buffer_cnt <= 0 || (buffer_cnt > 0 && len > (buffer_cnt * BUFFER_SIZE))) && retry < 10) {
 			retry++;
@@ -963,7 +988,8 @@ static int aicwf_sdio_tx_msg(struct aic_sdio_dev *sdiodev)
 	}
 	down(&sdiodev->tx_priv->cmd_txsema);
 
-	if(sdiodev->chipid == PRODUCT_ID_AIC8801 || sdiodev->chipid == PRODUCT_ID_AIC8800D80){
+	if(sdiodev->chipid == PRODUCT_ID_AIC8801 || sdiodev->chipid == PRODUCT_ID_AIC8800D80 ||
+		sdiodev->chipid == PRODUCT_ID_AIC8800D80X2){
 		if (buffer_cnt > 0 && len < (buffer_cnt * BUFFER_SIZE)) {
 			err = aicwf_sdio_send_pkt(sdiodev, payload, len);
 			if (err) {
@@ -1197,7 +1223,7 @@ int aicwf_sdio_aggr(struct aicwf_tx_priv *tx_priv, struct sk_buff *pkt)
 	if (tx_priv->sdiodev->chipid == PRODUCT_ID_AIC8801 || tx_priv->sdiodev->chipid == PRODUCT_ID_AIC8800DC ||
         tx_priv->sdiodev->chipid == PRODUCT_ID_AIC8800DW)
         sdio_header[3] = 0; //reserved
-    else if (tx_priv->sdiodev->chipid == PRODUCT_ID_AIC8800D80)
+    else if (tx_priv->sdiodev->chipid == PRODUCT_ID_AIC8800D80  || tx_priv->sdiodev->chipid == PRODUCT_ID_AIC8800D80X2)
 	    sdio_header[3] = crc8_ponl_107(&sdio_header[0], 3); // crc8
 
 	memcpy(tx_priv->tail, (u8 *)&sdio_header, sizeof(sdio_header));
@@ -1304,7 +1330,7 @@ static int aicwf_sdio_bus_start(struct device *dev)
 
 		if (ret != 0)
 			sdio_err("func2 intr register failed:%d\n", ret);
-	}else if(sdiodev->chipid == PRODUCT_ID_AIC8800D80){
+	}else if(sdiodev->chipid == PRODUCT_ID_AIC8800D80 || sdiodev->chipid == PRODUCT_ID_AIC8800D80X2){
 		sdio_claim_host(sdiodev->func);
 		sdio_claim_irq(sdiodev->func, aicwf_sdio_hal_irqhandler);
 
@@ -1445,7 +1471,7 @@ void aicwf_sdio_hal_irqhandler(struct sdio_func *func)
 
     	    ret = aicwf_sdio_readb(sdiodev, sdiodev->sdio_reg.block_cnt_reg, &intstatus);
     	}
-    }else if (sdiodev->chipid  == PRODUCT_ID_AIC8800D80) {
+    }else if (sdiodev->chipid  == PRODUCT_ID_AIC8800D80 || sdiodev->chipid  == PRODUCT_ID_AIC8800D80X2) {
         do {
             ret = aicwf_sdio_readb(sdiodev, sdiodev->sdio_reg.misc_int_status_reg, &intstatus);
             if (!ret) {
@@ -1600,22 +1626,33 @@ void aicwf_sdio_release_func2(struct aic_sdio_dev *sdiodev)
 
 void aicwf_sdio_release(struct aic_sdio_dev *sdiodev)
 {
-	struct aicwf_bus *bus_if;
+	struct aicwf_bus *bus_if = NULL;
+	struct aicwf_bus *bus_if_t = NULL;
 	int ret = 0;
 
 	sdio_dbg("%s\n", __func__);
+	if (sdiodev->func == NULL) {
+		printk("%s, NULL sdio func\n", __func__);
+		return;
+	}
 
 	bus_if = aicbsp_get_drvdata(sdiodev->dev);
-	bus_if->state = BUS_DOWN_ST;
+	if (bus_if)
+		bus_if->state = BUS_DOWN_ST;
 
-	sdio_claim_host(sdiodev->func);
-	//disable sdio interrupt
-	ret = aicwf_sdio_writeb(sdiodev, sdiodev->sdio_reg.intr_config_reg, 0x0);
-	if (ret < 0) {
-		sdio_err("reg:%d write failed!, ret=%d\n", sdiodev->sdio_reg.intr_config_reg, ret);
+	bus_if_t = dev_get_drvdata(sdiodev->dev);
+
+	if ((bus_if_t != NULL) && (sdiodev->bus_if == bus_if_t)) {
+		sdio_dbg("%s bsp release\n", __func__);
+		sdio_claim_host(sdiodev->func);
+		//disable sdio interrupt
+		ret = aicwf_sdio_writeb(sdiodev, sdiodev->sdio_reg.intr_config_reg, 0x0);
+		if (ret < 0) {
+			sdio_err("reg:%d write failed!, ret=%d\n", sdiodev->sdio_reg.intr_config_reg, ret);
+		}
+		sdio_release_irq(sdiodev->func);
+		sdio_release_host(sdiodev->func);
 	}
-	sdio_release_irq(sdiodev->func);
-	sdio_release_host(sdiodev->func);
 
 	if(sdiodev->chipid == PRODUCT_ID_AIC8800DC || sdiodev->chipid == PRODUCT_ID_AIC8800DW){
 		aicwf_sdio_release_func2(sdiodev);
@@ -1633,6 +1670,8 @@ void aicwf_sdio_release(struct aic_sdio_dev *sdiodev)
 	rwnx_cmd_mgr_deinit(&sdiodev->cmd_mgr);
 }
 
+
+
 void aicwf_sdio_reg_init(struct aic_sdio_dev *sdiodev)
 {
     sdio_dbg("%s\n", __func__);
@@ -1649,7 +1688,7 @@ void aicwf_sdio_reg_init(struct aic_sdio_dev *sdiodev)
         sdiodev->sdio_reg.block_cnt_reg =          SDIOWIFI_BLOCK_CNT_REG;
         sdiodev->sdio_reg.rd_fifo_addr =           SDIOWIFI_RD_FIFO_ADDR;
         sdiodev->sdio_reg.wr_fifo_addr =           SDIOWIFI_WR_FIFO_ADDR;
-	} else if (sdiodev->chipid == PRODUCT_ID_AIC8800D80){
+	} else if (sdiodev->chipid == PRODUCT_ID_AIC8800D80 || sdiodev->chipid == PRODUCT_ID_AIC8800D80X2){
         sdiodev->sdio_reg.bytemode_len_reg =       SDIOWIFI_BYTEMODE_LEN_REG_V3;
         sdiodev->sdio_reg.intr_config_reg =        SDIOWIFI_INTR_ENABLE_REG_V3;
         sdiodev->sdio_reg.sleep_reg =              SDIOWIFI_INTR_PENDING_REG_V3;
@@ -1841,16 +1880,35 @@ int aicwf_sdiov3_func_init(struct aic_sdio_dev *sdiodev)
 
 void aicwf_sdio_func_deinit(struct aic_sdio_dev *sdiodev)
 {
-	sdio_claim_host(sdiodev->func);
-	sdio_disable_func(sdiodev->func);
-	sdio_release_host(sdiodev->func);
+	struct aicwf_bus *bus_if = NULL;
+
+	if (sdiodev->func == NULL) {
+		sdio_err("%s, NULL sdio func\n", __func__);
+		return;
+	}
+
+	bus_if = dev_get_drvdata(sdiodev->dev);
+	if (bus_if == NULL) {
+		sdio_err("%s, bus_if is null\n", __func__);
+		return;
+	}
+
+	if (sdiodev->bus_if == bus_if) {
+		sdio_dbg("%s bsp disable\n", __func__);
+		sdio_claim_host(sdiodev->func);
+		sdio_disable_func(sdiodev->func);
+		sdio_release_host(sdiodev->func);
+	}
+
 	if(sdiodev->chipid == PRODUCT_ID_AIC8800DC || sdiodev->chipid == PRODUCT_ID_AIC8800DW){
 		sdio_claim_host(sdiodev->func_msg);
 		sdio_disable_func(sdiodev->func_msg);
 		sdio_release_host(sdiodev->func_msg);
 	}
+
 }
 
+
 void *aicwf_sdio_bus_init(struct aic_sdio_dev *sdiodev)
 {
 	int ret;
@@ -1943,6 +2001,11 @@ void set_irq_handler(void *fn){
     aicbsp_sdiodev->sdio_hal_irqhandler = (sdio_irq_handler_t *)fn;
 }
 
+extern int adap_test;
+int get_adap_test(void){
+    return adap_test;
+}
+
 uint8_t crc8_ponl_107(uint8_t *p_buffer, uint16_t cal_size)
 {
     uint8_t i;
@@ -1971,4 +2034,5 @@ EXPORT_SYMBOL(get_fw_path);
 EXPORT_SYMBOL(get_testmode);
 EXPORT_SYMBOL(get_sdio_func);
 EXPORT_SYMBOL(set_irq_handler);
+EXPORT_SYMBOL(get_adap_test);
 

osdrv/extdrv/wireless/aic8800/aic8800_bsp/aicsdio.h

@@ -69,7 +69,8 @@ enum AICWF_IC{
 	PRODUCT_ID_AIC8801	=	0,
 	PRODUCT_ID_AIC8800DC,
 	PRODUCT_ID_AIC8800DW,
-	PRODUCT_ID_AIC8800D80
+	PRODUCT_ID_AIC8800D80,
+	PRODUCT_ID_AIC8800D80X2
 };
 
 struct aic_sdio_reg {
@@ -108,6 +109,7 @@ struct aic_sdio_dev {
 	struct semaphore pwrctl_wakeup_sema;
 #endif
 	u16 chipid;
+	u32 fw_version_uint;
     struct aic_sdio_reg sdio_reg;
     void (*sdio_hal_irqhandler) (struct sdio_func *func);
 };

osdrv/extdrv/wireless/aic8800/aic8800_bsp/aicsdio_txrxif.c

@@ -41,21 +41,22 @@ int aicwf_bus_init(uint bus_hdrlen, struct device *dev)
 	init_completion(&bus_if->busrx_trgg);
 #ifdef AICWF_SDIO_SUPPORT
 	bus_if->bustx_thread = kthread_run(aicwf_sdio_bustx_thread, (void *)bus_if, "aicwf_bustx_thread");
-	bus_if->busrx_thread = kthread_run(aicwf_sdio_busrx_thread, (void *)bus_if->bus_priv.sdio->rx_priv, "aicwf_busrx_thread");
-#endif
-
 	if (IS_ERR(bus_if->bustx_thread)) {
 		bus_if->bustx_thread  = NULL;
 		txrx_err("aicwf_bustx_thread run fail\n");
+		ret = -1;
 		goto fail;
 	}
 
+	bus_if->busrx_thread = kthread_run(aicwf_sdio_busrx_thread, (void *)bus_if->bus_priv.sdio->rx_priv, "aicwf_busrx_thread");
 	if (IS_ERR(bus_if->busrx_thread)) {
 		bus_if->busrx_thread  = NULL;
 		txrx_err("aicwf_bustx_thread run fail\n");
+		ret = -1;
 		goto fail;
 	}
 
+#endif
 	return ret;
 fail:
 	aicwf_bus_deinit(dev);

osdrv/extdrv/wireless/aic8800/aic8800_bsp/rwnx_version_gen.h

@@ -1,4 +1,4 @@
 #define RWNX_VERS_REV "241c091M (master)"
 #define RWNX_VERS_MOD "6.4.3.0"
 #define RWNX_VERS_BANNER "rwnx v6.4.3.0 - - 241c091M (master)"
-#define RELEASE_DATE "2024_0109_ec460377"
+#define RELEASE_DATE "2025_0926_91c9dae5"

osdrv/extdrv/wireless/aic8800/aic8800_btlpm/Makefile

@@ -12,38 +12,23 @@ CONFIG_PLATFORM_AMLOGIC ?= n
 CONFIG_PLATFORM_UBUNTU ?= y
 
 
-CONFIG_SUPPORT_LPM = y
+CONFIG_SUPPORT_LPM ?= y
 CONFIG_AUTO_PM ?= n
 
 aic8800_btlpm-y := \
 	aic_bluetooth_main.o \
 	rfkill.o \
 
-ifeq ($(CONFIG_PLATFORM_UBUNTU), n)
-	aic8800_btlpm-$(CONFIG_SUPPORT_LPM) += lpm.o
-endif
+aic8800_btlpm-$(CONFIG_SUPPORT_LPM) += lpm.o
 
 ccflags-y += -DAIC_TRACE_INCLUDE_PATH=$(src)
 
 ccflags-$(CONFIG_AUTO_PM) += -DCONFIG_AUTO_PM
 
 ifeq ($(CONFIG_PLATFORM_ROCKCHIP), y)
-KDIR  ?= /home/yaya/E/Rockchip/3229/Android9/rk3229_android9.0_box/kernel
-ARCH ?= arm
-CROSS_COMPILE ?= /home/yaya/E/Rockchip/3229/Android9/rk3229_android9.0_box/prebuilts/gcc/linux-x86/arm/gcc-linaro-6.3.1-2017.05-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-
-#KDIR  ?= /home/yaya/E/Rockchip/3229/Android10/SDK/kernel/
-#ARCH ?= arm
-#CROSS_COMPILE ?= /home/yaya/E/Rockchip/3229/Android10/SDK/prebuilts/gcc/linux-x86/arm/gcc-linaro-6.3.1-2017.05-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-
-#KDIR  ?= /home/yaya/E/Rockchip/3288/Android10/kernel/kernel/
-#ARCH ?= arm
-#CROSS_COMPILE ?= /home/yaya/E/Rockchip/3288/Android10/tool/gcc-linaro-6.3.1-2017.05-x86_64_arm-linux-gnueabihf/bin/arm-linux#-gnueabihf-
-#KDIR ?= /home/yaya/E/Rockchip/3229/Android7/RK3229_ANDROID7.1_v1.01_20170914/rk3229_Android7.1_v1.01_xml0914/kernel
-#ARCH ?= arm
-#CROSS_COMPILE ?= /home/yaya/E/Rockchip/3229/Android7/RK3229_ANDROID7.1_v1.01_20170914/rk3229_Android7.1_v1.01_xml0914/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
-#KDIR ?= /home/yaya/E/Rockchip/3328/Android9/SDK/SDK/kernel
-#ARCH ?= arm64
-#CROSS_COMPILE ?= /home/yaya/E/Rockchip/3328/Android9/SDK/SDK/prebuilts/gcc/linux-x86/aarch64/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
-
+ARCH = arm64
+KDIR = /home/yaya/E/Rockchip/3566/firefly/Android11.0/Firefly-RK356X_Android11.0_git_20210824/RK356X_Android11.0/kernel
+CROSS_COMPILE = /home/yaya/E/Rockchip/3566/firefly/Android11.0/Firefly-RK356X_Android11.0_git_20210824/RK356X_Android11.0/prebuilts/gcc/linux-x86/aarch64/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
 ccflags-$(CONFIG_PLATFORM_ROCKCHIP) += -DCONFIG_PLATFORM_ROCKCHIP
 ccflags-y += -DANDROID_PLATFORM
 endif

osdrv/extdrv/wireless/aic8800/aic8800_fdrv/Makefile

@@ -72,38 +72,72 @@ CONFIG_ARP_OFFLOAD =y
 CONFIG_RADAR_OR_IR_DETECT =n
 CONFIG_DOWNLOAD_FW =n
 CONFIG_RFTEST=y
-CONFIG_USB_BT =y
+CONFIG_USB_BT =n
+CONFIG_SDIO_BT=y
 CONFIG_USE_5G ?= y
-CONFIG_SDIO_PWRCTRL ?= y
 CONFIG_CREATE_TRACE_POINTS = n
 CONFIG_TXRX_THREAD_PRIO = y
 # CONFIG_COEX = n for BT_ONLY, CONFIG_COEX =y for combo and sw
 CONFIG_COEX = y
 CONFIG_RX_NETIF_RECV_SKB = y
-CONFIG_GPIO_WAKEUP = n
 CONFIG_SET_VENDOR_EXTENSION_IE = n
 CONFIG_SUPPORT_REALTIME_CHANGE_MAC = y
 CONFIG_WPA3_FOR_OLD_KERNEL ?= n
 CONFIG_VHT_FOR_OLD_KERNEL ?= n
 CONFIG_HE_FOR_OLD_KERNEL ?= n
-CONFIG_PREALLOC_RX_SKB = n
+CONFIG_PREALLOC_RX_SKB ?= n
 CONFIG_WIFI_SUSPEND_FOR_LINUX = n
 # Need to set fw path in BOARD_KERNEL_CMDLINE
-CONFIG_USE_FW_REQUEST = n
+CONFIG_USE_FW_REQUEST ?= n
 CONFIG_USE_P2P0=n
+CONFIG_TX_NETIF_FLOWCTRL = n
+CONFIG_ONE_TXQ = n
 CONFIG_BR_SUPPORT =n
 BR_NAME = br0
 CONFIG_FDRV_NO_REG_SDIO=n
 CONFIG_SCHED_SCAN = n
-CONFIG_OOB = n
+CONFIG_OOB ?= n
 CONFIG_USE_CUSTOMER_MAC = n
-CONFIG_PREALLOC_TXQ = y
+CONFIG_PREALLOC_TXQ ?= y
 CONFIG_DPD = y
 CONFIG_FORCE_DPD_CALIB = y
-CONFIG_FILTER_TCP_ACK =n
-CONFIG_RESV_MEM_SUPPORT = y
+CONFIG_LOFT_CALIB = n
+CONFIG_FILTER_TCP_ACK =y
+CONFIG_RESV_MEM_SUPPORT ?= y
 CONFIG_GKI = n
 CONFIG_TEMP_COMP = n
+CONFIG_TEMP_CONTROL = n
+CONFIG_EXT_FEM_8800DCDW = n
+CONFIG_SHUTDOWN_CALLBACK = y
+CONFIG_FOR_IPCAM = n
+CONFIG_SDIO_ADMA = n
+# CONFIG_MCC = n for sta and p2p concurrent in same channel.
+CONFIG_MCC = y
+CONFIG_APF = n
+CONFIG_POWER_LIMIT = n
+CONFIG_BAND_STEERING = n
+CONFIG_PRBREQ_REPORT = n
+
+#CONFIG FOR LOW POWER MODE
+CONFIG_SDIO_PWRCTRL ?= n
+CONFIG_GPIO_WAKEUP ?= n
+CONFIG_AUTO_POWERSAVE = n
+
+# Enable wifi-hal Latency Mode
+CONFIG_AICWF_LATENCY_MODE = n
+
+#support D80X2 can write rf result to file
+CONFIG_WRITE_FILE_D80X2 = n
+
+ifneq ($(CONFIG_WIRELESS_EXT), y)
+CONFIG_USE_WIRELESS_EXT = n
+endif
+
+ifeq ($(CONFIG_EXT_FEM_8800DCDW), y)
+CONFIG_DPD = n
+CONFIG_FORCE_DPD_CALIB = n
+CONFIG_LOFT_CALIB = y
+endif
 
 # Support of MU-MIMO transmission (need FW support)
 ifeq ($(CONFIG_RWNX_BFMER), y)
@@ -119,7 +153,10 @@ CONFIG_RWNX_RADAR ?= y
 CONFIG_RWNX_BCMC ?= y
 
 # Enable Monitor+Data interface support (need FW support)
-CONFIG_RWNX_MON_DATA =y
+CONFIG_RWNX_MON_DATA = n
+CONFIG_RWNX_MON_XMIT = n
+CONFIG_RWNX_MON_RXFILTER = n
+
 
 # extra DEBUG config
 CONFIG_RWNX_SW_PROFILING ?= n
@@ -153,8 +190,11 @@ $(MODULE_NAME)-y := \
 	aicwf_compat_8800d80.o \
 	rwnx_wakelock.o		\
 	regdb.o				   \
+	aic_priv_cmd.o		\
 	aicwf_rx_prealloc.o
 
+$(MODULE_NAME)-$(CONFIG_BAND_STEERING)    += aicwf_manager.o    \
+	aicwf_steering.o
 $(MODULE_NAME)-$(CONFIG_BR_SUPPORT)       += aic_br_ext.o
 $(MODULE_NAME)-$(CONFIG_RWNX_RADAR)       += rwnx_radar.o
 $(MODULE_NAME)-$(CONFIG_DEBUG_FS)         += rwnx_debugfs.o
@@ -166,6 +206,8 @@ $(MODULE_NAME)-$(CONFIG_SDIO_SUPPORT)     += sdio_host.o
 $(MODULE_NAME)-$(CONFIG_SDIO_SUPPORT)     += aicwf_txrxif.o
 $(MODULE_NAME)-$(CONFIG_SDIO_SUPPORT)     += aicwf_sdio.o
 $(MODULE_NAME)-$(CONFIG_FILTER_TCP_ACK)   += aicwf_tcp_ack.o
+$(MODULE_NAME)-$(CONFIG_SDIO_BT)   += aic_btsdio.o
+$(MODULE_NAME)-$(CONFIG_SDIO_BT)   += btsdio.o
 
 $(MODULE_NAME)-$(CONFIG_USB_SUPPORT)     += usb_host.o
 $(MODULE_NAME)-$(CONFIG_USB_SUPPORT)     += aicwf_txrxif.o
@@ -216,6 +258,9 @@ ccflags-y += -I$(srctree)/$(src)/../aic8800_bsp
 ccflags-y += -DCONFIG_AIC_FW_PATH=\"$(CONFIG_AIC_FW_PATH)\"
 ccflags-$(CONFIG_RWNX_RADAR) += -DCONFIG_RWNX_RADAR
 ccflags-$(CONFIG_RWNX_MON_DATA) += -DCONFIG_RWNX_MON_DATA
+ccflags-$(CONFIG_RWNX_MON_XMIT) += -DCONFIG_RWNX_MON_XMIT
+ccflags-$(CONFIG_RWNX_MON_RXFILTER) += -DCONFIG_RWNX_MON_RXFILTER
+
 ccflags-$(CONFIG_RWNX_BFMER) += -DCONFIG_RWNX_BFMER
 ccflags-$(CONFIG_RWNX_SPLIT_TX_BUF) += -DCONFIG_RWNX_SPLIT_TX_BUF
 ifeq ($(CONFIG_RWNX_SPLIT_TX_BUF), y)
@@ -241,15 +286,27 @@ ccflags-$(CONFIG_USE_P2P0) += -DCONFIG_USE_P2P0
 ccflags-$(CONFIG_FDRV_NO_REG_SDIO) += -DCONFIG_FDRV_NO_REG_SDIO
 ccflags-$(CONFIG_SCHED_SCAN) += -DCONFIG_SCHED_SCAN
 ccflags-$(CONFIG_OOB) += -DCONFIG_OOB
+ccflags-$(CONFIG_AICWF_LATENCY_MODE) += -DAICWF_LATENCY_MODE
 ccflags-$(CONFIG_USE_CUSTOMER_MAC) += -DCONFIG_USE_CUSTOMER_MAC
 ccflags-$(CONFIG_PREALLOC_TXQ) += -DCONFIG_PREALLOC_TXQ
 ccflags-$(CONFIG_DPD) += -DCONFIG_DPD
 ccflags-$(CONFIG_FORCE_DPD_CALIB) += -DCONFIG_FORCE_DPD_CALIB -DCONFIG_DPD
+ccflags-$(CONFIG_LOFT_CALIB) += -DCONFIG_LOFT_CALIB
 ccflags-$(CONFIG_FILTER_TCP_ACK) += -DCONFIG_FILTER_TCP_ACK
+ccflags-$(CONFIG_SDIO_BT) += -DCONFIG_SDIO_BT
 ccflags-$(CONFIG_RESV_MEM_SUPPORT) += -DCONFIG_RESV_MEM_SUPPORT
 ccflags-$(CONFIG_GKI) += -DCONFIG_GKI
 ccflags-$(CONFIG_TEMP_COMP) += -DCONFIG_TEMP_COMP
-
+ccflags-$(CONFIG_TEMP_CONTROL) += -DCONFIG_TEMP_CONTROL
+ccflags-$(CONFIG_POWER_LIMIT) += -DCONFIG_POWER_LIMIT
+ccflags-$(CONFIG_EXT_FEM_8800DCDW) += -DCONFIG_EXT_FEM_8800DCDW
+ccflags-$(CONFIG_MCC) += -DCONFIG_MCC
+ccflags-$(CONFIG_SHUTDOWN_CALLBACK) += -DCONFIG_SHUTDOWN_CALLBACK
+ccflags-$(CONFIG_FOR_IPCAM) += -DCONFIG_FOR_IPCAM
+ccflags-$(CONFIG_SDIO_ADMA) += -DCONFIG_SDIO_ADMA
+ccflags-$(CONFIG_BAND_STEERING) += -DCONFIG_BAND_STEERING
+ccflags-$(CONFIG_PRBREQ_REPORT) += -DCONFIG_PRBREQ_REPORT
+ccflags-$(CONFIG_WRITE_FILE_D80X2) += -DRF_WRITE_FILE
 
 ifeq ($(CONFIG_SDIO_SUPPORT), y)
 ccflags-y += -DAICWF_SDIO_SUPPORT
@@ -284,11 +341,18 @@ endif
 
 ccflags-$(CONFIG_RX_REORDER) += -DAICWF_RX_REORDER
 ccflags-$(CONFIG_ARP_OFFLOAD) += -DAICWF_ARP_OFFLOAD
-ccflags-$(CONFIG_RADAR_DETECT) += -DRADAR_OR_IR_DETECT
+ccflags-$(CONFIG_RADAR_OR_IR_DETECT) += -DCONFIG_RADAR_OR_IR_DETECT
 ccflags-$(CONFIG_DOWNLOAD_FW)  += -DCONFIG_DOWNLOAD_FW
 ccflags-$(CONFIG_RX_NETIF_RECV_SKB) += -DCONFIG_RX_NETIF_RECV_SKB
+ccflags-$(CONFIG_ONE_TXQ)  += -DCONFIG_ONE_TXQ
+ccflags-$(CONFIG_TX_NETIF_FLOWCTRL) += -DCONFIG_TX_NETIF_FLOWCTRL
+ccflags-$(CONFIG_APF) += -DCONFIG_APF
+ccflags-$(CONFIG_AUTO_POWERSAVE) += -DCONFIG_AUTO_POWERSAVE
 
-# Platform support list
+ccflags-y += -DAIC_TRACE_INCLUDE_PATH=$(src)
+MAKEFLAGS +=-j$(shell nproc)
+
+########## Platform support list ##########
 CONFIG_PLATFORM_ROCKCHIP ?= n
 CONFIG_PLATFORM_ROCKCHIP2 ?= n
 CONFIG_PLATFORM_ALLWINNER ?= n
@@ -296,32 +360,10 @@ CONFIG_PLATFORM_INGENIC_T20 ?= n
 CONFIG_PLATFORM_AMLOGIC ?= n
 CONFIG_PLATFORM_UBUNTU ?= y
 
-ccflags-y += -DAIC_TRACE_INCLUDE_PATH=$(src)
-
 ifeq ($(CONFIG_PLATFORM_ROCKCHIP), y)
-#KDIR ?= /home/yaya/E/Rockchip/3229/Android7/RK3229_ANDROID7.1_v1.01_20170914/rk3229_Android7.1_v1.01_xml0914/kernel
-#ARCH ?= arm
-#CROSS_COMPILE ?= /home/yaya/E/Rockchip/3229/Android7/RK3229_ANDROID7.1_v1.01_20170914/rk3229_Android7.1_v1.01_xml0914/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
-#KDIR  ?= /home/yaya/E/Rockchip/3399/rk3399-android-10/kernel
-#ARCH ?= arm64
-#CROSS_COMPILE ?= /home/yaya/E/Rockchip/3399/rk3399-android-10/prebuilts/gcc/linux-x86/aarch64/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
-#KDIR  ?= /home/yaya/E/Rockchip/3288/Android10/kernel/kernel/
-#ARCH ?= arm
-#CROSS_COMPILE ?= /home/yaya/E/Rockchip/3288/Android10/tool/gcc-linaro-6.3.1-2017.05-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-
-#KDIR  ?= /home/yaya/E/Rockchip/3229/Android9/rk3229_android9.0_box/kernel
-#ARCH ?= arm
-#CROSS_COMPILE ?= /home/yaya/E/Rockchip/3229/Android9/rk3229_android9.0_box/prebuilts/gcc/linux-x86/arm/gcc-linaro-6.3.1-2017.05-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-
-#KDIR ?= /home/yaya/E/Rockchip/3566/Android/kernel
-#ARCH ?= arm64
-#CROSS_COMPILE ?= /home/yaya/E/Rockchip/3566/Android/prebuilts/gcc/linux-x86/aarch64/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
-#KDIR ?= /home/yaya/E/Rockchip/3328/Android9/SDK/kernel/
-#ARCH ?= arm64
-#CROSS_COMPILE ?= /home/yaya/E/Rockchip/3328/Android9/SDK/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
-#KDIR ?= /home/yaya/E/Rockchip/3566/oudu/kernel
-KDIR ?= ~/E/Rockchip/3566/Android11/rk3566_rk3568_android11_oranth/kernel
-#KDIR ?= /home/yaya/E/Rockchip/3566/shengteng/kernel
-ARCH ?= arm64
-CROSS_COMPILE ?= ~/E/Rockchip/3566/Android11/rk3566_rk3568_android11_oranth/prebuilts/gcc/linux-x86/aarch64/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
+ARCH := arm64
+KDIR ?= /home/yaya/E/Rockchip/3566/firefly/Android11.0/Firefly-RK356X_Android11.0_git_20210824/RK356X_Android11.0/kernel
+CROSS_COMPILE := /home/yaya/E/Rockchip/3566/firefly/Android11.0/Firefly-RK356X_Android11.0_git_20210824/RK356X_Android11.0/prebuilts/gcc/linux-x86/aarch64/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
 ccflags-$(CONFIG_PLATFORM_ROCKCHIP) += -DCONFIG_PLATFORM_ROCKCHIP
 ccflags-y += -DANDROID_PLATFORM
 endif
@@ -356,6 +398,7 @@ ccflags-y += -DANDROID_PLATFORM
 endif
 
 ifeq ($(CONFIG_PLATFORM_UBUNTU), y)
+ccflags-$(CONFIG_PLATFORM_UBUNTU) += -DCONFIG_PLATFORM_UBUNTU
 KDIR  ?= /lib/modules/$(shell uname -r)/build
 PWD   ?= $(shell pwd)
 KVER ?= $(shell uname -r)
@@ -363,6 +406,7 @@ MODDESTDIR ?= /lib/modules/$(KVER)/kernel/drivers/net/wireless/
 ARCH ?= x86_64
 CROSS_COMPILE ?=
 endif
+###########################################
 
 
 all: modules

osdrv/extdrv/wireless/aic8800/aic8800_fdrv/aic_br_ext.c

@@ -1,17 +1,21 @@
 /******************************************************************************
  *
- * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *  Copyright (C) 2019-2021 Aicsemi Corporation
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
+ *  Licensed under the Apache License, Version 2.0 (the "License");
+ *  you may not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at:
  *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
+ *  http://www.apache.org/licenses/LICENSE-2.0
  *
- *****************************************************************************/
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ ******************************************************************************/
+
 #define _AIC_BR_EXT_C_
 
 #ifdef __KERNEL__

osdrv/extdrv/wireless/aic8800/aic8800_fdrv/aic_br_ext.h

@@ -1,17 +1,21 @@
 /******************************************************************************
  *
- * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *  Copyright (C) 2019-2021 Aicsemi Corporation
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
+ *  Licensed under the Apache License, Version 2.0 (the "License");
+ *  you may not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at:
  *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
+ *  http://www.apache.org/licenses/LICENSE-2.0
  *
- *****************************************************************************/
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ ******************************************************************************/
+
 #ifndef _AIC_BR_EXT_H_
 #define _AIC_BR_EXT_H_
 

osdrv/extdrv/wireless/aic8800/aic8800_fdrv/aic_bsp_export.h

@@ -23,7 +23,7 @@ enum skb_buff_id {
 	AIC_RESV_MEM_TXDATA,
 };
 
-#ifdef CONFIG_DPD
+#if defined(CONFIG_DPD) || defined(CONFIG_LOFT_CALIB)
 typedef struct {
     uint32_t bit_mask[3];
     uint32_t reserved;
@@ -45,10 +45,16 @@ typedef struct {
 
 #define MEMBER_SIZE(type, member)   sizeof(((type *)0)->member)
 #define DPD_RESULT_SIZE_8800DC      sizeof(rf_misc_ram_lite_t)
+#endif
 
+#ifdef CONFIG_DPD
 extern rf_misc_ram_lite_t dpd_res;
 #endif
 
+#ifdef CONFIG_LOFT_CALIB
+extern rf_misc_ram_lite_t loft_res_local;
+#endif
+
 int aicbsp_set_subsys(int, int);
 int aicbsp_get_feature(struct aicbsp_feature_t *feature, char *fw_path);
 bool aicbsp_get_load_fw_in_fdrv(void);

osdrv/extdrv/wireless/aic8800/aic8800_fdrv/aic_btsdio.h

@@ -0,0 +1,554 @@
+#ifndef _AICWF_SDIO_BT_H_
+#define _AICWF_SDIO_BT_H_
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/skbuff.h>
+#include <linux/errno.h>
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/poll.h>
+
+#include <linux/version.h>
+#include <linux/pm_runtime.h>
+#include <linux/firmware.h>
+#include <linux/suspend.h>
+
+
+#ifdef CONFIG_PLATFORM_UBUNTU
+#define CONFIG_BLUEDROID        0 /* bleuz 0, bluedroid 1, lbh 2 */
+#else
+#define CONFIG_BLUEDROID        1 /* bleuz 0, bluedroid 1, lbh 2 */
+#endif
+/* #define HCI_VERSION_CODE KERNEL_VERSION(3, 14, 41) */
+#define HCI_VERSION_CODE LINUX_VERSION_CODE
+
+
+#define PRINT_CMD_EVENT         1
+#define PRINT_ACL_DATA          1
+#define PRINT_SCO_DATA          1
+
+#define AICBT_DBG_FLAG          1
+
+#if AICBT_DBG_FLAG
+#define AICBT_DBG(fmt, arg...) printk( "aic_btsdio: " fmt "\n" , ## arg)
+#else
+#define AICBT_DBG(fmt, arg...)
+#endif
+
+#define AICBT_INFO(fmt, arg...) printk("aic_btsdio: " fmt "\n" , ## arg)
+#define AICBT_WARN(fmt, arg...) printk("aic_btsdio: " fmt "\n" , ## arg)
+#define AICBT_ERR(fmt, arg...) printk("aic_btsdio: " fmt "\n" , ## arg)
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3, 4, 0)
+#define GET_DRV_DATA(x)        hci_get_drvdata(x)
+#else
+#define GET_DRV_DATA(x)        x->driver_data
+#endif
+
+#if CONFIG_BLUEDROID
+struct btusb_data {
+    struct hci_dev       *hdev;
+    //struct usb_device    *udev;
+    //struct usb_interface *intf;
+    //struct usb_interface *isoc;
+
+    spinlock_t lock;
+
+    unsigned long flags;
+
+    struct work_struct work;
+    struct work_struct waker;
+
+    /*struct usb_anchor tx_anchor;
+    struct usb_anchor intr_anchor;
+    struct usb_anchor bulk_anchor;
+    struct usb_anchor isoc_anchor;
+    struct usb_anchor deferred;*/
+    int tx_in_flight;
+    spinlock_t txlock;
+	
+#if (CONFIG_BLUEDROID == 0)
+#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)
+		spinlock_t rxlock;
+		struct sk_buff *evt_skb;
+		struct sk_buff *acl_skb;
+		struct sk_buff *sco_skb;
+#endif
+#endif
+
+    /*struct usb_endpoint_descriptor *intr_ep;
+    struct usb_endpoint_descriptor *bulk_tx_ep;
+    struct usb_endpoint_descriptor *bulk_rx_ep;
+    struct usb_endpoint_descriptor *isoc_tx_ep;
+    struct usb_endpoint_descriptor *isoc_rx_ep;*/
+
+    __u8 cmdreq_type;
+
+    unsigned int sco_num;
+    int isoc_altsetting;
+    int suspend_count;
+    uint16_t sco_handle;
+
+#if (CONFIG_BLUEDROID == 0)
+#if HCI_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)
+    int (*recv_bulk) (struct btusb_data * data, void *buffer, int count);
+#endif
+#endif
+
+//#ifdef CONFIG_HAS_EARLYSUSPEND
+#if 0
+    struct early_suspend early_suspend;
+#else
+    struct notifier_block pm_notifier;
+    struct notifier_block reboot_notifier;
+#endif
+    //firmware_info *fw_info;
+
+#ifdef CONFIG_SCO_OVER_HCI
+    AIC_sco_card_t  *pSCOSnd;
+#endif
+};
+
+
+
+#define QUEUE_SIZE 500
+
+/***************************************
+** AicSemi - Integrate from bluetooth.h **
+*****************************************/
+/* Reserv for core and drivers use */
+#define BT_SKB_RESERVE    8
+
+/* BD Address */
+typedef struct {
+    __u8 b[6];
+} __packed bdaddr_t;
+
+/* Skb helpers */
+struct bt_skb_cb {
+    __u8 pkt_type;
+    __u8 incoming;
+    __u16 expect;
+    __u16 tx_seq;
+    __u8 retries;
+    __u8 sar;
+    __u8 force_active;
+};
+
+#define bt_cb(skb) ((struct bt_skb_cb *)((skb)->cb))
+
+
+/***********************************
+** AicSemi - Integrate from hci.h **
+***********************************/
+#define HCI_MAX_ACL_SIZE    1024
+#define HCI_MAX_SCO_SIZE    255
+#define HCI_MAX_EVENT_SIZE    260
+#define HCI_MAX_FRAME_SIZE    (HCI_MAX_ACL_SIZE + 4)
+
+/* HCI bus types */
+#define HCI_VIRTUAL    0
+#define HCI_USB        1
+#define HCI_PCCARD    2
+#define HCI_UART    3
+#define HCI_RS232    4
+#define HCI_PCI        5
+#define HCI_SDIO    6
+
+/* HCI controller types */
+#define HCI_BREDR    0x00
+#define HCI_AMP        0x01
+
+/* HCI device flags */
+enum {
+    HCI_UP,
+    HCI_INIT,
+    HCI_RUNNING,
+
+    HCI_PSCAN,
+    HCI_ISCAN,
+    HCI_AUTH,
+    HCI_ENCRYPT,
+    HCI_INQUIRY,
+
+    HCI_RAW,
+
+    HCI_RESET,
+};
+
+/*
+ * BR/EDR and/or LE controller flags: the flags defined here should represent
+ * states from the controller.
+ */
+enum {
+    HCI_SETUP,
+    HCI_AUTO_OFF,
+    HCI_MGMT,
+    HCI_PAIRABLE,
+    HCI_SERVICE_CACHE,
+    HCI_LINK_KEYS,
+    HCI_DEBUG_KEYS,
+    HCI_UNREGISTER,
+
+    HCI_LE_SCAN,
+    HCI_SSP_ENABLED,
+    HCI_HS_ENABLED,
+    HCI_LE_ENABLED,
+    HCI_CONNECTABLE,
+    HCI_DISCOVERABLE,
+    HCI_LINK_SECURITY,
+    HCI_PENDING_CLASS,
+};
+
+/* HCI data types */
+#define HCI_COMMAND_PKT        0x01
+#define HCI_ACLDATA_PKT        0x02
+#define HCI_SCODATA_PKT        0x03
+#define HCI_EVENT_PKT        0x04
+#define HCI_VENDOR_PKT        0xff
+
+#define HCI_MAX_NAME_LENGTH        248
+#define HCI_MAX_EIR_LENGTH        240
+
+#define HCI_OP_READ_LOCAL_VERSION    0x1001
+struct hci_rp_read_local_version {
+    __u8     status;
+    __u8     hci_ver;
+    __le16   hci_rev;
+    __u8     lmp_ver;
+    __le16   manufacturer;
+    __le16   lmp_subver;
+} __packed;
+
+#define HCI_EV_CMD_COMPLETE        0x0e
+struct hci_ev_cmd_complete {
+    __u8     ncmd;
+    __le16   opcode;
+} __packed;
+
+/* ---- HCI Packet structures ---- */
+#define HCI_COMMAND_HDR_SIZE 3
+#define HCI_EVENT_HDR_SIZE   2
+#define HCI_ACL_HDR_SIZE     4
+#define HCI_SCO_HDR_SIZE     3
+
+struct hci_command_hdr {
+    __le16    opcode;        /* OCF & OGF */
+    __u8    plen;
+} __packed;
+
+struct hci_event_hdr {
+    __u8    evt;
+    __u8    plen;
+} __packed;
+
+struct hci_acl_hdr {
+    __le16    handle;        /* Handle & Flags(PB, BC) */
+    __le16    dlen;
+} __packed;
+
+struct hci_sco_hdr {
+    __le16    handle;
+    __u8    dlen;
+} __packed;
+
+static inline struct hci_event_hdr *hci_event_hdr(const struct sk_buff *skb)
+{
+    return (struct hci_event_hdr *) skb->data;
+}
+
+static inline struct hci_acl_hdr *hci_acl_hdr(const struct sk_buff *skb)
+{
+    return (struct hci_acl_hdr *) skb->data;
+}
+
+static inline struct hci_sco_hdr *hci_sco_hdr(const struct sk_buff *skb)
+{
+    return (struct hci_sco_hdr *) skb->data;
+}
+
+/* ---- HCI Ioctl requests structures ---- */
+struct hci_dev_stats {
+    __u32 err_rx;
+    __u32 err_tx;
+    __u32 cmd_tx;
+    __u32 evt_rx;
+    __u32 acl_tx;
+    __u32 acl_rx;
+    __u32 sco_tx;
+    __u32 sco_rx;
+    __u32 byte_rx;
+    __u32 byte_tx;
+};
+/* AicSemi - Integrate from hci.h end */
+
+/*****************************************
+** AicSemi - Integrate from hci_core.h  **
+*****************************************/
+struct hci_conn_hash {
+    struct list_head list;
+    unsigned int     acl_num;
+    unsigned int     sco_num;
+    unsigned int     le_num;
+};
+
+#define HCI_MAX_SHORT_NAME_LENGTH    10
+
+#define NUM_REASSEMBLY 4
+struct hci_dev {
+    struct mutex    lock;
+
+    char        name[8];
+    unsigned long    flags;
+    __u16        id;
+    __u8        bus;
+    __u8        dev_type;
+
+    struct sk_buff        *reassembly[NUM_REASSEMBLY];
+
+    struct hci_conn_hash    conn_hash;
+
+    struct hci_dev_stats    stat;
+
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(3, 4, 0)
+    atomic_t        refcnt;
+    struct module           *owner;
+    void                    *driver_data;
+#endif
+
+    atomic_t        promisc;
+
+    struct device        *parent;
+    struct device        dev;
+
+    unsigned long        dev_flags;
+
+    int (*open)(struct hci_dev *hdev);
+    int (*close)(struct hci_dev *hdev);
+    int (*flush)(struct hci_dev *hdev);
+    int (*send)(struct sk_buff *skb);
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(3, 4, 0)
+    void (*destruct)(struct hci_dev *hdev);
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3, 7, 1)
+    __u16               voice_setting;
+#endif
+    void (*notify)(struct hci_dev *hdev, unsigned int evt);
+    int (*ioctl)(struct hci_dev *hdev, unsigned int cmd, unsigned long arg);
+	u8 *align_data;
+};
+
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(3, 4, 0)
+static inline struct hci_dev *__hci_dev_hold(struct hci_dev *d)
+{
+    atomic_inc(&d->refcnt);
+    return d;
+}
+
+static inline void __hci_dev_put(struct hci_dev *d)
+{
+    if (atomic_dec_and_test(&d->refcnt))
+        d->destruct(d);
+}
+#endif
+
+static inline void *hci_get_drvdata(struct hci_dev *hdev)
+{
+    return dev_get_drvdata(&hdev->dev);
+}
+
+static inline void hci_set_drvdata(struct hci_dev *hdev, void *data)
+{
+    dev_set_drvdata(&hdev->dev, data);
+}
+
+#define SET_HCIDEV_DEV(hdev, pdev) ((hdev)->parent = (pdev))
+
+
+/* ---- HCI Packet structures ---- */
+#define HCI_COMMAND_HDR_SIZE 3
+#define HCI_EVENT_HDR_SIZE   2
+#define HCI_ACL_HDR_SIZE     4
+#define HCI_SCO_HDR_SIZE     3
+
+/* -----  HCI Commands ---- */
+#define HCI_OP_INQUIRY            0x0401
+#define HCI_OP_INQUIRY_CANCEL        0x0402
+#define HCI_OP_EXIT_PERIODIC_INQ    0x0404
+#define HCI_OP_CREATE_CONN        0x0405
+#define HCI_OP_DISCONNECT                0x0406
+#define HCI_OP_ADD_SCO            0x0407
+#define HCI_OP_CREATE_CONN_CANCEL    0x0408
+#define HCI_OP_ACCEPT_CONN_REQ        0x0409
+#define HCI_OP_REJECT_CONN_REQ        0x040a
+#define HCI_OP_LINK_KEY_REPLY        0x040b
+#define HCI_OP_LINK_KEY_NEG_REPLY    0x040c
+#define HCI_OP_PIN_CODE_REPLY        0x040d
+#define HCI_OP_PIN_CODE_NEG_REPLY    0x040e
+#define HCI_OP_CHANGE_CONN_PTYPE    0x040f
+#define HCI_OP_AUTH_REQUESTED        0x0411
+#define HCI_OP_SET_CONN_ENCRYPT        0x0413
+#define HCI_OP_CHANGE_CONN_LINK_KEY    0x0415
+#define HCI_OP_REMOTE_NAME_REQ        0x0419
+#define HCI_OP_REMOTE_NAME_REQ_CANCEL    0x041a
+#define HCI_OP_READ_REMOTE_FEATURES    0x041b
+#define HCI_OP_READ_REMOTE_EXT_FEATURES    0x041c
+#define HCI_OP_READ_REMOTE_VERSION    0x041d
+#define HCI_OP_SETUP_SYNC_CONN        0x0428
+#define HCI_OP_ACCEPT_SYNC_CONN_REQ    0x0429
+#define HCI_OP_REJECT_SYNC_CONN_REQ    0x042a
+#define HCI_OP_SNIFF_MODE        0x0803
+#define HCI_OP_EXIT_SNIFF_MODE        0x0804
+#define HCI_OP_ROLE_DISCOVERY        0x0809
+#define HCI_OP_SWITCH_ROLE        0x080b
+#define HCI_OP_READ_LINK_POLICY        0x080c
+#define HCI_OP_WRITE_LINK_POLICY    0x080d
+#define HCI_OP_READ_DEF_LINK_POLICY    0x080e
+#define HCI_OP_WRITE_DEF_LINK_POLICY    0x080f
+#define HCI_OP_SNIFF_SUBRATE        0x0811
+#define HCI_OP_Write_Link_Policy_Settings 0x080d
+#define HCI_OP_SET_EVENT_MASK        0x0c01
+#define HCI_OP_RESET            0x0c03
+#define HCI_OP_SET_EVENT_FLT        0x0c05
+#define HCI_OP_Write_Extended_Inquiry_Response        0x0c52
+#define HCI_OP_Write_Simple_Pairing_Mode 0x0c56
+#define HCI_OP_Read_Buffer_Size 0x1005
+#define HCI_OP_Host_Buffer_Size 0x0c33
+#define HCI_OP_Read_Local_Version_Information 0x1001
+#define HCI_OP_Read_BD_ADDR 0x1009
+#define HCI_OP_Read_Local_Supported_Commands 0x1002
+#define HCI_OP_Write_Scan_Enable 0x0c1a
+#define HCI_OP_Write_Current_IAC_LAP 0x0c3a
+#define HCI_OP_Write_Inquiry_Scan_Activity 0x0c1e
+#define HCI_OP_Write_Class_of_Device 0x0c24
+#define HCI_OP_LE_Rand 0x2018
+#define HCI_OP_LE_Set_Random_Address 0x2005
+#define HCI_OP_LE_Set_Extended_Scan_Enable 0x2042
+#define HCI_OP_LE_Set_Extended_Scan_Parameters 0x2041
+#define HCI_OP_Set_Event_Filter 0x0c05
+#define HCI_OP_Write_Voice_Setting 0x0c26
+#define HCI_OP_Change_Local_Name 0x0c13
+#define HCI_OP_Read_Local_Name 0x0c14
+#define HCI_OP_Wirte_Page_Timeout 0x0c18
+#define HCI_OP_LE_Clear_Resolving_List 0x0c29
+#define HCI_OP_LE_Set_Addres_Resolution_Enable_Command 0x0c2e
+#define HCI_OP_Write_Inquiry_mode 0x0c45
+#define HCI_OP_Write_Page_Scan_Type 0x0c47
+#define HCI_OP_Write_Inquiry_Scan_Type 0x0c43
+
+#define HCI_OP_Delete_Stored_Link_Key 0x0c12
+#define HCI_OP_LE_Read_Local_Resolvable_Address 0x202d
+#define HCI_OP_LE_Extended_Create_Connection 0x2043
+#define HCI_OP_Read_Remote_Version_Information 0x041d
+#define HCI_OP_LE_Start_Encryption 0x2019
+#define HCI_OP_LE_Add_Device_to_Resolving_List 0x2027
+#define HCI_OP_LE_Set_Privacy_Mode 0x204e
+#define HCI_OP_LE_Connection_Update 0x2013
+
+/* -----  HCI events---- */
+#define HCI_OP_DISCONNECT        0x0406
+#define HCI_EV_INQUIRY_COMPLETE        0x01
+#define HCI_EV_INQUIRY_RESULT        0x02
+#define HCI_EV_CONN_COMPLETE        0x03
+#define HCI_EV_CONN_REQUEST            0x04
+#define HCI_EV_DISCONN_COMPLETE        0x05
+#define HCI_EV_AUTH_COMPLETE        0x06
+#define HCI_EV_REMOTE_NAME            0x07
+#define HCI_EV_ENCRYPT_CHANGE        0x08
+#define HCI_EV_CHANGE_LINK_KEY_COMPLETE    0x09
+
+#define HCI_EV_REMOTE_FEATURES        0x0b
+#define HCI_EV_REMOTE_VERSION        0x0c
+#define HCI_EV_QOS_SETUP_COMPLETE    0x0d
+#define HCI_EV_CMD_COMPLETE            0x0e
+#define HCI_EV_CMD_STATUS            0x0f
+
+#define HCI_EV_ROLE_CHANGE            0x12
+#define HCI_EV_NUM_COMP_PKTS        0x13
+#define HCI_EV_MODE_CHANGE            0x14
+#define HCI_EV_PIN_CODE_REQ            0x16
+#define HCI_EV_LINK_KEY_REQ            0x17
+#define HCI_EV_LINK_KEY_NOTIFY        0x18
+#define HCI_EV_CLOCK_OFFSET            0x1c
+#define HCI_EV_PKT_TYPE_CHANGE        0x1d
+#define HCI_EV_PSCAN_REP_MODE        0x20
+
+#define HCI_EV_INQUIRY_RESULT_WITH_RSSI    0x22
+#define HCI_EV_REMOTE_EXT_FEATURES    0x23
+#define HCI_EV_SYNC_CONN_COMPLETE    0x2c
+#define HCI_EV_SYNC_CONN_CHANGED    0x2d
+#define HCI_EV_SNIFF_SUBRATE            0x2e
+#define HCI_EV_EXTENDED_INQUIRY_RESULT    0x2f
+#define HCI_EV_IO_CAPA_REQUEST        0x31
+#define HCI_EV_SIMPLE_PAIR_COMPLETE    0x36
+#define HCI_EV_REMOTE_HOST_FEATURES    0x3d
+#define HCI_EV_LE_Meta 0x3e
+
+/* ULP Event sub code */
+#define HCI_BLE_CONN_COMPLETE_EVT 0x01
+#define HCI_BLE_ADV_PKT_RPT_EVT 0x02
+#define HCI_BLE_LL_CONN_PARAM_UPD_EVT 0x03
+#define HCI_BLE_READ_REMOTE_FEAT_CMPL_EVT 0x04
+#define HCI_BLE_LTK_REQ_EVT 0x05
+#define HCI_BLE_RC_PARAM_REQ_EVT 0x06
+#define HCI_BLE_DATA_LENGTH_CHANGE_EVT 0x07
+#define HCI_BLE_ENHANCED_CONN_COMPLETE_EVT 0x0a
+#define HCI_BLE_DIRECT_ADV_EVT 0x0b
+#define HCI_BLE_PHY_UPDATE_COMPLETE_EVT 0x0c
+#define HCI_LE_EXTENDED_ADVERTISING_REPORT_EVT 0x0D
+#define HCI_BLE_PERIODIC_ADV_SYNC_EST_EVT      0x0E
+#define HCI_BLE_PERIODIC_ADV_REPORT_EVT        0x0F
+#define HCI_BLE_PERIODIC_ADV_SYNC_LOST_EVT     0x10
+#define HCI_BLE_SCAN_TIMEOUT_EVT               0x11
+#define HCI_LE_ADVERTISING_SET_TERMINATED_EVT 0x12
+#define HCI_BLE_SCAN_REQ_RX_EVT                0x13
+#define HCI_BLE_CIS_EST_EVT 0x19
+#define HCI_BLE_CIS_REQ_EVT 0x1a
+#define HCI_BLE_CREATE_BIG_CPL_EVT 0x1b
+#define HCI_BLE_TERM_BIG_CPL_EVT 0x1c
+#define HCI_BLE_BIG_SYNC_EST_EVT 0x1d
+#define HCI_BLE_BIG_SYNC_LOST_EVT 0x1e
+#define HCI_BLE_REQ_PEER_SCA_CPL_EVT 0x1f
+
+#define HCI_VENDOR_SPECIFIC_EVT 0xFF /* Vendor specific events */
+
+#define CONFIG_MAC_OFFSET_GEN_1_2       (0x3C)      //MAC's OFFSET in config/efuse for aic generation 1~2 bluetooth chip
+#define CONFIG_MAC_OFFSET_GEN_3PLUS     (0x44)      //MAC's OFFSET in config/efuse for aic generation 3+ bluetooth chip
+
+//Define ioctl cmd the same as HCIDEVUP in the kernel
+#define DOWN_FW_CFG             _IOW('E', 176, int)
+//#ifdef CONFIG_SCO_OVER_HCI
+//#define SET_ISO_CFG             _IOW('H', 202, int)
+//#else
+#define SET_ISO_CFG             _IOW('E', 177, int)
+//#endif
+#define RESET_CONTROLLER        _IOW('E', 178, int)
+#define DWFW_CMPLT              _IOW('E', 179, int)
+
+#define GET_USB_INFO            _IOR('E', 180, int)
+
+void bt_data_dump(char* tag, void* data, unsigned long len);
+int aic_enqueue(struct sk_buff *skb);
+int aic_queue_cnt(void);
+int bt_sdio_recv(u8 *data,u32 data_len);
+
+
+int btchr_init(void);
+void btchr_exit(void);
+int hdev_init(void);
+void hdev_exit(void);
+
+
+struct hci_dev *hci_dev_get(int index);
+int hci_recv_fragment(struct hci_dev *hdev, int type, void *data, int count);
+#else
+int btsdio_init(void);
+void btsdio_remove(void);
+int bt_sdio_recv(u8 *data,u32 data_len);
+#endif
+#endif//_AICWF_SDIO_BT_H_
+

osdrv/extdrv/wireless/aic8800/aic8800_fdrv/aic_priv_cmd.h

@@ -0,0 +1,33 @@
+/**
+ ******************************************************************************
+ *
+ * @file private_cmd.h
+ *
+ * Copyright (C) Aicsemi 2018-2024
+ *
+ ******************************************************************************
+ */
+
+#ifndef _AIC_PRIV_CMD_H_
+#define _AIC_PRIV_CMD_H_
+
+#include "rwnx_defs.h"
+
+typedef struct _android_wifi_priv_cmd {
+    char *buf;
+    int used_len;
+    int total_len;
+} android_wifi_priv_cmd;
+
+#ifdef CONFIG_COMPAT
+typedef struct _compat_android_wifi_priv_cmd {
+    compat_caddr_t buf;
+    int used_len;
+    int total_len;
+} compat_android_wifi_priv_cmd;
+#endif /* CONFIG_COMPAT */
+
+int android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd);
+
+#endif /* _AIC_PRIV_CMD_H_ */
+