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Enable boxFilter OpenCL fast paths on all aligned GPUs.
Remove Intel-only gates for the 3x3 8UC1 cols16/rows2 kernel and the filterSmall path while keeping alignment and kernel-size preconditions.
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@@ -60,7 +60,6 @@ namespace cv {
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static bool ocl_boxFilter3x3_8UC1( InputArray _src, OutputArray _dst, int ddepth,
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Size ksize, Point anchor, int borderType, bool normalize )
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{
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const ocl::Device & dev = ocl::Device::getDefault();
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int type = _src.type(), sdepth = CV_MAT_DEPTH(type), cn = CV_MAT_CN(type);
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if (ddepth < 0)
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@@ -71,7 +70,7 @@ static bool ocl_boxFilter3x3_8UC1( InputArray _src, OutputArray _dst, int ddepth
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if (anchor.y < 0)
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anchor.y = ksize.height / 2;
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if ( !(dev.isIntel() && (type == CV_8UC1) &&
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if ( !(type == CV_8UC1 &&
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(_src.offset() == 0) && (_src.step() % 4 == 0) &&
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(_src.cols() % 16 == 0) && (_src.rows() % 2 == 0) &&
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(anchor.x == 1) && (anchor.y == 1) &&
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@@ -159,7 +158,7 @@ static bool ocl_boxFilter( InputArray _src, OutputArray _dst, int ddepth,
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ocl::Kernel kernel;
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if (dev.isIntel() && !(dev.type() & ocl::Device::TYPE_CPU) &&
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if (!(dev.type() & ocl::Device::TYPE_CPU) &&
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((ksize.width < 5 && ksize.height < 5 && esz <= 4) ||
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(ksize.width == 5 && ksize.height == 5 && cn == 1)))
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{
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