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add unfinished docs

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wonderfullook
2022-10-23 21:22:32 +08:00
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79
docs/hardware/en/tang/tang-primer-20k/examples/lite/blink.md
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@@ -28,4 +28,81 @@ Because of the DDR test function, Core Board will be very hot. you can erase the
Visit [Install IDE](./../../../Tang-Nano-Doc/install-the-ide.md) to prepare the enviroment for this FPGA.
For windows users, we recommend use this
For windows users, we recommend use this [Programmer](https://dl.sipeed.com/shareURL/TANG/programmer) application install the Programmer application installed with IDE, this can reduce many trobules we will meet.
For Linux users, if it's difficult to run Programmer application to burn firmware into fpga, please visit [OpenFpgaloader](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-Doc/flash-in-linux.html) to see how to use it.
## New Project
New Project：File-->NEW-->FPGA Dsign Project-->OK
<div>
<img src="./../../../Tang-Nano-1K/assets/LED-1.png" width=58% alt="new_project">
<img src="./../../../Tang-Nano-1K/assets/LED-2.png" width=35% alt="fpga_project">
</div>
Set Project Name and path, Project Name and project path should be English.
![project_path](./../../../../../../../news/others/20k_lite_start/assets/project_path.png)
Select Device we choose GW2A-LV18PG256C8/I7, use filter like below to help us choose device more easy. Note that the Device is GW2A-18C.
![device_choose](./../../../../../../../news/others/20k_lite_start/assets/device_choose.png)
Then click OK to preview the project. After confirming no error, the project is created.
## New file
Gowin IDE contains 3 ways to create file. Here we use shortcuts keys `Ctrl + N` to new a file. The other 2 ways to new file are not mentioned here,
In the pop-up windows, we choose `Verilog File`, you can also choose `VHDL File` if you are good at it. Here we just use Verilog as example.
<img src="./../../../../../../../news/others/20k_lite_start/assets/new_verilog_file.png" width=50% alt="new_verilog_file">
Then click OK to set the file name, here we take `led` as the verilog file name as example.
<img src="./../../../../../../../news/others/20k_lite_start/assets/file_name.png" width=75% alt="file_name">
Up to now we have finished creating file, then we need to prepare our code.
![created_file](./../../../../../../../news/others/20k_lite_start/assets/created_file.png)
### Verilog introduction
Verilog is a kind of Hardware Description Language(HDL), it's used to describe digital circuits.
The basic unit in Verilog is module.
A module is composed of two parts: one describes the interface, and the other describes the internal logic function, that is, defines how the input affects the output.
A module is like this:
```v
module module_name
#(parameter)
(port) ;
function
endmodule
```
The module starts from module and ends by endmodule. The module is followed by the module name (module_name), transitable variable parameters (parameter), port and direction declaration (port), followed by internal logic function description (function), and finally, endmodule is used to represent this module.
The internal logic function is usually composed by the assign and always blocks; The assign statement describes logical circuit, and the always block is used to describe timing circuit.
### Think storm
Before coding, we need to think our purpose: The led flashes every 0.5S.
Then we draw demand block diagram as follows:
![block_method](./../../../../../../../news/others/20k_lite_start/assets/block_method.png)
然后对于 0.5S 我们需要一个计数器来计时，LED 灯闪就是 IO 翻转
![count_block](./../../../../../../../news/others/20k_lite_start/assets/time_count.png)
把上面的思维框图具体到实际使用的话，就变成下面的样式了:
![clock_time_count](./../../../../../../../news/others/20k_lite_start/assets/clock_time_count.png)
其中 Clock 为时钟源，用来给计时器提供准确的时间。

2
docs/hardware/zh/tang/Tang-Nano-Doc/questions.md
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@@ -241,7 +241,7 @@ update:
GAO 是高云半导体在线逻辑分析仪（Gowin Analyzer Oscilloscope）。安装高云 IDE 之后就能在对应的安装相对路径下看到相关文档了
![gao](./questions/gao.png)
![gao](./../assets/questions/gao.png)
使用高云半导体所提供的最新的教育版的编程器 [点我跳转](http://www.gowinsemi.com.cn/faq.aspx) 能够正常使用 GAO（因为 GAO 必须在 IDE 内才能打开，所以你需要自己替换掉安装时候的 Programmer 文件夹，并且确定替换后的路径与之前的相同）。

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news/others/20k_lite_start/20k_lite_start.md
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@@ -33,7 +33,7 @@ update:
对于 Windows 用户需要额外下载一下 [Programmer](https://dl.sipeed.com/shareURL/TANG/programmer) 烧录专用软件可以降低我们在烧录的时候出现问题的可能性。
对于 Linux 用户的话建议使用 [openfpgaLoader](https://wiki.sipeed.com/hardware/zh/tang/Tang-Nano-Doc/get_started/flash_in_linux.html) 这软件来烧录 GW2A-18。
对于 Linux 用户，如果打开 Programmer 烧录软件困难的话，可以使用 [openfpgaLoader](https://wiki.sipeed.com/hardware/zh/tang/Tang-Nano-Doc/get_started/flash_in_linux.html) 这软件来烧录 GW2A-18，相关用法在 [OpenFpgaloader](https://wiki.sipeed.com/hardware/zh/tang/Tang-Nano-Doc/get_started/flash_in_linux.html) 一文中有说明。
## 新建工程
@@ -44,7 +44,7 @@ update:
<img src="./assets/fpga_project.png" width=35% alt="fpga_project">
</div>
设置工程名称，要求只用英文的下划线命名，存放路径中不要有中文字符或者空格等。
设置工程名称，要求只用英文和下划线命名，存放路径中不要有中文字符或者空格等。
![project_path](./assets/project_path.png)