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RVV: add fused HAL implementation for rotate - #30057 ## Pull Request Readiness Checklist See details at [https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request](https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request) - [x] I agree to contribute to the project under the Apache 2 License. - [x] To the best of my knowledge, the proposed patch is not based on code under GPL or another license that is incompatible with OpenCV. - [x] The PR is proposed to the proper branch (`4.x`). - [x] Accuracy tests are included and performance results are provided below. ## Summary This PR adds an RVV HAL implementation for `cv_hal_rotate90` and fuses the transpose and flip operations used by 90-degree and 270-degree rotations into a single vectorized pass. The previous path composes transpose and flip operations, which requires an intermediate image and additional memory traffic. The new RVV path loads several source rows, builds RVV vector tuples, and writes directly to the final rotated positions with strided segmented stores. ## Implementation details - Registers `cv_hal_rotate90` in the RISC-V RVV core HAL. - Processes 1-, 2-, and 8-byte elements in blocks of eight source rows using `vssseg8e8`, `vssseg8e16`, and `vssseg8e64`. - Processes 4-byte elements in blocks of four source rows using `vssseg4e32`. - Uses positive or negative destination strides to implement clockwise and counter-clockwise rotation without a separate flip pass. - Uses dynamic VL and strided vector stores for remaining rows and non-multiple tails. - Supports padded/non-contiguous source rows through `src_step` and `dst_step`. - Returns `CV_HAL_ERROR_NOT_IMPLEMENTED` for aliased input/output and unsupported element sizes, preserving the existing OpenCV fallback behavior. - Keeps the existing RVV flip path for 180-degree rotation when safe. - For 1-byte 180-degree rotation with `VLMAX > 256`, uses 16-bit gather indices with `vrgatherei16` to avoid index wraparound in the existing 8-bit gather path. - Includes compatibility helpers for Clang versions earlier than 18 that do not provide the required vector tuple creation intrinsics. The directly accelerated total element sizes are 1, 2, 4, and 8 bytes. Other sizes, including common 3- and 6-byte pixel formats, fall back to the existing implementation. ## Test environment ```text Build type: Release Compiler: GCC 14.2.0 ISA flags: -march=rv64gcv RISCV_RVV_SCALABLE: ON CPU_BASELINE_REQUIRE: RVV QEMU: 8.2.2, RVV 1.0 ``` ## Accuracy tests The new `Core_Rotate.OddSizesAndPaddedRows` test and the existing randomized rotate test passed under QEMU RVV at VLEN 128, 256, 512, and 1024. ## Performance tests Performance was measured with `opencv_perf_core` under the environment described above. Detailed performance results are provided in the comment below. These measurements are intended to show the relative difference between identical baseline and optimized builds under QEMU. Absolute performance should be confirmed on RISC-V hardware.