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con4a，组装文档
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SinKy-Yan
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---
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title: Tang Mega 138K Pro Dock
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keywords: FPGA, Tang, Mega, 138K
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update:
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- date: 2023-08-29
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version: v
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author: wonder
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content:
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- 新建文档
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---
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- Product Overview
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Tang Mega 138K uses a 22nm process GW5AST-LV138FPG676A FPGA chip, which has 138,240 lookup table units and nearly 300 DSP units. It contains eight high-speed transceivers with a speed range of 270Mbps ~ 12.5Gbps, suitable for transmitting data through high-speed ports such as fiber optics or PCIE. In addition, the chip contains a hard-core PCIE, which consumes better resources when using PCIE and achieves better performance. It is suitable for high-speed communication, protocol conversion, high-performance computing, and other occasions.
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aliexpress purchase link: [Click me](https://www.aliexpress.us/item/3256805893801730.html)
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## Board Features
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- Large capacity LUT
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- Large capacity memory
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- PCIE3.0 x 4
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- SFP+ x 2
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- RISCV hard core
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## Product Appearance
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<img src="./assets/mega_138k_top.png" width="45%">
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## Hardware Parameters
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### Core Board Parameters
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<table>
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<thead>
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<tr>
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<th style="text-align:center">Item</th>
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<th style="text-align:center">Parameter</th>
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<th style="text-align:center">Supplement</th>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td style="text-align:left">FPGA Chip</td>
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<td style="text-align:left"><a href="http://www.gowinsemi.com.cn/prod_view.aspx?TypeId=10&FId=t3:10:3&Id=167#GW2A">GW5AST-LV138FPG676A</a>
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</td>
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<td style="text-align:left">
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<table>
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<tr>
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<td>Logic Unit (LUT4)</td>
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<td>138240</td>
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</tr>
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<tr>
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<td>Register (FF)</td>
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<td>138240</td>
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</tr>
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<tr>
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<td>Distributed SRAM (S-SRAM) (Kbits)</td>
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<td>1080</td>
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</tr>
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<tr>
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<td>Block SRAM (B-SRAM) (Kbits)</td>
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<td>6120</td>
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</tr>
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<tr>
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<td>Number of Block SRAMs (B-SRAM) (pcs)</td>
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<td>340</td>
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</tr>
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<tr>
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<td>Multiplier (18x18 Multiplier)</td>
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<td>298</td>
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</tr>
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<tr>
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<td>Phase-Locked Loop (PLLs)</td>
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<td>12</td>
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</tr>
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<tr>
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<td>Global Clock</td>
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<td>16</td>
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</tr>
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<tr>
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<td>High-Speed Clock</td>
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<td>24</td>
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</tr>
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<tr>
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<td>Transceivers</td>
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<td>8</td>
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</tr>
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<tr>
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<td>Transceivers Rate</td>
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<td>270Mbps-12.5Gbps</td>
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</tr>
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<tr>
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<td>PCIE Hard Core</td>
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<td>1<br>Speed optional x1, x2, x4, x8 PCIe 2.0</td>
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</tr>
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<tr>
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<td>LVDS (Gbps)</td>
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<td>1.25</td>
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</tr>
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<tr>
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<td>DDR3 (Mbps)</td>
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<td>1,333</td>
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</tr>
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<tr>
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<td>MIPI D-PHY Hard Core</td>
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<td>2.5Gbps (RX),<br>8 data channels,<br>2 clock channels</td>
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</tr>
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<tr>
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<td>Hard Core Processor</td>
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<td>RiscV AE350_SOC</td>
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</tr>
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<tr>
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<td>ADC</td>
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<td>2</td>
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</tr>
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<tr>
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<td>Total I/O Bank</td>
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<td>10</td>
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</tr>
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</table>
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</td>
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</tr>
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<tr>
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<td style="text-align:left">Memory</td>
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<td style="text-align:left">1GB DDR3</td>
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<td style="text-align:left">512MB x 2</td>
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</tr>
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<tr>
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<td style="text-align:left">Flash</td>
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<td style="text-align:left">128Mbits Flash x 2</td>
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<td style="text-align:left">See <a href="#burn_flash">How to Burn to Flash</a></td>
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</tr>
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<tr>
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<td style="text-align:left">Debug Interface</td>
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<td style="text-align:left">Jtag + Uart</td>
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<td style="text-align:left">JST SH1.0 8Pins Connector</td>
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</tr>
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<tr>
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<td style="text-align:left">Overall Package</td>
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<td style="text-align:left">50mm x 70mm Size</td>
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<td style="text-align:left">BTB Connector Connects the Core Board and the Base Board</td>
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</tr>
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</tbody>
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</table>
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### Baseboard Parameters
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| Item | Quantity | Remarks |
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| :------------------ | -------- | ------------------------------------------------- |
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| LED | 6 | |
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| WS2812 | 1 | |
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| Button | 4 | |
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| PCIE | 1 | |
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| SFP+ | 2 | |
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| Gigabit Ethernet | 1 | |
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| DVI RX | 2 | Mutually occupied with DVI TX |
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| DVI TX | 2 | Mutually occupied with DVI RX |
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| PMOD | 3 | |
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| ADC | 2 | |
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| MIPI CSI | 2 | 3 LANE MIPI CSI |
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| ARGB | 1 | Same data pin with WS2812 |
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| DVP Interface | 1 | |
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| RGB Interface | 1 | Supports RGB888 screen |
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| MIC ARRAY Interface | 1 | Supports connecting Sipeed 6+1 microphone array |
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| SD Card Slot | 1 | |
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| EEPROM | 1 | Can store necessary information |
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| M.2 Socket | 1 | Reserved, can write peripheral driver yourself |
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| PWM Fan Interface | 1 | |
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| Speaker Interface | 1 | |
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| 3.5mm Headphone Jack| 1 | |
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| Custom USB | 1 | Cannot power the board |
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| MS5351 | 2 | Provides RefClk for Serdes; control output via onboard UART |
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| USB JTAG&UART | 1 | Supports FPGA programming and provides UART function |
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| 40P Pin Header | 1 | |
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| Power Switch | 1 | |
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| 12V DC | 1 | |
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## Hardware Resources
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[Board Specification](https://dl.sipeed.com/shareURL/TANG/Mega_138K_Pro/01_Specification)
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[Board Schematic](https://dl.sipeed.com/shareURL/TANG/Mega_138K_Pro/02_Schematic)
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[PCB BOM](https://dl.sipeed.com/shareURL/TANG/Mega_138K_Pro/03_Designator_drawing)
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[Board Dimension Diagram](https://dl.sipeed.com/shareURL/TANG/Mega_138K_Pro/04_Mechanical_drawing)
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[Board 3D Model](https://dl.sipeed.com/shareURL/TANG/Mega_138K_Pro/05_3D_file)
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[Some Chip Manuals](https://dl.sipeed.com/shareURL/TANG/Mega_138K_Pro/07_Datasheet)
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## Getting Started
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Note that 138K is currently not supported by the education version, and you need to download V1.9.9Beta-5 or a newer version of the commercial IDE for use.
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Lic can be applied on the Gowin official website, or you can use the online Lic service provided by Sipeed. In the IDE, select Float Lic and fill in the following information:
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~~~
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ip: 43.128.7.128
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port: 10559
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~~~
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Install IDE [Click me](https://wiki.sipeed.com/hardware/zh/tang/Tang-Nano-Doc/get_started/install-the-ide.html)
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Example code [github](https://github.com/sipeed/TangMega-138KPro-example)
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- Other Learning Resources
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- Free online tutorial: [Verilog Tutorial](https://www.runoob.com/w3cnote/verilog-tutorial.html) (Learn Verilog)
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- Free online FPGA tutorial: [Verilog](https://www.asic-world.com/verilog/index.html) (English website)
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- Verilog practice website: [HDLBits](https://hdlbits.01xz.net/wiki/Main_Page) (English website)
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- Online Gowin Semiconductor reference video tutorials: [Click here](http://www.gowinsemi.com.cn/video_complex.aspx?FId=n15:15:26)
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## Communication Methods
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- **Discussion forum: [maixhub.com/discussion](https://maixhub.com/discussion)**
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- **QQ discussion group: [834585530](https://jq.qq.com/?_wv=1027&k=wBb8XUan)**
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- Leave a message directly below this page
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- Business email : [support@sipeed.com](support@sipeed.com)
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## Precautions
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<table>
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<tr>
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<th>Item</th>
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<th>Precautions</th>
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</tr>
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<tr>
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<td>Chip Model</td>
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<td>The specific model of the FPGA chip used by Tang Mega 138K Pro is GW5AST-LV138FPG676A. Please select the package model FCPBG676A in the IDE.</td>
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</tr>
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<tr>
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<td>Static Electricity</td>
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<td>Please avoid static electricity hitting the PCBA; release the static electricity from your hands before touching the PCBA.</td>
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</tr>
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<tr>
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<td>Tolerance Voltage</td>
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<td>When using GPIO pin headers for external communication, ensure that the IO voltage is 3.3V. Excessive voltage will permanently damage the PCBA.</td>
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</tr>
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<tr>
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<td>FPC Socket</td>
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<td>When connecting the FPC soft cable, please ensure that the cable is completely and correctly inserted into the socket without any deviation.</td>
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</tr>
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<tr>
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<td>PCIE Gold Finger</td>
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<td>When testing the PCIE gold finger, ensure that both the host and the board are in the off or unpowered state to avoid short-circuiting the gold finger due to displacement during the insertion process.</td>
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</tr>
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<tr>
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<td>Plug and Unplug</td>
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<td>Please completely power off before plugging and unplugging.</td>
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</tr>
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<tr>
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<td>Avoid Short Circuit</td>
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<td>Please avoid any liquid or metal touching the solder pads of the components on the PCBA during the power-on process, otherwise it may cause a short circuit and burn the PCBA.</td>
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</tr>
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</table>
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## Contact
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Tang Mega 138K can meet different needs of customers in various scenarios. For technical support and business cooperation, please contact [support@sipeed.com](support@sipeed.com)
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## Frequently Asked Questions
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### The power light is not on after the board is powered on
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1. Please check if the power switch of the board is turned on.
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2. Check your power supply method.
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