fix: correct typos in different files (#697)

* fix: correct typos in different files

README.md

@@ -27,7 +27,7 @@ teedoc serve
 
 More build tool usage see [teedoc](http://github.com/teedoc/teedoc)
 
-## For administator
+## For administrator
 
 GitHub action will automatically push changed doc to cloud server.
 But if you did some special things like force commit, some files maybe missing on server, manually trigger the publish_upload_all action to build doc and upload all files to server.

config/config_en.json

@@ -109,7 +109,7 @@
                     "target": "_blank"
                 },
                 {
-                    "label": "Open Souece Projects",
+                    "label": "Open Source Projects",
                     "url": "https://github.com/sipeed",
                     "target": "_blank"
                 }

docs/hardware/en/lichee/RV/86_panel.md

@@ -2,7 +2,7 @@
 
 ## Introduction
 
-Lichee RV-86 Panel is a development kit designed for smart home central control sence. it's equipped with LicheeRV Core board (ALlwinner D1 chip with 512MB ddr3), 4-inch touch IPS screen, Wifi+BT module, Ethernet, two digital silicon mic and GPIO expansion interface. For software it can use Linux OS (Openwrt or Debian) and Ali WATF(WAFT is a high-performance application research framework for aiot based on WebAssembly and their own rendering engine)
+Lichee RV-86 Panel is a development kit designed for smart home central control scene. It's equipped with LicheeRV Core board (Allwinner D1 chip with 512MB ddr3), 4-inch touch IPS screen, Wifi+BT module, Ethernet, two digital silicon mic and GPIO expansion interface. For software it can use Linux OS (OpenWrt or Debian) and Ali WAFT (WAFT is a high-performance application research framework for AIoT based on WebAssembly and their own rendering engine)
 
 ![Basic board](./../assets/RV/86_2.png)
 
@@ -35,4 +35,4 @@ Lichee RV-86 Panel is a development kit designed for smart home central control
 
 ## Support
 
-Email to support@sipeed.com for business cooperation or leave messge in this page for help.
+Email to support@sipeed.com for business cooperation or leave message on this page for help.

docs/hardware/en/lichee/RV/Dock.md

@@ -16,7 +16,7 @@ Lichee RV Dock is a RISC-V Linux development kits with high integration, small s
 | USB | Onboard USB type-A host |
 | Audio | On-board speaker driver circuit (supports 4Ω 3W speakers) and speaker; connector<br>On-board electrical microphone circuit |
 | Memory | Reserved a SOP8 pad, and the connection protocol is the SPI; <br> Consult for the customer service staff for more information |
-| Extra connector | Onborad 30P FPC connector，supports our Mic Array R6 microphone array |
+| Extra connector | Onboard 30P FPC connector，supports our Mic Array R6 microphone array |
 | GPIO connector | Reserved 2x20P 2.54mm pads(Default welding pin headers) |
 | LED | An onboard WS2812 RGB LED<br> An onboard power LED |
 | KEY | An onboard reset key<br>An user's key |
@@ -32,4 +32,4 @@ Lichee RV Dock is a RISC-V Linux development kits with high integration, small s
 
 ## Support
 
-Email to support@sipeed.com for business cooperation or leave messge in this page for help.
+Email to support@sipeed.com for business cooperation or leave message on this page for help.

docs/hardware/en/lichee/RV/RV.md

@@ -3,7 +3,7 @@
 > Edit on 2022.05.13
 
 ## Overview
-Lichee RV - Nezha CM is a compute module with modular design, equipped with Allwinner D1 chip (based on T-Head XuanTie C906 core), 512MB DDR3 RAM. It can boot from TF card or SD-NAND, uses two sets of M.2 b key 67 pin connectors to route all IO, making it convient for wide use and easy to replace.
+Lichee RV - Nezha CM is a compute module with modular design, equipped with Allwinner D1 chip (based on T-Head XuanTie C906 core), 512MB DDR3 RAM. It can boot from TF card or SD-NAND, uses two sets of M.2 b key 67 pin connectors to route all IO, making it convenient for wide use and easy to replace.
 
 ![](./../assets/RV/D1-4.jpg)
 
@@ -15,7 +15,7 @@ Lichee RV - Nezha CM is a compute module with modular design, equipped with Allw
 | -------------------- | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
 | CPU                  | Allwinner D1 chip (Based on T-Head XuanTie C906 core) up to 1GHZ                                                                                                                                                                  |
 | RAM                  | 16bits 512MB DDR3，Up to 792MHz                                                                                                                                                                                                   |
-| Storge               | Onboard TF card slot，can use tf card for storing,1TB storage capacity have been tested ok <br>Reserve SD-NAND pads (Conflict with 8pins lcd interface. using for business custom made )                                                                                    |
+| Storage               | Onboard TF card slot，can use tf card for storing,1TB storage capacity have been tested ok <br>Reserve SD-NAND pads (Conflict with 8pins lcd interface. using for business custom made )                                                                                    |
 | Display              | **MIPI**：4-lane MIPI DSI <br>**RGB**：RGB888 interface(partially multiplexed with DSI) <br>**MCU** : I80 interface<br>**SPI**：Onboard 8pins SPI screen interface，can be used for 1.14 inch screen                              |
 | Audio                | Analog audio headphone output(HPOUT); <br>Analog audio line input(LINEIN); <br>Digital Audio (I2S/SPDIF); <br>Analog microphone interface(MIC3);<br>Digital microphone interface(DMIC);<br>All above pin out to connecting finger |
 | Ethernet             | Pin out RMII/RGMII to connecting finger (Multiplexed with some GPIOs)                                                                                                                                                             |
@@ -25,7 +25,7 @@ Lichee RV - Nezha CM is a compute module with modular design, equipped with Allw
 | Led                  | • A power led <br>• A user led (active high)                                                                                                                                                                                      |
 | PCB                  | 4 layers                                                                                                                                                                                                                          |
 | Fixed<br> way        | Connect the core board and bottom board by two sets of M.2B connecting finger and fasten with a M2 screw                                                                                                                          |
-| Development lanuguge | C/C++, Python, Golang, etc...                                                                                                                                                                                                     |
+| Development language | C/C++, Python, Golang, etc...                                                                                                                                                                                                     |
 | System Mirrors       | Tina Linux (Based on OpenWRT 14.07), Debian, YoC (RTOS )                                                                                                                                                                         |
 
 ![](./../assets/RV/D1-pin.png)

docs/hardware/en/lichee/RV/flash.md

@@ -6,7 +6,7 @@ There are two system images for Lichee RV and they are tina and debian.
 ## Prepare
 
 1. Lichee RV Core board
-2. TF card (It's suggested to use tf card provided by sipeed beacuse other card might fail to burn or fail to boot system)
+2. TF card (It's suggested to use tf card provided by sipeed because other card might fail to burn or fail to boot system)
 3. Burn tool [PhoenixCard](https://dl.sipeed.com/shareURL/LICHEE/D1/Lichee_RV/tool)
 4. System image
    - [Tina](https://dl.sipeed.com/shareURL/LICHEE/D1/Lichee_RV/SDK/image) 
@@ -45,12 +45,12 @@ Follow the steps below to complete burning
 - From `Status bar` marked with ④ to see your progress；If it's red when finishing this means it fails burning, then we should rerun `SD Card Formatter` to format the TF card to increase its success possibility.
 - Click `Close` to close PhoenixCard
 
-> Not each card can successed be burned, if you can't do this we suggest you buy an image card we provide
+> Not each card can successfully be burned, if you can't do this we suggest you buy an image card we provide
 
 Waiting for finishing burning, It will be faster if flashing Tina OS and it will take about 10 minutes if flashing Debian 
 
 ## Run OS
-The username and passward are as follows:
+The username and password are as follows:
 
 - Tina   OS username：`root`   password：`tina`
 

docs/hardware/en/lichee/RV/problems.md

@@ -1,6 +1,6 @@
 ---
 title: Questions&Answers
-keywords: debian, Rv, Problam, apt, img, sipeed
+keywords: debian, Rv, Problem, apt, img, sipeed
 ---
 
 ## Apt trouble
@@ -11,7 +11,7 @@ keywords: debian, Rv, Problam, apt, img, sipeed
 
 This means built-in key expires and need updating manually, here are two ways to download key.
 
- - Doanload from web page：https://packages.debian.org/sid/all/debian-ports-archive-keyring/download
+ - Download from web page：https://packages.debian.org/sid/all/debian-ports-archive-keyring/download
  - wget : `wget http://ftp.cn.debian.org/debian/pool/main/d/debian-ports-archive-keyring/debian-ports-archive-keyring_2022.02.15_all.deb`
   
 Copy downloaded key (usr scp or lrzsz tool) into LicheeRV board, then run following command to update key:
@@ -22,7 +22,7 @@ Then run `sudo apt-get update` to update apt.
 
 ## Not work
 
-- Make sure you choose as what is shown below when burnning card by yourself
+- Make sure you choose as what is shown below when burning card by yourself
   <details>
   <summary><font color="#4F84FF">Click to see burn requirement</font></summary>
 <img src="./../assets/RV/flash.png">
@@ -35,7 +35,7 @@ Then run `sudo apt-get update` to update apt.
 
 ## 86 panel screen no display/ display wrong
 
-Here we need use corresopnding fex file to overwrite the board-level configuration by using following command in linux system 
+Here we need use corresponding fex file to overwrite the board-level configuration by using following command in linux system 
 Download fex file here https://dl.sipeed.com/shareURL/LICHEE/D1/Lichee_RV/SDK/board
 Overwrite command:
 ```bash

docs/hardware/en/lichee/RV/ubuntu.md

@@ -41,7 +41,7 @@ Visit [balenaEtcher](https://www.balena.io/etcher/) to download application. We
 
 ### Flash System
 
-Prepare a SD card over 8G, the card with better performance can have better experienxe.
+Prepare a SD card over 8G, the card with better performance can have better experience.
 
 Connect the TF card with computer by SD card reader or SD card slot in the computer. Here is an example about SD card slot in computer, if your computer dose not have SD card slot, you need the SD card reader.
 
@@ -74,7 +74,7 @@ This will take a bit time, and after finishing this work it will be like as foll
 
 ## Run System
 
-Finishing flashing system and seeing `sucessful` shown in the end, we can connect SD card with this board to start ubuntu.
+Finishing flashing system and seeing `successful` shown in the end, we can connect SD card with this board to start ubuntu.
 
 ![dock_pro_ubuntu](./../../../zh/lichee/assets/RV/ubuntu/dock_pro_ubuntu.jpg)
 

docs/hardware/en/lichee/RV/user.md

@@ -16,7 +16,7 @@ It may run slow because of the speed of TF card.
 
 The users name is `root` and password is `licheepi`
 
-**When using serial port connets board it always print kernel message, do following steps to stop it:**
+**When using serial port connection board it always print kernel message, do following steps to stop it:**
 - Edit `/etc/rsyslog.conf` by root and change `*.emerg` located in lht last line into `#*.emerg` in this file
 - Restart rsyslog service by this command `/etc/init.d/rsyslog restart`
 

docs/hardware/en/lichee/RV_Nano/3_images.md

@@ -12,4 +12,4 @@ The image is compressed using xz. After decompression, use tools like Rufus, Win
 
 ## Debian Sid Based image
 
-[Image Infomation and Downloads](https://github.com/Fishwaldo/sophgo-sg200x-debian)
+[Image Information and Downloads](https://github.com/Fishwaldo/sophgo-sg200x-debian)

docs/hardware/en/lichee/th1520/lm4a.md

@@ -36,7 +36,7 @@ The LicheePi 4A Module is the Core Module using the [T-Head](https://www.t-head.
 </tr>
 <tr>
   <td>NPU</td>
-  <td>Support 4TOPS@INT8, up to 1GHz <br>· Support TensorFlow、ONNX、Caffe <br>· Support CNN、RNN、DNN </td>
+  <td>Support 4TOPS@INT8, up to 1GHz <br>· Support TensorFlow, ONNX, Caffe <br>· Support CNN, RNN, DNN </td>
 </tr>
 <tr>
   <td>Decode</td>

docs/hardware/en/lichee/th1520/lpi4a/1_intro.md

@@ -81,7 +81,7 @@ For quality contributions to the docs, we offer discount coupons from ¥5 to ¥1
 </tr>
 <tr>
   <td>Storage</td>
-  <td>· eMMC(Optional): None 、 8G、 32G、 128G<br>· Support TF card</td>
+  <td>· eMMC(Optional): None, 8G, 32G, 128G<br>· Support TF card</td>
 </tr>
 <tr>
   <td>Ethernet</td>

docs/hardware/en/lichee/th1520/lpi4a/2_unbox.md

@@ -121,7 +121,7 @@ LicheePi 4A is a high performance SBC，you need to install an active cooler to
     ![silicone_pad](./../../../../zh/lichee/th1520/lpi4a/assets/unbox/silicone_pad.png)
 
 2. Installing the fan / heatsink
-    Allign the 30x30mm heatsink and fan with the thermal pad and press down lightly.
+    Align the 30x30mm heatsink and fan with the thermal pad and press down lightly.
     ![insert_fan](./../../../../zh/lichee/th1520/lpi4a/assets/unbox/insert_fan.png)
 
 3. Connecting the cooling fan
@@ -161,7 +161,7 @@ LicheePi 4A is pre-loaded with a basic system image, so you can try it out direc
 Note: The pre-loaded system image might be very old. After you booted the system for the first time, please have a look at the next section on how to flash / update the image.
 
 Use an HDMI cable (not included) to connect a display (not included) to the HDMI port of LicheePi 4A. Use the supplied USB-C cable to connect the board to a USB power supply (not included) with at least 5V and 2A output.
-The LicheePi 4A will automatically boot into the default image and the login screen should appear within 30 seconds, or automaticly login via sipeed username.
+The LicheePi 4A will automatically boot into the default image and the login screen should appear within 30 seconds, or automatically login via sipeed username.
 
 ![boot_login](./../../../../zh/lichee/th1520/lpi4a/assets/unbox/boot_login.png)
 
@@ -255,7 +255,7 @@ After booting up the board for the first time, let´s take a look at the hardwar
 
 The nominal operating frequency of the TH1520 is 1.85GHz, and we only guarantee that the board you receive can work stably at 1.85GHz.
 If you are an enthusiast you can try to overclock the board to 2GHz, but we don´t guarantee that the board will work stable at this frequency.
-After some testing, about 80% of the boards can boot into the system when overclocked to 2GHz and about 50% of the boards sucessfully pass the stress test at 2GHz.
+After some testing, about 80% of the boards can boot into the system when overclocked to 2GHz and about 50% of the boards successfully pass the stress test at 2GHz.
 
 ### USB Power Limitation
 

docs/hardware/en/lichee/th1520/lpi4a/4_burn_image.md

@@ -23,7 +23,7 @@ The following burning method takes Debian single-screen image `LPI4A_20230721.zi
 
 ### Get the burning tool
 The burning tool can be obtained from the Mega cloud disk and is found in the `burn_tool.zip` file.
-After decompresseion the fastboot binary is found in the win/linux/mac subfolders.
+After decompression the fastboot binary is found in the win/linux/mac subfolders.
 **Note:** Images from 20231023 and later versions have added support for burning large image files, which require using the latest version of fastboot. You can find the latest version of fastboot in the [cloud disk link](https://mega.nz/folder/phoQlBTZ#cZeQ3qZ__pDvP94PT3_bGA). The file name is `burn_tools_support_bigimage.zip`.
 
 ## How to enter burning mode

docs/hardware/en/maix/m1s/m1s_module.md

@@ -299,7 +299,7 @@ Visit Schematic for details：[Click me](https://dl.sipeed.com/shareURL/MAIX/M1s
 <tr>
   <td rowspan="4">Pooling</td>
   <td rowspan="2">MaxPool (NPU TBD)</td>
-  <td>Kerenl: 2x2</td>
+  <td>Kernel: 2x2</td>
   <td rowspan="2">DSP</td>
 </tr>
 <tr>
@@ -307,7 +307,7 @@ Visit Schematic for details：[Click me](https://dl.sipeed.com/shareURL/MAIX/M1s
 </tr>
 <tr>
   <td rowspan="2">MaxPool</td>
-  <td>Kerenl: 3x3</td>
+  <td>Kernel: 3x3</td>
   <td rowspan="2">:strong:<code>NPU</code></td>
 </tr>
 <tr>

docs/hardware/en/maix/m1s/other/others.md

@@ -86,7 +86,7 @@ The camera can be assembled in two directions: the camera shooting direction is
     <tr>
         <td>Rotate the shell to make the TF card slot on the board is in the same direction as the SiPEED logo on the shell</td>
         <td>Align the two TypeC ports with the holes in the shell to prepare for inserting the board into the shell</td>
-        <td>Press where the arrow points at, it's a bit difficult for first time inserting, make sure the two TypeC ports align with the holes. Inster board into the shell</td>
+        <td>Press where the arrow points at, it's a bit difficult for first time inserting, make sure the two TypeC ports align with the holes. Insert board into the shell</td>
     </tr>
     <tr>
         <td><img alt="insert_screen_direction_1" src="./../../../../zh/maix/m1s/other/assets/others/insert_screen_direction_1.jpg" ></td>
@@ -136,7 +136,7 @@ Up to now we have finished installing shell.
 <table>
     <tr>
         <td>Align the two TypeC ports with the holes in the shell to prepare for inserting the board into the shell</td>
-        <td>Press where the arrow points at, it's a bit difficult for first time inserting, make sure the two TypeC ports align with the holes. Inster board into the shell</td>
+        <td>Press where the arrow points at, it's a bit difficult for first time inserting, make sure the two TypeC ports align with the holes. Insert board into the shell</td>
     </tr>
     <tr>
         <td><img alt="insert_screen_direction_2" src="./../../../../zh/maix/m1s/other/assets/others/insert_screen_direction_2.jpg" ></td>

docs/hardware/en/maix/m1s/other/questions.md

@@ -11,5 +11,5 @@ update:
 
 ## c906_app/build_out/xxxxx/.map:No such file or directory
 
-When compiling your firmware, make sure your command is `./build.sh demo_name`, like  `./build.sh hello_world`, not `./build.sh hello_world/` (pay atention to the end symbol `/`)
+When compiling your firmware, make sure your command is `./build.sh demo_name`, like  `./build.sh hello_world`, not `./build.sh hello_world/` (pay attention to the end symbol `/`)
 

docs/hardware/en/maix/m1s/other/start.md

@@ -178,7 +178,7 @@ We mainly use `BLDevCube`, `BLDevCube-macos` and `BLDevCube-ubuntu` these three
 
 ![application](./../../../../zh/maix/m1s/other/assets/start/application.png)
 
-And there are `bflb_iot_tool`、`bflb_iot_tool-macos`、`bflb_iot_tool-ubuntu` three applications, with which we can burn this board via commad line.
+And there are `bflb_iot_tool`、`bflb_iot_tool-macos`、`bflb_iot_tool-ubuntu` three applications, with which we can burn this board via command line.
 
 #### Burn via graphical interface
 
@@ -201,9 +201,9 @@ The firmware file for E907 or C906 can be gotten by compiling [M1s_dock example]
 
 First time burning, both `firmware` and `boot2` are needed, after this you just need tick what you want to burn not all.
 
-The default old firmware can be downloaded [here](https://dl.sipeed.com/shareURL/MAIX/M1s/M1s_Dock/7_Firmware/factory), and the newest firmware is not frovided any more. [Click me](https://wiki.sipeed.com/hardware/en/maix/m1s/other/start.html#Old-firmware-test) to see the old factory firmware details.
+The default old firmware can be downloaded [here](https://dl.sipeed.com/shareURL/MAIX/M1s/M1s_Dock/7_Firmware/factory), and the newest firmware is not provided any more. [Click me](https://wiki.sipeed.com/hardware/en/maix/m1s/other/start.html#Old-firmware-test) to see the old factory firmware details.
 
-After choose the firmware, click the `Refresh` in the righr to refresh the serial port, then we can see 2 serial ports. If there are not 2 serial ports, visit [Burn onboard bl702](https://wiki.sipeed.com/hardware/en/maix/m1s/other/start.html#Burn-onboard-bl702) to solve this. We choose the bigger number serial port, and set uartrate 2000000 .
+After choose the firmware, click the `Refresh` in the righr to refresh the serial port, then we can see 2 serial ports. If there are not 2 serial ports, visit [Burn onboard bl702](https://wiki.sipeed.com/hardware/en/maix/m1s/other/start.html#Burn-onboard-bl702) to solve this. We choose the bigger number serial port, and set uart rate 2000000 .
 
 ![burn_steps](./../../../../zh/maix/m1s/other/assets/start/burn_steps.png)
 
@@ -242,7 +242,7 @@ Of course, make sure you have made this board into UART burning mode: Press BOOT
 
 ![command_burn_flash](./../../../../zh/maix/m1s/other/assets/start/command_burn_flash.jpg)
 
-After burning these, you can burn the bin file for C906 core according to [Burn via u-disk](https://wiki.sipeed.com/hardware/en/maix/m1s/other/start.html#Burn-via-u-disk). You can also burn this board based on the adderss, from `partition_cfg_16M_m1sdock.toml` file you can know the burn address and modify it.
+After burning these, you can burn the bin file for C906 core according to [Burn via u-disk](https://wiki.sipeed.com/hardware/en/maix/m1s/other/start.html#Burn-via-u-disk). You can also burn this board based on the address, from `partition_cfg_16M_m1sdock.toml` file you can know the burn address and modify it.
 
 ### Troubles when burning
 
@@ -353,7 +353,7 @@ M1s can be compiled in Linux.
 
 ### Preparation
 
-We need `git` to get the SDK complie envorioument, and use `make` to compile SDK, `tree` is also need to be installed to check the directory structure.
+We need `git` to get the SDK compile environment, and use `make` to compile SDK, `tree` is also need to be installed to check the directory structure.
 
 The following command can be used in debian Linux distribution like Ubuntu to install the three softwares mentioned above.
 
@@ -435,7 +435,7 @@ sipeed@DESKTOP:~$ tree -L 2
 
 ### Set toolchain path
 
-Everytime compling for M1s, we need to set toolchain path once.
+Every time compiling for M1s, we need to set toolchain path once.
 
 First we need to know the path of `M1s_BL808_SDK`:
 
@@ -445,7 +445,7 @@ sipeed@DESKTOP:~/M1s_BL808_SDK$ pwd
 /home/lee/bl808/M1s_BL808_SDK
 ```
 
-We copy the result (the result of everyone is different) of `pwd` command, then run following commamd to set toolchain path.
+We copy the result (the result of everyone is different) of `pwd` command, then run following command to set toolchain path.
 
 ```bash
 export BL_SDK_PATH=/home/lee/bl808/M1s_BL808_SDK
@@ -506,7 +506,7 @@ Then the compiled bin file is in M1s_BL808_example/e907_app/build_out folder, an
 
 2. Failed compiling
 
-When compiling your firmware, make sure your command is `./build.sh demo_name`, like  `./build.sh hello_world`, not `./build.sh hello_world/` (pay atention to the end symbol `/`)
+When compiling your firmware, make sure your command is `./build.sh demo_name`, like  `./build.sh hello_world`, not `./build.sh hello_world/` (pay attention to the end symbol `/`)
 
 ## WIFI stream DEMO
 

docs/hardware/en/maix/modules_spmod/spmod_bt.md

@@ -175,5 +175,5 @@ SPMOD-BT(Bluetooth module) uses YDJ-23.
 | Sipeed model shop | [https://maixhub.com/](https://maixhub.com/) |
 | SDK Relevant information | [dl.sipeed.com/MAIX/SDK](dl.sipeed.com/MAIX/SDK) |
 | HDK Relevant information | [dl.sipeed.com/MAIX/HDK](dl.sipeed.com/MAIX/HDK) |
-| E-mail(Technical Support and Business Cooperation) | [Support@sipeed.com](mailto:support@sipeed.com) |
+| E-mail(Technical Support and Business Cooperation) | [support@sipeed.com](mailto:support@sipeed.com) |
-| telgram link | [https://t.me/sipeed](https://t.me/sipeed) |
+| Telegram link | [https://t.me/sipeed](https://t.me/sipeed) |

docs/hardware/en/maix/modules_spmod/spmod_eink.md

@@ -229,7 +229,7 @@ The following parameters need to be modified
 | Sipeed model shop | [https://maixhub.com/](https://maixhub.com/) |
 | SDK Relevant information | [dl.sipeed.com/MAIX/SDK](dl.sipeed.com/MAIX/SDK) |
 | HDK Relevant information | [dl.sipeed.com/MAIX/HDK](dl.sipeed.com/MAIX/HDK) |
-| E-mail(Technical Support and Business Cooperation) | [Support@sipeed.com](mailto:support@sipeed.com) |
+| E-mail(Technical Support and Business Cooperation) | [support@sipeed.com](mailto:support@sipeed.com) |
-| telgram link | [https://t.me/sipeed](https://t.me/sipeed)  |
+| Telgram link | [https://t.me/sipeed](https://t.me/sipeed)  |
 
 

docs/hardware/en/maix/modules_spmod/spmod_ethernet.md

@@ -75,5 +75,5 @@ SPMOD_Ethernet(Ethernet module) uses W5500 chip.
 | Sipeed model shop | [https://maixhub.com/](https://maixhub.com/) |
 | SDK Relevant information | [dl.sipeed.com/MAIX/SDK](dl.sipeed.com/MAIX/SDK) |
 | HDK Relevant information | [dl.sipeed.com/MAIX/HDK](dl.sipeed.com/MAIX/HDK) |
-| E-mail(Technical Support and Business Cooperation) | [Support@sipeed.com](mailto:support@sipeed.com) |
+| E-mail(Technical Support and Business Cooperation) | [support@sipeed.com](mailto:support@sipeed.com) |
-| telgram link | [https://t.me/sipeed](https://t.me/sipeed)  |
+| telegram link | [https://t.me/sipeed](https://t.me/sipeed)  |

docs/hardware/en/maix/modules_spmod/spmod_extender.md

@@ -18,9 +18,9 @@ SPMOD_Extender(8PIN SP-MOD Expander)
 
 | Features: | --- |
 | --- | -- |
-| Two-wire SP-MOD interface*3 | Connect to the D0 and D1 on the SP-MOD，Used as UART interface (Connect at most one device)
+| Two-wire SP-MOD interface*3 | Connect to the D0 and D1 on the SP-MOD, Used as UART interface (Connect at most one device)
-or I2C interface(Connect at most three device) , can also be used as two independent GPIO |
+or I2C interface(Connect at most three device), can also be used as two independent GPIO |
-| Four-wire SP-MOD interface |  Connect to the D2-D5 on the SP-MOD，Uusually used as SPI interface，
+| Four-wire SP-MOD interface |  Connect to the D2-D5 on the SP-MOD, Usually used as SPI interface,
 can also be used as four independent GPIO |
 | Supply voltage of external power supply | Depends on connected modules |
 | Supply current of external power supply | Depends on the working conditions of the module, usually less than 1000mA |
@@ -46,5 +46,5 @@ can also be used as four independent GPIO |
 | Sipeed model shop | [https://maixhub.com/](https://maixhub.com/) |
 | SDK Relevant information | [dl.sipeed.com/MAIX/SDK](dl.sipeed.com/MAIX/SDK) |
 | HDK Relevant information | [dl.sipeed.com/MAIX/HDK](dl.sipeed.com/MAIX/HDK) |
-| E-mail(Technical Support and Business Cooperation) | [Support@sipeed.com](mailto:support@sipeed.com) |
+| E-mail(Technical Support and Business Cooperation) | [support@sipeed.com](mailto:support@sipeed.com) |
-| telgram link | [https://t.me/sipeed](https://t.me/sipeed) |
+| Telegram link | [https://t.me/sipeed](https://t.me/sipeed) |

docs/hardware/en/maix/modules_spmod/spmod_fpc.md

@@ -10,7 +10,7 @@ SPMOD_FPC( SPMOD extension module )
 
 ## SPMOD - FPC Introduction
 
-- Using **Sipeed-SPMOD** interface(2.54mm * 8PIN )，unified MaixPy board interface
+- Using **Sipeed-SPMOD** interface(2.54mm * 8PIN ), unified MaixPy board interface
 - As an extension module, easily extend the SP-MOD interface with FPC.
 - Provide a pair of SP-MOD to FPC adapters(Male and female), one FPC cable(10P).
 - Size:15.0\*10.0\*3.3mm
@@ -45,5 +45,5 @@ SPMOD_FPC( SPMOD extension module )
 | Sipeed model shop | [https://maixhub.com/](https://maixhub.com/) |
 | SDK Relevant information | [dl.sipeed.com/MAIX/SDK](dl.sipeed.com/MAIX/SDK) |
 | HDK Relevant information | [dl.sipeed.com/MAIX/HDK](dl.sipeed.com/MAIX/HDK) |
-| E-mail(Technical Support and Business Cooperation) | [Support@sipeed.com](mailto:support@sipeed.com) |
+| E-mail(Technical Support and Business Cooperation) | [support@sipeed.com](mailto:support@sipeed.com) |
-| telgram link | [https://t.me/sipeed](https://t.me/sipeed) |
+| Telegram link | [https://t.me/sipeed](https://t.me/sipeed) |

docs/hardware/en/maix/modules_spmod/spmod_grove.md

@@ -11,7 +11,7 @@ SPMOD_Grove(GROVE module)
 ## SPMOD - Grove Introduction
 
 - Using **Sipeed-SPMOD** interface(2.54mm * 8PIN )，unified MaixPy board interface
-- Ass an Expansion board，it povides three standard Grove interfaces.
+- Ass an Expansion board, it povides three standard Grove interfaces.
 - All data cables are provide external pull-ups.
 - The power supply can handle up to 1000mA
 - Size:35.0\*10.0\*2.1mm
@@ -45,5 +45,5 @@ SPMOD_Grove(GROVE module)
 | Sipeed model shop | [https://maixhub.com/](https://maixhub.com/) |
 | SDK Relevant information | [dl.sipeed.com/MAIX/SDK](dl.sipeed.com/MAIX/SDK) |
 | HDK Relevant information | [dl.sipeed.com/MAIX/HDK](dl.sipeed.com/MAIX/HDK) |
-| E-mail(Technical Support and Business Cooperation) | [Support@sipeed.com](mailto:support@sipeed.com) |
+| E-mail(Technical Support and Business Cooperation) | [support@sipeed.com](mailto:support@sipeed.com) |
-| telgram link | [https://t.me/sipeed](https://t.me/sipeed) |
+| Telegram link | [https://t.me/sipeed](https://t.me/sipeed) |

docs/hardware/en/maix/modules_spmod/spmod_joystick.md

@@ -56,5 +56,5 @@ SPMOD_JoyStick (JoyStick module).
 | Sipeed model shop | [https://maixhub.com/](https://maixhub.com/) |
 | SDK Relevant information | [dl.sipeed.com/MAIX/SDK](dl.sipeed.com/MAIX/SDK) |
 | HDK Relevant information | [dl.sipeed.com/MAIX/HDK](dl.sipeed.com/MAIX/HDK) |
-| E-mail(Technical Support and Business Cooperation) | [Support@sipeed.com](mailto:support@sipeed.com) |
+| E-mail(Technical Support and Business Cooperation) | [support@sipeed.com](mailto:support@sipeed.com) |
-| telgram link | [https://t.me/sipeed](https://t.me/sipeed) |
+| Telegram link | [https://t.me/sipeed](https://t.me/sipeed) |

docs/hardware/en/maix/modules_spmod/spmod_lcd1.14.md

@@ -10,7 +10,7 @@ SPMOD_LCD1.14(1.14 inch LCD) uses ST7735S TFT LCD.
 ## SPMOD - LCD1.14 Introduction
 
 - Using **Sipeed-SPMOD** interface(2.54mm * 8PIN )，unified MaixPy board interface
-- Using commom LCD driver IC ST7735S(4-wire SPI communicate)
+- Using common LCD driver IC ST7735S(4-wire SPI communicate)
 - Display Resolution:240\*135
 - Size:35.0\*20.0mm
 
@@ -214,5 +214,5 @@ The following parameters need to be modified.
 | Sipeed model shop | [https://maixhub.com/](https://maixhub.com/) |
 | SDK Relevant information | [dl.sipeed.com/MAIX/SDK](dl.sipeed.com/MAIX/SDK) |
 | HDK Relevant information | [dl.sipeed.com/MAIX/HDK](dl.sipeed.com/MAIX/HDK) |
-| E-mail(Technical Support and Business Cooperation) | [Support@sipeed.com](mailto:support@sipeed.com) |
+| E-mail(Technical Support and Business Cooperation) | [support@sipeed.com](mailto:support@sipeed.com) |
-| telgram link | [https://t.me/sipeed](https://t.me/sipeed) |
+| Telegram link | [https://t.me/sipeed](https://t.me/sipeed) |

docs/hardware/en/maix/modules_spmod/spmod_lora.md

@@ -208,5 +208,5 @@ The following parameters need to be modified
 | Sipeed model shop | [https://maixhub.com/](https://maixhub.com/) |
 | SDK Relevant information | [dl.sipeed.com/MAIX/SDK](dl.sipeed.com/MAIX/SDK) |
 | HDK Relevant information | [dl.sipeed.com/MAIX/HDK](dl.sipeed.com/MAIX/HDK) |
-| E-mail(Technical Support and Business Cooperation) | [Support@sipeed.com](mailto:support@sipeed.com) |
+| E-mail(Technical Support and Business Cooperation) | [support@sipeed.com](mailto:support@sipeed.com) |
-| telgram link | [https://t.me/sipeed](https://t.me/sipeed) |
+| Telegram link | [https://t.me/sipeed](https://t.me/sipeed) |

docs/hardware/en/maix/modules_spmod/spmod_micarray.md

@@ -69,5 +69,5 @@ Thermal Shutdown,Integrated 80mΩ Power MOSFET
 | Sipeed model shop | [https://maixhub.com/](https://maixhub.com/) |
 | SDK Relevant information | [dl.sipeed.com/MAIX/SDK](dl.sipeed.com/MAIX/SDK) |
 | HDK Relevant information | [dl.sipeed.com/MAIX/HDK](dl.sipeed.com/MAIX/HDK) |
-| E-mail(Technical Support and Business Cooperation) | [Support@sipeed.com](mailto:support@sipeed.com) |
+| E-mail(Technical Support and Business Cooperation) | [support@sipeed.com](mailto:support@sipeed.com) |
-| telgram link | [https://t.me/sipeed](https://t.me/sipeed) |
+| Telegram link | [https://t.me/sipeed](https://t.me/sipeed) |

docs/hardware/en/maix/modules_spmod/spmod_psram.md

@@ -32,7 +32,7 @@ SPMOD_PSRAM(PSRAM module) uses IPS6404L-SQ PSRAM.
 
 ###  SPMOD_PSRAM pin description:
 
-| Pin  | Name | Type  | Decription    |
+| Pin  | Name | Type  | Description    |
 | -------- | -------- | ---- | ---------- |
 | 1 | GND  | G | Ground |
 | 2 | CS | I  | Chip Select input pin |
@@ -70,5 +70,5 @@ SPMOD_PSRAM(PSRAM module) uses IPS6404L-SQ PSRAM.
 | Sipeed model shop | [https://maixhub.com/](https://maixhub.com/) |
 | SDK Relevant information | [dl.sipeed.com/MAIX/SDK](dl.sipeed.com/MAIX/SDK) |
 | HDK Relevant information | [dl.sipeed.com/MAIX/HDK](dl.sipeed.com/MAIX/HDK) |
-| E-mail(Technical Support and Business Cooperation) | [Support@sipeed.com](mailto:support@sipeed.com) |
+| E-mail(Technical Support and Business Cooperation) | [support@sipeed.com](mailto:support@sipeed.com) |
-| telgram link | [https://t.me/sipeed](https://t.me/sipeed) |
+| Telegram link | [https://t.me/sipeed](https://t.me/sipeed) |

docs/hardware/en/maix/modules_spmod/spmod_rfid.md

@@ -198,5 +198,5 @@ The following parameters need to be modified
 | Sipeed model shop | [https://maixhub.com/](https://maixhub.com/) |
 | SDK Relevant information | [dl.sipeed.com/MAIX/SDK](dl.sipeed.com/MAIX/SDK) |
 | HDK Relevant information | [dl.sipeed.com/MAIX/HDK](dl.sipeed.com/MAIX/HDK) |
-| E-mail(Technical Support and Business Cooperation) | [Support@sipeed.com](mailto:support@sipeed.com) |
+| E-mail(Technical Support and Business Cooperation) | [support@sipeed.com](mailto:support@sipeed.com) |
-| telgram link | [https://t.me/sipeed](https://t.me/sipeed) |
+| Telegram link | [https://t.me/sipeed](https://t.me/sipeed) |

docs/hardware/en/maix/modules_spmod/spmod_servo.md

@@ -53,5 +53,5 @@ SPMOD_SERVO (SERVO module).
 | Sipeed model shop | [https://maixhub.com/](https://maixhub.com/) |
 | SDK Relevant information | [dl.sipeed.com/MAIX/SDK](dl.sipeed.com/MAIX/SDK) |
 | HDK Relevant information | [dl.sipeed.com/MAIX/HDK](dl.sipeed.com/MAIX/HDK) |
-| E-mail(Technical Support and Business Cooperation) | [Support@sipeed.com](mailto:support@sipeed.com) |
+| E-mail(Technical Support and Business Cooperation) | [support@sipeed.com](mailto:support@sipeed.com) |
-| telgram link | [https://t.me/sipeed](https://t.me/sipeed) |
+| Telegram link | [https://t.me/sipeed](https://t.me/sipeed) |

docs/hardware/en/maix/modules_spmod/spmod_tof.md

@@ -65,7 +65,7 @@ SPMOD_TOF(TOF module) uses VL53L0X .
 
 * Process
 
-  1. Initializatin
+  1. Initialization
   2. Adjust(option)
   3. Get distance
 
@@ -143,7 +143,7 @@ Modify the following parameters to fit other K210 boards.
 ```c
   // board_config.h
   #define VL53L0X_I2C_DEVICE 0 // i2c device number
-  #define VL53L0X_I2C_FREQ_KHZ 100 // i2c frequence
+  #define VL53L0X_I2C_FREQ_KHZ 100 // i2c frequency
   #define VL53L0X_SCL 6 // scl
   #define VL53L0X_SDA 7 // sda
   #define VL53L0X_SHT 8 // sht
@@ -181,5 +181,5 @@ Modify the following parameters to fit other K210 boards.
 | Sipeed model shop | [https://maixhub.com/](https://maixhub.com/) |
 | SDK Relevant information | [dl.sipeed.com/MAIX/SDK](dl.sipeed.com/MAIX/SDK) |
 | HDK Relevant information | [dl.sipeed.com/MAIX/HDK](dl.sipeed.com/MAIX/HDK) |
-| E-mail(Technical Support and Business Cooperation) | [Support@sipeed.com](mailto:support@sipeed.com) |
+| E-mail(Technical Support and Business Cooperation) | [support@sipeed.com](mailto:support@sipeed.com) |
-| telgram link | [https://t.me/sipeed](https://t.me/sipeed) |
+| Telegram link | [https://t.me/sipeed](https://t.me/sipeed) |

docs/hardware/en/maix/modules_spmod/spmod_weather.md

@@ -150,5 +150,5 @@ low power consumption (75uA).
 | Sipeed model shop | [https://maixhub.com/](https://maixhub.com/) |
 | SDK Relevant information | [dl.sipeed.com/MAIX/SDK](dl.sipeed.com/MAIX/SDK) |
 | HDK Relevant information | [dl.sipeed.com/MAIX/HDK](dl.sipeed.com/MAIX/HDK) |
-| E-mail(Technical Support and Business Cooperation) | [Support@sipeed.com](mailto:support@sipeed.com) |
+| E-mail(Technical Support and Business Cooperation) | [support@sipeed.com](mailto:support@sipeed.com) |
-| telgram link | [https://t.me/sipeed](https://t.me/sipeed) |
+| Telegram link | [https://t.me/sipeed](https://t.me/sipeed) |

docs/hardware/en/maixII/M2/flash.md

@@ -35,7 +35,7 @@ Only bussiness edition M2 model contains the Flash, so we need to start the syst
 
 ### Preparation
 
-- Get burnning tool [PhoenixCard](https://dl.sipeed.com/shareURL/MaixII/MaixII-Dock/SDK/tools)
+- Get burning tool [PhoenixCard](https://dl.sipeed.com/shareURL/MaixII/MaixII-Dock/SDK/tools)
 - Get [image file](https://dl.sipeed.com/shareURL/MaixII/MaixII-Dock/SDK/release)
 - Get SD card Formatter Tool [SD Card Formatter](https://www.sdcard.org/downloads/formatter/eula_windows/SDCardFormatterv5_WinEN.zip)
 

docs/hardware/en/maixII/M2/other.md

@@ -66,7 +66,7 @@ The rule of dtb file name is shown as following:
 | sipeed_1.3_240x240_vs3205.dtb | 1.3 inch | vs3205 |
 | sipeed_1.3_240x240_sp2305.dtb | 1.3 inch | sp2305 |
 
-Copy the compiled dtb file into the virtual U-disk, then run following commmand in adb shell.
+Copy the compiled dtb file into the virtual U-disk, then run following command in adb shell.
 
 ```bash
 sync  #Refresh contents
@@ -76,7 +76,7 @@ reboot #Restart to apply
 
 Then we succeed changing device tree. 
 
-- If your screen displays incorrectly, this means you choose wrond dtb file, just reupdate it to fix this.
+- If your screen displays incorrectly, this means you choose wrong dtb file, just reupdate it to fix this.
 
 Here is a correct display picture. 
 

docs/hardware/en/maixII/M2/resources.md

@@ -4,10 +4,10 @@ keywords: MaixII, MaixPy3, Python, Python3, M2dock
 desc: maixpy  Onboard resources
 ---
 
-Maix-II-Dock is positioned as a cost-effective AIOT development board. While supporting conventional Linux development, it also has a unique AI hardware acceleration feature. With the complete software ecosystem provided by Sipeed, you can quickly realize your edge AI application.
+Maix-II-Dock is positioned as a cost-effective AIoT development board. While supporting conventional Linux development, it also has a unique AI hardware acceleration feature. With the complete software ecosystem provided by Sipeed, you can quickly realize your edge AI application.
 
 * **Hardware**, based on the Allwinner V831 chip, the development board is formed in the form of [core board] + [ext-board]. You can use the development board directly, or you can use only the core board to design your own ext-board according to your needs, which is convenient and fast to complete the development.
-* **Software**, in addition to directly using the datasheet provided by Allwinner for development (some satasheet may need to be obtained from Allwinner), Sipeed provides a very convenient Python SDK ([MaixPy3](/maixpy3)) and C SDK ([libmaix](https://github.com/sipeed/libmaix)). It also provides an online model training service ([MaixHub](https://maixhub.com), which is more convenient for beginners to quickly train their usable AI models.
+* **Software**, in addition to directly using the datasheet provided by Allwinner for development (some datasheet may need to be obtained from Allwinner), Sipeed provides a very convenient Python SDK ([MaixPy3](/maixpy3)) and C SDK ([libmaix](https://github.com/sipeed/libmaix)). It also provides an online model training service ([MaixHub](https://maixhub.com), which is more convenient for beginners to quickly train their usable AI models.
 * **Purchase**: [sipeed.aliexpress.com](https://www.aliexpress.com/item/1005002538932487.html)
 
 <p align="center">
@@ -67,14 +67,14 @@ Normally we think the screen panel is the front and camera is back.
 
 | Number | Maix II Part                       | Function                                              | Note                                                             |
 | ------ | ---------------------------------- | ----------------------------------------------------- | ---------------------------------------------------------------- |
-| 1      | M.2 B-KEY female slot*1            | Used for connect V831 core board                      | Have connectted with core board when sold                        |
+| 1      | M.2 B-KEY female slot*1            | Used for connect V831 core board                      | Have connected with core board when sold                        |
 | 2      | Core board M2 copper column nuts*1 | Fix core board with bottom board                      | Have been fixed when sold                                        |
 | 3      | Power LED*1                        | Show power state                                      | ---                                                              |
 | 4      | State LED*1                        | User programmable led                                 | ---                                                              |
 | 5      | CPU Reset button*1                 | Reset V831 chip                                       | ---                                                              |
-| 6      | User button*2                      | Change IO voltage value，custome usage                | ---                                                              |
+| 6      | User button*2                      | Change IO voltage value，custom usage                 | ---                                                              |
 | 7      | Wi-Fi module*1                     | RTL8189FTV，adds Wi-Fi function for this board        | SDIO Interface                                                   |
-| 8      | BTB camera interface*1             | Connect BTB camera module                             | Have connectted with bottom board when sold                      |
+| 8      | BTB camera interface*1             | Connect BTB camera module                             | Have connected with bottom board when sold                       |
 | 9      | Camera M2 copper column nuts*2     | Fix BTB camera with bottom board                      | Have been fixed when sold                                        |
 | 10     | FHD camera*1                       | Default SP2305 Sensor BTB style, 1080P                | Default 6mm focal length M12 lens，can use other Suitable camera |
 | 11     | USB to UART chip*1                 | Provide serial port communication                     | ---                                                              |
@@ -83,11 +83,11 @@ Normally we think the screen panel is the front and camera is back.
 | 14     | Three-axis accelerometer*1         | I2C interface，can read 3 axes acceleration data      | ---                                                              |
 | 15     | MicroSD card slot*1                | Connect microSD card                                  | Default boot from SD card                                        |
 | 16     | LCD interface*1                    | FPC0.5mm 24Pin，MCU interface                         |                                                                  |
-| 17     | IPS HD screen\*1                   | 1.3 inch IPS screen，resolution 240\*240              | Have connectted with core board when sold                        |
+| 17     | IPS HD screen\*1                   | 1.3 inch IPS screen，resolution 240\*240              | Have connected with core board when sold                         |
 | 18     | IPEX Wi-Fi antenna connector       | IPEX(first generation) Wi-Fi antenna                  | ---                                                              |
 | 19     | Extension female header            | Route V831 general IO，used for connecting peripheral | ---                                                              |
 | 20     | Speaker connector*1                | MX1.25 2P interface（1.25mm pitch）                   | ---                                                              |
-| 21     | Loudspeaker*1                      | 8Ω1W 1609 composite aluminum membrane speakers        | Have connectted with core board when sold                        |
+| 21     | Loudspeaker*1                      | 8Ω1W 1609 composite aluminum membrane speakers        | Have connected with core board when sold                         |
 | 22     | Microphone*1                       | Analog electret microphone                            | ---                                                              |
 
 ## Resource summary

docs/hardware/en/maixII/M2/usage.md

@@ -4,7 +4,7 @@ keywords: MaixII, MaixPy3, Python, Python3, M2dock, Tina, Openwrt
 desc: maixpy  MaixII M2dock start to use
 ---
 
-## Introduct openwrt
+## Introduction openwrt
 
 > Allwinnner V831 use Tina Linux, which is created from [OpenWrt](https://openwrt.org).
 
@@ -25,7 +25,7 @@ Because of the change of different system image, the ways to connect to wireless
 
 ### V0.5.4
 
-In this system version, we remove the way to connect wireless network by editting `wpa_supplicant.conf` file of the u-disk, and we use commands to connect wireless network.
+In this system version, we remove the way to connect wireless network by editing `wpa_supplicant.conf` file of the u-disk, and we use commands to connect wireless network.
 
 We can see there are many linux commands about wifi in this system.
 
@@ -43,7 +43,7 @@ Change `Sipeed_Guest` into your target wireless network name and change `qwert12
 
 ![wifi_test_connect_wireless](./../../../zh/maixII/M2/asserts/usage/wifi_test_connect_wireless.jpg)
 
-From the connection message, we can see `192.168.3.158`, this is the IP address of M2Dock in this network enviroment.
+From the connection message, we can see `192.168.3.158`, this is the IP address of M2Dock in this network environment.
 
 We can run `ifconfig` on M2Dock to see the ip address, from which we see that the ip address is the same as the wireless network connection message.
 
@@ -77,7 +77,7 @@ Do Not Do Any Operation When Updating.
 
 The opkg utility is the lightweight package manager used for upgrading the functionality of the system rather significantly by downloading and installing pre-made packages from package repositories.
 
-#### Related commom commands
+#### Related common commands
 
 - opkg update # Update the updatable utility
 - opkg upgrade # Upgrade the upgradable utility
@@ -182,4 +182,4 @@ We suggest you use [Maixpy3](/maixpy3) to develop , and its English documents wi
 
 ## SDK development
 
-Now we have open V831 source sode here, use this https://github.com/Tina-Linux/tina-V83x if you need. 
+Now we have open V831 source code here, use this https://github.com/Tina-Linux/tina-V83x if you need. 

docs/hardware/en/maixII/M2A/config_system.md

@@ -24,7 +24,7 @@ Click this to download the driver for this serial chip, after installing [ch340
 
 ## Config Tina OS
 
-We suggest beginners use armbian OS because there are many informations about it on internet, and for Tina OS suits those who are good at Linux.
+We suggest beginners use Armbian OS because there is a lot of information about it on the internet, and for Tina OS suits those who are good at Linux.
 
 The Tina OS configuration steps of Lichee MaixSense are similar to [M2dock](./../M2/usage.md), so here will not retell its usages.
 <!-- 
@@ -104,7 +104,7 @@ Create password: *********
 Repeat password: *********
 ```
 
-The new creater user is granted root permission by default, and we can use this identity to login this board and control this system.
+The new created user is granted root permission by default, and we can use this identity to login this board and control this system.
 
 We can use command `passwd` to change the password or delete the password.
 

docs/hardware/en/maixII/M2A/flash_system.md

@@ -26,7 +26,7 @@ This image file is created by [dd](https://en.wikipedia.org/wiki/Dd_(Unix)). So
 
 ### Tina system image
 
-Tina os need to be compiled by yourself, visit [https://github.com/sipeed/R329-Tina-jishu](https://github.com/sipeed/R329-Tina-jishu) for imformation.
+Tina os need to be compiled by yourself, visit [https://github.com/sipeed/R329-Tina-jishu](https://github.com/sipeed/R329-Tina-jishu) for information.
 
 ## Burn system
 
@@ -42,7 +42,7 @@ Extract your downloaded image file to get the `.img` file, run Etcher, click `Fl
 
 ![burn](./../../maixII/M2A/assets/95133.gif)
 
-If failed burning, try to format your sdcard. For Windows and macos users we suggest use [SD Card Formatter](https://www.sdcard.org/downloads/formatter/eula_windows/SDCardFormatterv5_WinEN.zip "SDCardFormatter") to format sdcard, while for linuc users can try [Gparted](https://gparted.org/).
+If failed burning, try to format your sdcard. For Windows and macos users we suggest use [SD Card Formatter](https://www.sdcard.org/downloads/formatter/eula_windows/SDCardFormatterv5_WinEN.zip "SDCardFormatter") to format sdcard, while for linux users can try [Gparted](https://gparted.org/).
 
 ### Burn Tina image
 

docs/hardware/en/maixII/M2A/maixsense.md

@@ -4,7 +4,7 @@ This board is different from Maix-I series, it's main chip not only incorporates
 
 ## M2A core board
 
-M2A core board use R329 as main chip, and also contains components like power management chip, fel burn key, wifi module, storge pad reserved and RMGII interface.
+M2A core board use R329 as main chip, and also contains components like power management chip, fel burn key, wifi module, storage pad reserved and RMGII interface.
 
 ![M2A](./../../maixII/M2A/assets/M2A.jpg)
 
@@ -34,7 +34,7 @@ R329 is a 64 bits processor designed by Allwinner containing dual Cortex-A53 ins
 
 ### MaixSense 
 
-MaixSense is a really small Linux card computer. Its package contains a SOM based on R329, and a multifunction IO expansion bottom board. Running Linux OS, it can be used for personal server, Intelligent voice assistant or robotis. Because of the AIPU npu core, this board can also be used for intelligent voice and video image processing, and AI model like  CV , NLP can also run on it.
+MaixSense is a really small Linux card computer. Its package contains a SOM based on R329, and a multifunction IO expansion bottom board. Running Linux OS, it can be used for personal server, Intelligent voice assistant or robotics. Because of the AIPU npu core, this board can also be used for intelligent voice and video image processing, and AI model like  CV , NLP can also run on it.
 
 **Tina Linux**：Tina Linux is an embedded system built for intelligent hardware products by Allwinner based on openwrt-14.07. Kernel source code, drivers, toolchain, system middleware and application packages can be found @ [https://github.com/sipeed/r329-linux-4.9](https://github.com/sipeed/r329-linux-4.9)
 
@@ -123,4 +123,4 @@ Camera Port pin：
 
 ## Support
 
-Email to support@sipeed.com for business cooperation or leave messge in this page for help.
+Email to support@sipeed.com for business cooperation or leave message on this page for help.

docs/hardware/en/maixII/M2A/usages.md

@@ -82,7 +82,7 @@ logout
 
 The new created user may need administrator privilege to do finish some work, so here we tell how to grant administrator privilege.
 
-To grant administrator privilege, we just neet to edit a file named `sudoers` in `/etc`.
+To grant administrator privilege, we just need to edit a file named `sudoers` in `/etc`.
 
 ```bash
 sudo nano /etc/sudoers
@@ -103,7 +103,7 @@ root    ALL=(ALL:ALL) ALL
 xxx     ALL=(ALL:ALL) ALL
 ```
 
-Then save this file and quie editing.
+Then save this file and quit editing.
 
 ## Install application
 
@@ -113,7 +113,7 @@ Here we take install `armbian-config` as example, just run following command:
 sudo apt install armbian-config -y
 ```
 
-The above command means to install armbian-config by running the apt application with root privileges and that everything whichi needs to be selected is the yes option
+The above command means to install armbian-config by running the apt application with root privileges and that everything which needs to be selected is the yes option
 
 ## Config Timezone
 
@@ -127,7 +127,7 @@ Just use `armbian-config` to change timezone. Here we take change to Shanghai ti
 
 We also use `armbian-config` to change language. 
 
-Just `armbian-config` -> `Personal` -> `Locales`, and select your target language, then choose the default sustem language.
+Just `armbian-config` -> `Personal` -> `Locales`, and select your target language, then choose the default system language.
 
 Dont't forget to download your language font to avoid wrong display.
 
@@ -357,7 +357,7 @@ After finishing compiling our code, run it.
 
 ## Prepare python code
 
-- See [Program C code](#program-c-code) to get explaination.
+- See [Program C code](#program-c-code) to get explanation.
 
 ```bash
 vim helloworld.py
@@ -453,7 +453,7 @@ echo "hello world!"
 
 Then restart the board.
 
-For example, after editing the auto-start script, it executs before user logs in, and the execution example log is as follows.
+For example, after editing the auto-start script, it executes before user logs in, and the execution example log is as follows.
 
 ```bash
 [  OK  ] Finished Permit User Sessions.

docs/hardware/en/maixIII/ax-pi/axpi.md

@@ -17,7 +17,7 @@ If you think this AI development board are excellent enough and your friends may
 
 In the past few years, many Linux AI chips come out.
 
-Raspberry Pi and Jetson Nano these boards are really popular by their good performance, but now MAIX-III AXera-Pi comes out, equipped with the high-performance 3.6TOPs@INT8 chip ax620a, which will be your good choice and provice you a really good experience.
+Raspberry Pi and Jetson Nano these boards are really popular by their good performance, but now MAIX-III AXera-Pi comes out, equipped with the high-performance 3.6TOPs@INT8 chip ax620a, which will be your good choice and provide you a really good experience.
 
 <p align="center">
 <img src="https://axera-tech.com/upload/8f/091a2540e7cdc5c7f62df022f80220.jpg" alt="img" style="zoom: 50%;" />
@@ -81,7 +81,7 @@ We design a core module for this chip, which is convenient if you want to design
 
 ## Introduction
 
-In WORLD ARTIFICIAL INTELLIGENCE CONFERENCE 2022, this AI board is shown the first tima, like what's in the following picture.
+In WORLD ARTIFICIAL INTELLIGENCE CONFERENCE 2022, this AI board is shown the first time, like what's in the following picture.
 
 <p align="center">
   <img src="./../../../zh/maixIII/assets/waic-axpi.jpg" style="zoom: 70%;" />
@@ -107,7 +107,7 @@ So, why is this AI development board good?
 - High power consumption? Just use one usb cable connecting with USB3.0 port to boot this device, no need of other power supply.
 - Difficult to develop? Compile your own application on this board, or train your own AI model online and deploy it on board.
 - Awful camera image? This chip is aimed for AI ISP night vision enhancement, we have adjust the camera to best state.
-- Too expensive? This board sold about 100$, chiper than any other similar board.
+- Too expensive? This board sold about 100$, cheaper than any other similar board.
 
 ## Special column Documents
 
@@ -264,7 +264,7 @@ Visit [Deploy models to AX-Pi (Maix-III(M3) series) board](/ai/en/deploy/ax-pi.h
 
 ### Tranning model online
 
-Now [MaixHub](https://maixhub.com/welcome) has been upgraded, with more friendly interface and more functions, here are steps to tranning model online.
+Now [MaixHub](https://maixhub.com/welcome) has been upgraded, with more friendly interface and more functions, here are steps to training model online.
 
 <p align="center">
   <img src="./assets/axpi/test_maixhub.jpg" style="zoom: 100%;" />
@@ -334,7 +334,7 @@ BSP development package for business, provided by Axera. It's the original devel
 
 #### [ax-pipeline](https://github.com/AXERA-TECH/ax-pipeline)
 
-AX-Pipeline is provided by Axera. With M3AXPI, this project is used for pepole to know the usages of ISP, image processing, NPU, codec and display, which is convenient for developers to quickly evaluate and develop their own multimedia applications.
+AX-Pipeline is provided by Axera. With M3AXPI, this project is used for people to know the usages of ISP, image processing, NPU, codec and display, which is convenient for developers to quickly evaluate and develop their own multimedia applications.
 
 1. [Quick compilation](https://github.com/AXERA-TECH/ax-pipeline/blob/main/docs/compile.md) Simple cross-platform compilation via cmake.
 2. [How to replace into my own trained yolov5 model](https://github.com/AXERA-TECH/ax-pipeline/blob/main/docs/how_to_deploy_custom_yolov5_model.md)
@@ -461,7 +461,7 @@ AX-Pipeline is provided by Axera. With M3AXPI, this project is used for pepole t
 </tbody>
 </table>
 
-[Hardware summary informations](https://dl.sipeed.com/shareURL/MaixIII/AXera)
+[Hardware summary information](https://dl.sipeed.com/shareURL/MaixIII/AXera)
 
 - [Datasheet](https://dl.sipeed.com/shareURL/MaixIII/AXera/01_Specification)
 - [Schematic](https://dl.sipeed.com/shareURL/MaixIII/AXera/02_Schematic)
@@ -493,4 +493,4 @@ AX-Pipeline is provided by Axera. With M3AXPI, this project is used for pepole t
 - Telegram: https://t.me/sipeed
 - Github: https://github.com/sipeed
 
-> Visit [Maix-III AXera-Pi (FAQ)](https://wiki.sipeed.com/hardware/en/maixIII/ax-pi/faq_axpi.html) if you have trobule.
+> Visit [Maix-III AXera-Pi (FAQ)](https://wiki.sipeed.com/hardware/en/maixIII/ax-pi/faq_axpi.html) if you have any trouble.

docs/hardware/en/maixIII/ax-pi/dev_prepare.md

@@ -23,7 +23,7 @@ Normally our computer have better performance than target embedded linux device,
 
 For example, `ax-sample` takes more than 10 minutes to be compiled on AXera-Pi, but it takes less than one minute on your computer.
 
-Above all, for embedded development, coree-compile technology is commom and it's necessary to know about this if you want to save your time.
+Above all, for embedded development, coree-compile technology is common and it's necessary to know about this if you want to save your time.
 
 ## Transfer files
 
@@ -40,7 +40,7 @@ There are many good SSH application on Windows, here we use [Mobaxterm](https://
 
 ![mobaxterm_transfer_file](./assets/dev_prepare/mobaxterm_transfer_file.jpg)
 
-Besides, [Vscode](https://code.visualstudio.com/) is also a gooe idea for transfering file. Install the [Remote - SSH](https://marketplace.visualstudio.com/items?itemName=ms-vscode-remote.remote-ssh) and [Remote Explorer](https://marketplace.visualstudio.com/items?itemName=ms-vscode.remote-explorer) extensions, then login to AXera-Pi via vscode SSH.
+Besides, [Vscode](https://code.visualstudio.com/) is also a good idea for transferring file. Install the [Remote - SSH](https://marketplace.visualstudio.com/items?itemName=ms-vscode-remote.remote-ssh) and [Remote Explorer](https://marketplace.visualstudio.com/items?itemName=ms-vscode.remote-explorer) extensions, then login to AXera-Pi via vscode SSH.
 
 ![transfer_file_vscode](./assets/flash_system/transfer_file_vscode.jpg)
 
@@ -72,13 +72,13 @@ Windows user can use Mobaxterm to transfer file between computer and AXera-Pi vi
 
 Here we tell how to compile application on AXera-Pi.
 
-Because serial port connector is slow and can be only opened by only one application at one time, we usually login to AXera-Pi by SSH, which we can open many terminals and enter different commands in dirrerent ssh terminal at the same time.
+Because serial port connector is slow and can be only opened by only one application at one time, we usually login to AXera-Pi by SSH, which we can open many terminals and enter different commands in different ssh terminal at the same time.
 
 ![ssh_mutiple_terminals](./assets/dev_prepare/ssh_mutiple_terminals.jpg)
 
 ### Vscode remote
 
-We have told how to login to AXera-Pi via SSH with vscode, login to AXera-Pi by Vscode first, make sure not install [C/C++](https://marketplace.visualstudio.com/items?itemName=ms-vscode.cpptools) extension of vscode on AXera-Pi, this extension may close SSH connnection.
+We have told how to login to AXera-Pi via SSH with vscode, login to AXera-Pi by Vscode first, make sure not install [C/C++](https://marketplace.visualstudio.com/items?itemName=ms-vscode.cpptools) extension of vscode on AXera-Pi, this extension may close SSH connection.
 
 Click ① and ② to open a SSH connection.
 
@@ -128,7 +128,7 @@ Running the commands above, screen displays camera content, use `Ctrl + c` to st
 
 Using Mobaxtern to login AXera-Pi is a good idea for windows user.
 
-Complie libmaix example on AXera-Pi:
+Compile libmaix example on AXera-Pi:
 
 ![mobaxterm_compile_application](./assets/dev_prepare/mobaxterm_compile_application.jpg)
 
@@ -186,7 +186,7 @@ So it can only be executed on Axera-Pi, sending the `test` executable file to Ax
 csp test root@192.168.233.1:/home
 ```
 
-By this command, we succeed upload the `test` executable file to Axera-Pi via rndis protocol by `scp` commmand. And note that the password requirement of running command above is `root`.
+By this command, we succeed upload the `test` executable file to Axera-Pi via rndis protocol by `scp` command. And note that the password requirement of running command above is `root`.
 
 Then we can run `test` executable file on Axera-Pi.
 
@@ -208,11 +208,11 @@ Here are repositories for AXera-Pi, check them if you need.
 
 ### axpi_bsp_sdk
 
-[axpi_bsp_sdk](https://github.com/sipeed/axpi_bsp_sdk) is the bsp development package for business usage. It's the original development package for this chip, containing components like uboot、linux、msp 、sample、rtsp、ipcdemo, and this is progressively open source, you can get these codes for commercial evaluation, such as ipcdemo, but normally these codes are complex and highly coupled, those who are experienced enough and want to use this board for business cooperation can try this.
+[axpi_bsp_sdk](https://github.com/sipeed/axpi_bsp_sdk) is the bsp development package for business usage. It's the original development package for this chip, containing components like uboot, linux, msp, sample, rtsp, ipcdemo, and this is progressively open source, you can get these codes for commercial evaluation, such as ipcdemo, but normally these codes are complex and highly coupled, those who are experienced enough and want to use this board for business cooperation can try this.
 
 ### ax-pipeline
 
-[ax-pipeline](https://github.com/AXERA-TECH/ax-pipeline) is provided by Axera. With m3axpi, this project is used for pepole to know the usages of ISP, image processing, NPU, codec and display, which is convenient for developers to quickly evaluate and develop their own multimedia applications.
+[ax-pipeline](https://github.com/AXERA-TECH/ax-pipeline) is provided by Axera. With m3axpi, this project is used for people to know the usages of ISP, image processing, NPU, codec and display, which is convenient for developers to quickly evaluate and develop their own multimedia applications.
 
 ## SDK usage
 
@@ -301,7 +301,7 @@ To load AI vision model, we need to use camera, screen and AI model. Here are se
 
 ### Build with ax-pipeline (Medium difficulty, for optimization)
 
-This SDK is based on `bsp sdk`(axpi_bsp_sdk), and with better proformance.
+This SDK is based on `bsp sdk`(axpi_bsp_sdk), and with better performance.
 
 - [Compile prepare](https://github.com/AXERA-TECH/ax-pipeline/blob/main/docs/compile.md)
 - [Use yolov5 model](https://github.com/AXERA-TECH/ax-pipeline/blob/main/docs/how_to_deploy_custom_yolov5_model.md)
@@ -309,6 +309,6 @@ This SDK is based on `bsp sdk`(axpi_bsp_sdk), and with better proformance.
 
 ### Build with ipcdemo (Hard for developmrnt, business suggessted)
 
-Based on axpi_bsp_sdk, difficult code with good proformance, it's suggessed for business development.
+Based on axpi_bsp_sdk, difficult code with good performance, it's suggested for business development.
 
 - [axpi_bsp_sdk/app/IPCDemo](https://github.com/sipeed/axpi_bsp_sdk/tree/main/app/IPCDemo)

docs/hardware/en/maixIII/ax-pi/faq_axpi.md

@@ -2,7 +2,7 @@
 title: Maix-III AXera-Pi Q&A
 ---
 
-## Q：Device not work
+## Q：Device does not work
 
 A: Try to plug both 2 USB on m3axpi, by this m3axpi can get enough power to boot. m3axpi comsume 5V*1A maximum.
 
@@ -31,7 +31,7 @@ A：Up to now we only provide screen with 5 inches, and for other screens you ne
 
 ## Q：Error `locale.Error: unsupported locale setting !` when running `xxxx menuconfig`
 
-A: Run `sudo localedef -i en_US -f UTF-8 en_US.UTF-8` to restore the configuration to slove this.
+A: Run `sudo localedef -i en_US -f UTF-8 en_US.UTF-8` to restore the configuration to solve this.
 
 ## Q：Error `VCEncInit:ERROR codecFormat NOT support by HW !` when running `IPC ODM`
 
@@ -66,7 +66,7 @@ A：This happens when data in the tf card system is broken because of the bad qu
 
 ## Q：No eth0 ip address after running `ifconfig -a`
 
-A：There is no ip address if the ethernet is not connected to the Internet, check your ethernet connection. Or use command `dhclient eth0` to get the ip address mannaly or visit [config eth0](https://wiki.sipeed.com/hardware/en/maixIII/ax-pi/flash_system.html#Connect-by-Ethernet) to know more.
+A：There is no ip address if the ethernet is not connected to the Internet, check your ethernet connection. Or use command `dhclient eth0` to get the ip address manually or visit [config eth0](https://wiki.sipeed.com/hardware/en/maixIII/ax-pi/flash_system.html#Connect-by-Ethernet) to know more.
 
 ## Q：Device not found after running uvc
 
@@ -142,7 +142,7 @@ The connector direction of camera changed, make sure the `1` on the connector of
 
 ### Change of screen
 
-We change the screen into new version, and the dafalut image use the latest version screen, see following photo to know your screen version, and for pervious version screen if need to run command `cp /boot/dtb.img.lcd20220830 dtb.img` to apply the hardware. Read [wrong display](#qscreen-display-wrong) to know more.
+We change the screen into new version, and the default image use the latest version screen, see following photo to know your screen version, and for pervious version screen if need to run command `cp /boot/dtb.img.lcd20220830 dtb.img` to apply the hardware. Read [wrong display](#qscreen-display-wrong) to know more.
 
 ![qa_screen_change](./assets/qa/qa_screen_change.jpg)
 
@@ -152,13 +152,13 @@ Why we can only see there is about 1.3G ram for us.
 
 ![htop_memory_usage](./assets/qa/htop_memory_usage.png)
 
-From the following diagram we cansee the original memory map of Axera 620A evb-board, it's equipeed with 1GB ram and is divided into 256MB kernel memory block and 768MB CMM (Contiguous Memory Model) memory block
+From the following diagram we can see the original memory map of Axera 620A evb-board, it's equipped with 1GB ram and is divided into 256MB kernel memory block and 768MB CMM (Contiguous Memory Model) memory block
 
 ![faq_ddr](./../../../zh/maixIII/assets/faq_ddr.png)
 
 And on Axera-Pi we equip 2GB ram, and set 512M CMM memory block and 256M kernel memory block, so there is less than 2GB ram for use.
 
-We can see the `insmod /soc/ko/ax_cmm.ko cmmpool=anonymous,0,0x60000000,512M` to initialize 512M MMC memery from the `auto_load_all_drv.sh`.
+We can see the `insmod /soc/ko/ax_cmm.ko cmmpool=anonymous,0,0x60000000,512M` to initialize 512M MMC memory from the `auto_load_all_drv.sh`.
 
 ![cmm_memory_size_script](./assets/qa/cmm_memory_size_script.png)
 

docs/hardware/en/maixIII/ax-pi/flash_system.md

@@ -41,7 +41,7 @@ We have tested the read and write speed of some TF cards on Axera-pi, for users
 | Number | Model                                    | <p style="white-space:nowrap">Write speed（Write 160MB）</p> | <p style="white-space:nowrap">Read speed（Read 160MB） </p> |
 | ------ | ---------------------------------------- | ------------------------------------------------------------ | ----------------------------------------------------------- |
 | 1.     | Netac A2  P500-HS-64GB                   | 2.04697 s, 80.0 MB/s                                         | 1.8759 s, 87.3 MB/s                                         |
-| 2.     | Samsung microSDXC UHS-I 128G (Bule card) | 2.53387 s, 64.7 MB/s                                         | 1.99882 s, 82.0 MB/s                                        |
+| 2.     | Samsung microSDXC UHS-I 128G (Blue card) | 2.53387 s, 64.7 MB/s                                         | 1.99882 s, 82.0 MB/s                                        |
 | 3.     | EAGET T1 series 64G                      | 6.56955 s, 24.9 MB/s                                         | 7.13792 s, 23.0 MB/s                                        |
 | 4.     | Keychron microSDXC UHS-I 128G            | 2.28133 s, 71.8 MB/s                                         | 1.92001 s, 85.3 MB/s                                        |
 | 5.     | KIOXIA microSDXC UHS-I 32G               | 6.71284 s, 24.4 MB/s                                         | 2.36794 s, 69.2 MB/s                                        |
@@ -156,7 +156,7 @@ Finishing burning system image into tf card, we can assemble this board and boot
 
 **Camera connection**
 
-There are 2 versions of camera, make sure the `1` on the camera matches the `1` on the board. Wrong connection will burn and distory the camera.
+There are 2 versions of camera, make sure the `1` on the camera matches the `1` on the board. Wrong connection will burn and destroy the camera.
 
 <img src="./../../../zh/maixIII/assets/senror_v3751.jpg" width=48%>
 <img src="./../../../zh/maixIII/assets/sensor_v3753.jpg" width=48%>
@@ -851,7 +851,7 @@ echo 1 > /sys/class/gpio/gpio68/value
 
 > Calculating Rule: GPIO2 A4 == 32 *  2 + 4 = 68
 
-For Axera chip, GPIO0 means A IO port and GPIO2 means C IO port, and example like A4 is just a siginal.
+For Axera chip, GPIO0 means A IO port and GPIO2 means C IO port, and example like A4 is just a signal.
 
 GPIO2 A4 in AXera-Pi is GPIO C(2) 4(A4) in standard definition , and standard definition GPIOA0 means IO GPIO0A4 in AXera-Pi.
 
@@ -1141,8 +1141,8 @@ cat /proc/ax_proc/uid
 
 This is an IPC (IP camera) demo program, and its functions are as follows:
 
-- ISP: Transfor the RAW data stream from Sensor into YUV data stream, and output it in 3 channels
+- ISP: Transfers the RAW data stream from Sensor into YUV data stream, and output it in 3 channels
-- IVPS: Image Video Processing submoule, Resize、Crop、Rotate the video image, or change the video image into multiple ones.
+- IVPS: Image Video Processing submodule, Resize, Crop, Rotate the video image, or change the video image into multiple ones.
 - VENC / JENC：Video / JPEG encoded output.
 - Detect: Face detection or structure detection.
 - Web display: H264 Web stream and provides to view real-time Web video.
@@ -1241,7 +1241,7 @@ Here we use [VLC Media Player](https://www.videolan.org/vlc/) to play the rtsp s
 
 ![vl-yolov5s](./../../../zh/maixIII/assets/vlc-yolov5s.jpg)
 
-Run the following cammand on AXera-Pi, open `VLC Media Player` and use hoykey `Ctrl + N` to open a network stream video, enter the ip address of AXera-Pi like `rtsp://192.168.233.1:8554/axstream0` to play the stream video.
+Run the following command on AXera-Pi, open `VLC Media Player` and use hotkey `Ctrl + N` to open a network stream video, enter the ip address of AXera-Pi like `rtsp://192.168.233.1:8554/axstream0` to play the stream video.
 
 Run this command on AXera-Pi:
 ```bash
@@ -1251,7 +1251,7 @@ Run this command on AXera-Pi:
 The log of AXera-Pi running rtsp stream video
 ![vlr-run](./../../../zh/maixIII/assets/vlc-run.jpg)
 
-Enter the ip address of AXera-Pi for playing the stream video, use hoykey `Ctrl + P` to play after entering the ip address of AXera-Pi.
+Enter the ip address of AXera-Pi for playing the stream video, use hotkey `Ctrl + P` to play after entering the ip address of AXera-Pi.
 ![vlc-urt](./../../../zh/maixIII/assets/vlc-urt.jpg)
 
 The rtsp example is as follows:
@@ -1303,7 +1303,7 @@ Run the `ONVIF Device Manager`, click `Refresh` to scan device, make sure you ha
 
 ![onvif_example](./assets/flash_system/onvif_example.jpg)
 
-And we just take RNDIS as example, other IP address like wireless or ethernrt are also fine. Make sure your nerwork is good, and bad network can not use `ONVIF Device Manager` with good experience.
+And we just take RNDIS as example, other IP address like wireless or ethernet are also fine. Make sure your network is good, and bad network can not use `ONVIF Device Manager` with good experience.
 
 - Switch model
 
@@ -1350,7 +1350,7 @@ Use the following command to edit the script file, change the annotation `#` to
 nano /home/examples/vin_ivps_joint_vo_pp_human_seg/run.sh
 ```
 
-Use hoykey  `Ctrl + X` and follow instructions we save the change of editing.
+Use hotkey  `Ctrl + X` and follow instructions we save the change of editing.
 ![pp_human_adb](./../../../zh/maixIII/assets/pp_humana_adb.png)
 
 ### uvc_vo

docs/hardware/en/maixsense/maixsense-a075v/install_drivers.md

@@ -20,7 +20,7 @@ Connect the device with computer, then we can see Serial Device in computer devi
 
 ![Serial device](./assets/install_drivers/serial.png)
 
-Right click it, choose Update driver, then choose `Broswer my computer for drivers`
+Right click it, choose Update driver, then choose `Browser my computer for drivers`
 
 ![Update drivers](./assets/install_drivers/update.png)
 
@@ -32,9 +32,9 @@ We choose `Have Disk...`
 
 ![Install_from_dick](./assets/install_drivers/install.png)
 
-We choose `Broswe...`
+We choose `Browse...`
 
-![broswer](./assets/install_drivers/path.png)
+![browser](./assets/install_drivers/path.png)
 
 Open the extracted downloaded file path, choose one .inf file, click the `open`.
 

docs/hardware/en/maixsense/maixsense-a075v/maixsense-a075v.md

@@ -42,8 +42,8 @@ The preview webpage contained many function configurations, we can change them t
 Here tells the functions of each widgets.
 
 - **RGB_Map** checkbox, control RGB map. Display the deep pseudo-colored point map when checked, display the RGB-mapped point cloud map when unchecked.
-- **colorMap** drop-down bar, provides several pseudo-color mapping options(cmap)，jet is recommended. Avaliable when RGB_Map is unchecked.
+- **colorMap** drop-down bar, provides several pseudo-color mapping options(cmap)，jet is recommended. Available when RGB_Map is unchecked.
-- **deepRangeMax** and **deepRangeMin** slide bar are used for setting the mapping range of cmap, the depth value between deepRangeMin and deepRangeMax are OK. Avaliable when RGB_Map is unchecked.
+- **deepRangeMax** and **deepRangeMin** slide bar are used for setting the mapping range of cmap, the depth value between deepRangeMin and deepRangeMax are OK. Available when RGB_Map is unchecked.
 - **NormalPoint** checkbox, control the display of normal point(There maybe some invalidation points when TOF worked, need to do opposite action). Recommend checked.
 - **OE_Points** checkbox, control the display of OE point. Recommend unchecked.
 - **UE_Points** checkbox, control the display of UE point. Recommend unchecked.

docs/hardware/en/maixzero/sense/start.md

@@ -104,7 +104,7 @@ Burn this demo to board, the data of onboard 6 axi IMU is printed by serial port
 
 Burn this demo to M0sense, press BOOT key, LED changes the color, and the state of LED is printed by serial port.
 
-The detailed usage can be analysised by reading <a href="https://github.com/Sipeed/M0sense_BL702_example/blob/main/m0sense_apps/rtos_demos/single_button_control/main.c">source code</a>.
+The detailed usage can be analyzed by reading <a href="https://github.com/Sipeed/M0sense_BL702_example/blob/main/m0sense_apps/rtos_demos/single_button_control/main.c">source code</a>.
 
 ![single_button_control](./../../../zh/maixzero/sense/assets/start/single_button_control.gif)
 ![single_button_control_uart](./../../../zh/maixzero/sense/assets/start/single_button_control_uart.gif)
@@ -228,9 +228,9 @@ When it shows `Apply patch for you!`, we succeed in doing this.
 
 ![m0sense_patch](./../../../zh/maixzero/sense/assets/start/m0sense_patch.jpg)
 
-### Set toolcahin path
+### Set toolchain path
 
-Everytime compling for M0sense, we need to set toolcahin path once.
+Every time compiling for M0sense, we need to set toolchain path once.
 
 First we need to know the path of `M0sense_BL702_example`:
 
@@ -239,13 +239,13 @@ sipeed@DESKTOP:~$ pwd
 /home/lee/M0sense_BL702_example
 ```
 
-We copy the result (the result of everyone is different) of `pwd` command, then add `/toolchain_gcc_sifive_linux/bin` in the end，run following command, then we finish setting the toolcahin path.
+We copy the result (the result of everyone is different) of `pwd` command, then add `/toolchain_gcc_sifive_linux/bin` in the end，run following command, then we finish setting the toolchain path.
 
 ```bash
 PATH=$PATH:/home/lee/M0sense_BL702_example/toolchain_gcc_sifive_linux/bin
 ```
 
-Then we can use command `riscv64-unknown-elf-gcc -v` to test our toolcahin, here is the right result.
+Then we can use command `riscv64-unknown-elf-gcc -v` to test our toolchain, here is the right result.
 
 ```bash
 sipeed@DESKTOP:~$ riscv64-unknown-elf-gcc -v
@@ -255,7 +255,7 @@ COLLECT_LTO_WRAPPER=/home/lee/M0sense_BL702_example/toolchain_gcc_sifive_linux/b
 Target: riscv64-unknown-elf
 ```
 
-If not set the path right, the command `riscv64-unknown-elf-gcc` will be shown not found, try to reset the toolcahin path.
+If not set the path right, the command `riscv64-unknown-elf-gcc` will be shown not found, try to reset the toolchain path.
 
 ![m0sense_toolchain_notfound](./../../../zh/maixzero/sense/assets/start/m0sense_toolchain_notfound.jpg)
 
@@ -281,7 +281,7 @@ The demo of uf2 format which can be burned to M0sense by u-disk is in the uf2_de
 ## SDK Note
 
 1. Compiling your own firmware conversion application if it's the first time compiling.
-2. Everytime compiling the firmware, make sure you have [set the toolcahin path](#set-toolcahin-path)
+2. Everytime compiling the firmware, make sure you have [set the toolchain path](#set-toolchain-path)
 3. If failing to compile SDK. make sure the compiling command is `./build.sh m0sense_apps/blink/blink_baremetal`, not `./build.sh m0sense_apps/blink/blink_baremetal/` (Pay attention to the `/` in the end)
 
 ## Burn bin file

docs/hardware/en/modules/micarray.md

@@ -36,7 +36,7 @@ Get it:
 | Sound pressure level | 140 dB SPL |
 | Sensitivity | -26(dB,dBFS @1kHz 1Pa) |
 | Signal noise ratio | 57 dB (20kHz bandwidth,A-weighted) <br>THD<1% (100dB SPL @1kHz S=Nom,Rload>2k ) |
-| Clock frequenxy | 1.0-4.0Mhz(Normal mode) <br>150-800khz(Low energy mode) |
+| Clock frequency | 1.0-4.0Mhz(Normal mode) <br>150-800khz(Low energy mode) |
 
 ## Pin definition
 
@@ -78,7 +78,7 @@ Because of the FPIOA feature of K210, each peripheral can be mapped to any pin.
 
 ### Burn firmware
 
-Go to [Download station](https://dl.sipeed.com/shareURL/MAIX/MaixPy/release/master) to download firmware, download the defalut firmware described in [Firmware naming instructions](https://wiki.sipeed.com/soft/maixpy/en/get_started/upgrade_maixpy_firmware.html#Get-the-firmware) .
+Go to [Download station](https://dl.sipeed.com/shareURL/MAIX/MaixPy/release/master) to download firmware, download the default firmware described in [Firmware naming instructions](https://wiki.sipeed.com/soft/maixpy/en/get_started/upgrade_maixpy_firmware.html#Get-the-firmware) .
 
 
 ### Micropython Code
@@ -102,7 +102,7 @@ mic.deinit()
 
 ```
 
-According to the pin number of your own connection, `init(i2s_d0=23, i2s_d1=22, i2s_d2=21, i2s_d3=20, i2s_ws=19, i2s_sclk=18, sk9822_dat=24, sk9822_clk=25) `. For example, if the `MIC_D0` on the microphone array is connected to the pin labeled 25 on the K210 board, then the corresponding parameter in this code needs to be changed to `i2s_d0=25`, the other seven pins should be changed by the same way. Since configuration of everyone is different, there are no identical connection instructions for using jumper wires, modify the pin parameters individually, and don't forget to delete the commect before `mic.init(...). `(just delete `#`).
+According to the pin number of your own connection, `init(i2s_d0=23, i2s_d1=22, i2s_d2=21, i2s_d3=20, i2s_ws=19, i2s_sclk=18, sk9822_dat=24, sk9822_clk=25) `. For example, if the `MIC_D0` on the microphone array is connected to the pin labeled 25 on the K210 board, then the corresponding parameter in this code needs to be changed to `i2s_d0=25`, the other seven pins should be changed by the same way. Since configuration of everyone is different, there are no identical connection instructions for using jumper wires, modify the pin parameters individually, and don't forget to delete the comment before `mic.init(...). `(just delete `#`).
 
 > Make sure not use the pin which has been used for peripherals(Like camera pins or lcd pins should not bu used for this micarray pin), which will make amazing error.
 

docs/hardware/en/sidebar.yaml

@@ -296,7 +296,7 @@ items:
                     file: tang/Tang-primer/get_started/install_linux.md
             -   label: Blink by FPGA
                 file: tang/Tang-primer/fpga/led.md
-            -   label: ' Prepare E203 enviroument'
+            -   label: ' Prepare E203 environment'
                 file: tang/Tang-primer/get_started/E203.md
             -   label: Burn FPGA
                 file: tang/Tang-primer/get_started/fpga_download.md
@@ -396,7 +396,7 @@ items:
     -   label: Longon Nano
         file: longan/Nano/Longan_nano.md
         items:
-        -   label: Setup enviroument
+        -   label: Setup environment
             file: longan/Nano/pio.md
         -   label: Blink test
             file: longan/Nano/blink.md

docs/hardware/en/tang/Tang-Nano-1K/Nano-1k.md

@@ -4,7 +4,7 @@
 
 ## Introduction
 
-Tang Nano 1K is a core board designed based on [Gowin](https://www.gowinsemi.com/en/) GW1NZ-LV1 FPGA chip. The board is equipped with RGB LCD interface and onboard USG-JTAG debugger, which make it convinent for users to use. User can use this for small digital logic design and experiment.
+Tang Nano 1K is a core board designed based on [Gowin](https://www.gowinsemi.com/en/) GW1NZ-LV1 FPGA chip. The board is equipped with RGB LCD interface and onboard USG-JTAG debugger, which make it convenient for users to use. User can use this for small digital logic design and experiment.
 
 ![Nano-1](./assets/1k-1.jpg)
 ![Nano-2](./assets/1k-2.jpg)

docs/hardware/en/tang/Tang-Nano-1K/examples/lcd.md

@@ -32,7 +32,7 @@ The following picture shows the screenshot about this LCD timing.
 
 The first picture form shows parameters of the screen and the the following picture is its timing. 
 
-From its timing picture, we can know we don't need to set front porch time and back proch time, we just need to set blanking time. 
+From its timing picture, we can know we don't need to set front porch time and back porch time, we just need to set blanking time. 
 
 ## Create project 
 

docs/hardware/en/tang/Tang-Nano-1K/examples/led/create_led.md

@@ -9,7 +9,7 @@ From this essay we can learn the basic usage of Gowin IDE
 Create Project：File-->NEW-->FPGA Dsign Project-->OK
 ![](./../../../../../zh/tang/Tang-Nano/assets/LED-1.png)
 
-Set project name and project path (File name and project path shoule be English)
+Set project name and project path (File name and project path should be English)
 ![](./../../../../../zh/tang/Tang-Nano/assets/LED-2.png)
 
 Choose correct device: 
@@ -18,7 +18,7 @@ Choose correct device:
 ## Prepare codes
 
 After creating project, we can start editing codes. 
-To creat a new file, we can click where the arrow points to in the picture or use shortcut key Ctrl+N.
+To create a new file, we can click where the arrow points to in the picture or use shortcut key Ctrl+N.
 Then choose Verilog File in the pop-up window.
 ![](./../../../../../zh/tang/Tang-Nano/assets/LED-5.png)
 

docs/hardware/en/tang/Tang-Nano-4K/Nano-4K.md

@@ -4,7 +4,7 @@
 
 ## Introduction
 
-Tang Nano 4K is a development board designed based on [Gowin](https://www.gowinsemi.com/en/) little-bee GW1NSR-LV4C FPGA chip. The board is equipped with camera interface and HDMI interface. There is also an onboard USG-JTAG debugger, which make it convinent for users to use. Its Cortex-M3 hardcore can help users study mcu.
+Tang Nano 4K is a development board designed based on [Gowin](https://www.gowinsemi.com/en/) little-bee GW1NSR-LV4C FPGA chip. The board is equipped with camera interface and HDMI interface. There is also an onboard USG-JTAG debugger, which make it convenient for users to use. Its Cortex-M3 hardcore can help users study mcu.
 
 ![Tang Nano 4K](./assets/4k-1.jpg)
 ![Tang Nano 4K](./assets/4k-2.jpg)
@@ -18,7 +18,7 @@ Tang Nano 4K is a development board designed based on [Gowin](https://www.gowins
 | FPGA chip           | GW1N-1-LV             | GW1NSR-LV4C    |
 | logic units         | 1152                  | 4608           |
 | Register            | 864                   | 3456           |
-| Hard processor      | none                  | ARM Cortex m3  |
+| Hard processor      | none                  | ARM Cortex M3  |
 | Block SRAM(bits)    | 72K                   | 180K           |
 | User flash(bits)    | 96K                   | 256K           |
 | Number of PLL       | 1                     | 2              |

docs/hardware/en/tang/Tang-Nano-4K/examples/led.md

@@ -23,7 +23,7 @@ Choose correct device:
 ## Prepare codes
 
 After creating project, we can start editing codes. 
-To creat a new file, we can click where the arrow points to in the picture or use shortcut key Ctrl+N.
+To create a new file, we can click where the arrow points to in the picture or use shortcut key Ctrl+N.
 Then choose Verilog File in the pop-up window.
 ![](./../../../../zh/tang/Tang-Nano/assets/LED-5.png)
 

docs/hardware/en/tang/Tang-Nano-9K/Nano-9K.md

@@ -2,7 +2,7 @@
 
 ## Introduction
 
-The Tang Nano 9K, powered by [Gowin's](https://www.gowinsemi.com/en/) GW1NR-9 FPGA chip, is a versatile and feature-rich development board. It features several often used connectors, including HDMI, RGB screen, and SPI screen interfaces, aswell as a 32Mbit SPI flash and six LEDs. It has 8640 LUT4 logic units, an onboard 27MHz clock and 2 PLLs meaning, as well as basic FPGA designs, it can also be used for full risc-v softcores such as PicoRV.
+The Tang Nano 9K, powered by [Gowin's](https://www.gowinsemi.com/en/) GW1NR-9 FPGA chip, is a versatile and feature-rich development board. It features several often used connectors, including HDMI, RGB screen, and SPI screen interfaces, as well as a 32Mbit SPI flash and six LEDs. It has 8640 LUT4 logic units, an onboard 27MHz clock and 2 PLLs meaning, as well as basic FPGA designs, it can also be used for full risc-v softcores such as PicoRV.
 
 ![](./../../../assets/Tang/Nano-9K/9K.png)
 
@@ -68,7 +68,7 @@ Indepth specifications of the tang nano 9k.
 
 3. **[Software User Guide](https://dl.sipeed.com/fileList/TANG/Nano%209K/6_Chip_Manual/EN/General%20Guide/SUG100-2.6E_Gowin%20Software%20User%20Guide.pdf)**: Refer to the "SUG100-2.6E_Gowin Software User Guide.pdf" in the downloaded package for detailed software instructions.
 
-4. **[LED Tutorial](./examples/led.md)**: A simple project to get you acquianted to FPGAs and the tangnano9k.
+4. **[LED Tutorial](./examples/led.md)**: A simple project to get you acquainted to FPGAs and the tangnano9k.
    - **Verilog Code Standards**: It's crucial to adhere to good coding practices.
    - **Recommended Reading**:
      - SUG949-1.1E_Gowin HDL Coding User Guide.pdf

docs/hardware/en/tang/Tang-Nano-9K/examples/led.md

@@ -8,7 +8,7 @@ This tutorial will walk you through the basics of the Gowin IDE, which we'll use
 
 ## Create Project
 
-Create Project：File-->NEW-->FPGA Dsign Project-->OK
+Create Project：File-->NEW-->FPGA Design Project-->OK
 ![Create Project](./../../../../zh/tang/Tang-Nano/assets/LED-1.png)
 
 Set project name and project path (File name and project path should be English)
@@ -136,10 +136,10 @@ Once that's complete, the LEDs start flashing like this：
 
 ## Other
 
-If you need to store firmware with no power, just change Accsess mode and choose your target .fs file .
+If you need to store firmware with no power, just change Access mode and choose your target .fs file .
 ![Access_mode](./../../../../zh/tang/Tang-Nano-9K/nano_9k/access_mode.png)
 
-Visit [Qustions&Answers](./../../Tang-Nano-Doc/questions.md) if you have trouble
+Visit [Questions&Answers](./../../Tang-Nano-Doc/questions.md) if you have trouble
 
 ## End
 

docs/hardware/en/tang/Tang-Nano-9K/examples/picorv.md

@@ -34,7 +34,7 @@ python .\sw\pico-programmer.py .\example-fw-flash.v COM13
 The COM13 at the end of command line refers to the serial port number of the development board in the system.
 For example, if it is allocated COM14 in your system, you need change it into COM14.
 
-There is a countdown shows `- Waiting for reset -` when you succeed excute the command, in which time it's required to press the S1 button of the development board to complete the programming. 
+There is a countdown shows `- Waiting for reset -` when you succeed execute the command, in which time it's required to press the S1 button of the development board to complete the programming. 
 The succeed done log is as below:
 
 ```powershell

docs/hardware/en/tang/Tang-Nano-9K/examples/rgb_screen.md

@@ -32,7 +32,7 @@ The following picture shows the screenshot about this LCD timing.
 
 The first picture form shows parameters of the screen and the the following picture is its timing. 
 
-From its timing picture, we can know we don't need to set front porch time and back proch time, we just need to set blanking time. 
+From its timing picture, we can know we don't need to set front porch time and back porch time, we just need to set blanking time. 
 
 ## Create project 
 
@@ -285,7 +285,7 @@ If there is some thing wrong, please fix by yourself.
 
 The corresponding pins and ports are as follows form shows
 
-The way to constain pins can refer to the [Light led](./../led/led.md), it contains a way to constain pins.
+The way to constain pins can refer to the [Light led](./../led/led.md), it contains a way to constrain pins.
 
 If you feel troublesome about the method above, you can copy the content from this [page](./../../../../zh/tang/Tang-Nano-9K/examples/lcd_constrains.md)， and paste it in ".cst" file in this project (if there is no ".cst" file, just create a "physicsl constrains file").
 

docs/hardware/en/tang/Tang-Nano-Doc/flash-in-linux.md

@@ -5,7 +5,7 @@ keyeords: Linux, FPGA, Gowin
 
 It's recommended to use **openFPGALoader** to flash the development board from linux environments. This page covers installation instructions and has been verified on Ubuntu but may work on other linux distributions.
 
-The currently available package on Ubuntu is older ('openfpgaloader') and does not support the latest boards (i.e. tangnano20k), because of this compiling the latest git source is recommended and covered below (adapted from the offical projects documentation: https://trabucayre.github.io/openFPGALoader/guide/install.html).
+The currently available package on Ubuntu is older ('openfpgaloader') and does not support the latest boards (i.e. tangnano20k), because of this compiling the latest git source is recommended and covered below (adapted from the official projects documentation: https://trabucayre.github.io/openFPGALoader/guide/install.html).
 
 ### Compiling openFPGALoader from git
 
@@ -64,7 +64,7 @@ index 0:
 
 ```
 
-Flash the bitstream to the device as shown below. The board name must be speficied after the `-b` option, `-f` options means the file is programmed to the non-volatile flash, without it it will be stored in SRAM but lost if the device loses power.
+Flash the bitstream to the device as shown below. The board name must be specified after the `-b` option, `-f` options means the file is programmed to the non-volatile flash, without it it will be stored in SRAM but lost if the device loses power.
 
 ```bash
 $ sudo ./openFPGALoader -b tangnano9k -f ../../nano9k_lcd/impl/pnr/Tang_nano_9K_LCD.fs

docs/hardware/en/tang/Tang-Nano-Doc/install-the-ide.md

@@ -103,7 +103,7 @@ if the ip not work, try use "gowinlic.sipeed.com" domain's IP.
 
 When you run GOWIN IDE, a license manager message box will appear. Once you have a license file you can click `Browse...` and select your license file, then `Check` and finally `Save`.
 
-<img src="./assets/IDE-13.png" alt="Broswer lic" width=45%>
+<img src="./assets/IDE-13.png" alt="Browser lic" width=45%>
 <img src="./assets/check.png"  alt="Check lic"   width=45%>
 
 Now you can use the GOWIN IDE.
@@ -116,7 +116,7 @@ For Linux users, go to the end of this page to see the section [burn-in-linux](#
 
 ## Other 
 
-It may take some time to receive a license. During this time we sugegst you read the GOWIN Semiconductor Corp official documents, which are installed with the IDE.
+It may take some time to receive a license. During this time we suggest you read the GOWIN Semiconductor Corp official documents, which are installed with the IDE.
 
 There are three things in the IDE installation path: IDE folder, Programmer folder, uninst.exe
 

docs/hardware/en/tang/Tang-Nano-Doc/questions.md

@@ -8,7 +8,7 @@ update:
     version: v0.3
     author: wonder
     content:
-      - Add some informations
+      - Add some information
 ---
 
 
@@ -47,7 +47,7 @@ It takes 10 seconds for debugger loading the driver. And you can install the dri
 
 ### Download frequency
 
-Make sure the frquency is equal or lower than `2.5MHz`, otherwise it may lead some troubles like burnning bitstream file really slow or failed burnning bitstream file.
+Make sure the frequency is equal or lower than `2.5MHz`, otherwise it may lead some troubles like burning bitstream file really slow or failed burning bitstream file.
 
 <img src="./../../../zh/tang/assets/questions/cable.png">
 
@@ -61,21 +61,21 @@ Then cilck Save
 
 This error means the Programmer application does detect debugger or your driver is wrong. 
 Visit [this programmer](https://dl.sipeed.com/shareURL/TANG/programmer) compressed file, download it and extract it, replace the programmer folder install with GOWIN IDE by this extracted file.
-If you don't know how to replace the programmer folder, just excute the programmer application in the extracted folder to download bisdtream file instead of the programmer application installed with GOWIN IDE.
+If you don't know how to replace the programmer folder, just execute the programmer application in the extracted folder to download bitstream file instead of the programmer application installed with GOWIN IDE.
 
-If this problem still occurs after you use our recommended programmer application, try to rerun this application. If all attemps fail, see the begin of this documents about `converter`.
+If this problem still occurs after you use our recommended programmer application, try to rerun this application. If all attempts fail, see the begin of this documents about `converter`.
 
 ### Cable lost
 
-Reflash bitstream to solve this. This occurs when flashing bitsteram, board and computer does not well disconneted.
+Reflash bitstream to solve this. This occurs when flashing bitstream, board and computer does not well disconnected.
 
-### Cabel open failed
+### Cable open failed
 
 ![cable_open_failed](./../../../zh/tang/Tang-Nano-Doc/assets/qusetions/cable_open_failed.png)
 
 This means the programmer application does not detect the debugger, try this programmer application mentioned in [Error found](#error-found).
 
-If this problem still occurs after you use our recommended programmer application, try to rerun this application. If all attemps fail, see the begin of this documents about `converter`.
+If this problem still occurs after you use our recommended programmer application, try to rerun this application. If all attempts fail, see the begin of this documents about `converter`.
 
 <!-- 
 After finishing replacing **programmer** as mentioned previously,Do following steps in programmer application.
@@ -95,13 +95,13 @@ Click Edit->Cable Setting->Cable->Query in the top menu bar,then save.
 
 ![no_gowin_device_found](./../../../zh/tang/Tang-Nano-Doc/assets/qusetions/no_gowin_device_found.png)
 
-This means the debugger does not detect the FPGA chip, you can use the latest [GOWIN Programmer](http://www.gowinsemi.com.cn/faq.aspx) to slove this problem.
+This means the debugger does not detect the FPGA chip, you can use the latest [GOWIN Programmer](http://www.gowinsemi.com.cn/faq.aspx) to solve this problem.
 
 ![gowin_programmer_download](./assets/questions/gowin_programmer_download.png)
 
 #### Nano 9K
 
-Because the FPGA JTAG_SEL pin is routed to Key S2, from the GOWIN mannual we can see when JTAGSEL_N=0 (Active low), Jtag is enabled.
+Because the FPGA JTAG_SEL pin is routed to Key S2, from the GOWIN manual we can see when JTAGSEL_N=0 (Active low), Jtag is enabled.
 
 ![gw1nr_9c_jtag_sel](./assets/questions/gw1nr_9c_jtag_sel.png)
 
@@ -115,7 +115,7 @@ For 20K Dock kits, it's necessary to enable the core board before using debugger
 | --- | --- | --- |
 |<img src="./../../../zh/tang/tang-primer-20k/assets/start/switch_1_on.png" alt="switch_1_on" width=100%>|<img src="./../../../zh/tang/tang-primer-20k/assets/start/reset_led_on.png" alt="reset_led_on" width=100%> | When disabled, the LDE0 and LED1 is on, and core board doesn't work.|
 
-When using RV Debugger Plus burnning firmware into 20K core board this error occurs, possibly the order of connectting wire is wrong, make sure your connectting order is same as following sheet, or you can check your core board jtag connector inside pins, make sure none of them are crooked(One time we get problem connecting Debugger with core board and finnaly check out that there is a crooked pin in the jtag connector, this maybe because of doing wrong connection operations when connecting)
+When using RV Debugger Plus burning firmware into 20K core board this error occurs, possibly the order of connecting wire is wrong, make sure your connecting order is same as following sheet, or you can check your core board jtag connector inside pins, make sure none of them are crooked(One time we get problem connecting Debugger with core board and finally check out that there is a crooked pin in the jtag connector, this maybe because of doing wrong connection operations when connecting)
 
 The JTAG pin orders can be found in the back of 20K core board.
 
@@ -150,7 +150,7 @@ The JTAG pin orders can be found in the back of 20K core board.
 
 ![id_code_mismatch](./../../../zh/tang/Tang-Nano-Doc/assets/qusetions/id_code_mismatch.png)
 
-This means the selected device in the project mismatch your burnning chip. All that refers chip model(The project device, pin constrain, IP modules and programmer device choose) need to be reset.
+This means the selected device in the project mismatch your burning chip. All that refers chip model(The project device, pin constrain, IP modules and programmer device choose) need to be reset.
 
 | Board name | Series | Device | Package | Speed |
 | --- | --- | --- | --- | --- |
@@ -172,7 +172,7 @@ For other boards, just make sure your device selection corresponds to the laser
 
 ### spi flash selected mismatch
 
-The board using GOWIN Semiconductor LittleBee product family (Series of chip names beginning with GW1N) incorporates embedded FLASH in main chip, so when burning firmware we burn into embedded FLASH, and reagrd the external FLASH as a peripheral. 
+The board using GOWIN Semiconductor LittleBee product family (Series of chip names beginning with GW1N) incorporates embedded FLASH in main chip, so when burning firmware we burn into embedded FLASH, and regard the external FLASH as a peripheral. 
 
 The board using GOWIN Semiconductor Arora product family (Series of chip names beginning with GW1N) does not incorporate embedded FLASH, so when burning firmware we burn into external FLASH, and the operations are as followed . 
 
@@ -200,23 +200,23 @@ Choose Frequency equal to or lower than 2.5MHz
 
 <img src="./../../../zh/tang/assets/questions/frequency.png" >
 
-Then cilck Save
+Then click Save
 
 ### Directory *** has null character.
 
 Error character of the project path.
 
 - Close IDE.
-- Check projrct path, only English works and `_` are Ok, take care of the blank character ` ` in the path.
+- Check project path, only English works and `_` are Ok, take care of the blank character ` ` in the path.
 - Reopen the project, clean and rerun your project.
 
-### Can't find bistream file
+### Can't find bitstream file
 
-Normally the bistream file with extension name `.fs` is in the impl/pnr folder under the project path.
+Normally the bitstream file with extension name `.fs` is in the impl/pnr folder under the project path.
 
 <img src="./../../../zh/tang/assets/questions/fs_path.png">
 
-From the picture above we can know the  of this bistream file path is `fpga_project1/impl/pnr/fpga_project1.fs`
+From the picture above we can know the  of this bitstream file path is `fpga_project1/impl/pnr/fpga_project1.fs`
 
 The fpga_project1 is the project directory, the impl folder is generated by IDE, and the download is in the pnr folder.
 
@@ -244,11 +244,11 @@ In the IP Core generate interface of IDE, click the folder icon next to device s
 
 ### Set top module
 
-For project containning muti-projects, if you succeed generating your module, right-click the module you want to set as the top module IDE -> Hierarchy interface.
+For project that contains multiple-projects, if you succeed generating your module, right-click the module you want to set as the top module IDE -> Hierarchy interface.
 
 ![set_top_module](./../../../zh/tang/Tang-Nano-Doc/assets/set_top_module.png)
 
-If your Hierarchy interface is the same as what is in the left picture, this means there are logic errors in the code, such as syntax errors or generate errors. Click 'RTL Anakysis Error' in the upper right corner then you can see the error type code and location of the error in the dialog box that pops up, as shown in the right picture in the following table.
+If your Hierarchy interface is the same as what is in the left picture, this means there are logic errors in the code, such as syntax errors or generate errors. Click 'RTL Analysis Error' in the upper right corner then you can see the error type code and location of the error in the dialog box that pops up, as shown in the right picture in the following table.
 
 <table>
 <tr>

docs/hardware/en/tang/Tang-Nano-Doc/summary.md

@@ -2,10 +2,10 @@
 title: Tang Nano
 ---
 
-Tang Nano series development boards are designed based on [Gowin](https://www.gowinsemi.com/en/) FPGA chip. Mutiple models of development board meets various requirements. 
+Tang Nano series development boards are designed based on [Gowin](https://www.gowinsemi.com/en/) FPGA chip. Multiple models of development board meets various requirements. 
 - Tang nano 1K with a extremely low price can lead user into FPGA fields
 - Tang nano 4K with a Cortex m3 hardcore, almost the cheapest heterogeneous core board
-- Tang nano 9K with rich logic units can be used to verify Riscv core 
+- Tang nano 9K with rich logic units can be used to verify RISC-V core 
 
 ## Comparation
 

docs/hardware/en/tang/Tang-Nano/Nano.md

@@ -4,7 +4,7 @@
 
 ## Introduction
 
-Tang Nano is a core board designed based on [Gowin](https://www.gowinsemi.com/en/) GW1N-1 FPGA chip.The board is equipped with PSRAM, RGB LCD interface and onboard USG-JTAG debugger, which make it convinent for users to use.
+Tang Nano is a core board designed based on [Gowin](https://www.gowinsemi.com/en/) GW1N-1 FPGA chip.The board is equipped with PSRAM, RGB LCD interface and onboard USG-JTAG debugger, which make it convenient for users to use.
 
 ![](./../../../assets/Tang/Nano/Tang_Nano.jpg)
 

docs/hardware/en/tang/Tang-Nano/examples/lcd.md

@@ -32,7 +32,7 @@ The following picture shows the screenshot about this LCD timing.
 
 The first picture form shows parameters of the screen and the the following picture is its timing. 
 
-From its timing picture, we can know we don't need to set front porch time and back proch time, we just need to set blanking time. 
+From its timing picture, we can know we don't need to set front porch time and back porch time, we just need to set blanking time. 
 
 ## Create project 
 
@@ -115,7 +115,7 @@ As for the front porch timing and back porch timing which have been mentioned ea
 
 ### Define variables
 
-- Define some variables helps us to meet timing requirment
+- Define some variables helps us to meet timing requirement
   
 ```verilog 
 
@@ -282,7 +282,7 @@ If there is some thing wrong, please fix by yourself.
 
 The corresponding pins and ports are as follows form shows
 
-The way to constain pins can refer to the [Light led](./led/create_led.md), it contains two ways to constain pins.
+The way to constrain pins can refer to the [Light led](./led/create_led.md), it contains two ways to constrain pins.
 
 If you feel troublesome about the method above,  you can copy the content in this [page](./../../../../zh/tang/Tang-Nano/examples/lcd_constrains.md)， and paste it in ".cst" file in this project (If there is no ".cst" file, just create a "physicsl constrains file"). 
 

docs/hardware/en/tang/Tang-primer/Tang-primer.md

@@ -49,5 +49,5 @@ Pinout for **Old** Tang Primer Board.
 
 + Schematic of Lichee Tang [Click me](https://dl.sipeed.com/shareURL/TANG/Primer/HDK) and choose `LicheeTang_RV(Schematic).pdf`
 
-Besides, its development enviroument IDE TD(Tang Dynasty) can be downloaded from following sites
+Besides, its development environment IDE TD(Tang Dynasty) can be downloaded from following sites
 - [https://dl.sipeed.com/shareURL/TANG/Primer/IDE](https://dl.sipeed.com/shareURL/TANG/Primer/IDE)

docs/hardware/en/tang/Tang-primer/get_started/install_TD_win.md

@@ -18,7 +18,7 @@ Then we can run TD
 ## Install the USB serial port
 
 Connect Tang Primer with computer and open device manager to see device information.
-It may be named WinUsb Device or USB-JTAG-Cable duo to different Windows verison.
+It may be named WinUsb Device or USB-JTAG-Cable duo to different Windows version.
 Make sure USB VID:PID is 0547:1002
 
 - Windows7 without installing driver
@@ -64,7 +64,7 @@ The installation is successful and can be seen in the device manager.
 Click on Download button as shown in following image.
 ![](./../../../../zh/tang/assets/get_started/87078310026779781.jpg)
 
-Plugin Tang Primer into your computer and click Refresh buttion on Download Dialog box.
+Plugin Tang Primer into your computer and click Refresh button on Download Dialog box.
 ![](./../../../../zh/tang/assets/get_started/1823555291194601.jpg)
 
 Congratulations, you have setup the TD driver on Windows.

docs/hardware/en/tang/Tang-primer/get_started/install_linux.md

@@ -9,19 +9,19 @@ But we need it to development tang primer
 IDE File name :  `TD_5.0.3_28716_NL_Linux.zip`
 License file：`Anlogic_20230606.lic`
 
-After finising downloading, new a terminal and cd into where we extract `TD_5.0.3_28716_NL_Linux.zip ` and rename the license file Anlogic_20230606.lic to Anlogic.lic, then move the license file to the TD5.0.28716\license folder in the extract path.
+After finishing downloading, new a terminal and cd into where we extract `TD_5.0.3_28716_NL_Linux.zip ` and rename the license file Anlogic_20230606.lic to Anlogic.lic, then move the license file to the TD5.0.28716\license folder in the extract path.
 
 ```bash
 cd <Application path >
 ```
 
-The /opt directory is reserved for all software and add-on packages that are not installed by default in Linux system, so we new a dirctionary for TD.
+The /opt directory is reserved for all software and add-on packages that are not installed by default in Linux system, so we new a directory for TD.
 
 ```bash
 sudo mkdir /opt/TD_DECEMBER2018
 ```
 
-Extract TD into /opt/TD_DECEMBER2018 dirctionary
+Extract TD into /opt/TD_DECEMBER2018 directory
 
 ```bash
 sudo tar -xvf  TD_5.0.3_28716_NL_Linux.zip -d /opt/TD_DECEMBER2018/
@@ -66,10 +66,10 @@ Go to <TD installation directory>/bin/ and execute the following command to open
 ./td -gui
 ```
 
-Plugin Tang Primer into your computer and hit Refresh buttion on Download Dialog box.
+Plugin Tang Primer into your computer and hit Refresh button on Download Dialog box.
 ![](./../../../../zh/tang/Tang-primer/get_started/assets/td_linux_gui.jpg)
 
-Plugin Tang Primer into your computer and hit Refresh buttion on Download Dialog box.
+Plugin Tang Primer into your computer and hit Refresh button on Download Dialog box.
 ![](./../../../../zh/tang/Tang-primer/get_started/assets/refresh.jpg)
 
 > Due to some unknown bug, JTAG only works with 400kbps or lower speed.

docs/hardware/en/tang/readme.md

@@ -260,9 +260,9 @@ If you don't know how to design the PCB, but you want to know more about FPGA, [
   <td style="text-align:left"></td>
 </tr>
 <tr>
-  <td style="text-align:left">Feature</td>
+  <td style="text-align:left">Features</td>
-  <td style="text-align:left">Many Luts, many interface, easy use.</td>
+  <td style="text-align:left">Many LUTs, many interfaces, easy to use.</td>
-  <td style="text-align:left">Many Luts, tiny size, mutiple clock</td>
+  <td style="text-align:left">Many LUTs, tiny size, multiple clocks</td>
   <td style="text-align:left">Good price, enough for softcore</td>
   <td style="text-align:left">FPGA SOC board，can drive DVP camera</td>
   <td style="text-align:left">Cheapest FPGA board</td>

docs/hardware/en/tang/tang-mega-138k/mega-138k.md

@@ -295,7 +295,7 @@ Tang Mega 138K can meet different needs of customers in various scenarios. For t
 
 ### No Response or Undesirable Pin Phenomenon After Burning
 
-1. First, ensure that the IDE has selected the correct model **GW5AST-LV138PG484AC1/10**; every parameter in the figure below **NUST** be consistent.
+1. First, ensure that the IDE has selected the correct model **GW5AST-LV138PG484AC1/10**; every parameter in the figure below **MUST** be consistent.
 
 <img src="./assets/partno_138K.png" alt="device_choose" width=35%>
 

docs/hardware/en/tang/tang-nano-20k/example/led.md

@@ -138,7 +138,7 @@ reg IO_voltage_reg = 1'b0; // Initial state
 
 always @(posedge Clock) begin
     if ( count_value_flag )  //  Flip flag 
-        IO_voltage_reg <= ~IO_voltage_reg; // IO voltage filp
+        IO_voltage_reg <= ~IO_voltage_reg; // IO voltage flip
     else //  No flip flag
         IO_voltage_reg <= IO_voltage_reg; // IO voltage constant
 end
@@ -157,7 +157,7 @@ module led(
 parameter count_value       = 13_499_999; // The number of times needed to time 0.5S
 
 reg [23:0]  count_value_reg ; // counter_value
-reg         count_value_flag; // IO chaneg flag
+reg         count_value_flag; // IO change flag
 
 always @(posedge Clock) begin
     if ( count_value_reg <= count_value ) begin //not count to 0.5S
@@ -175,7 +175,7 @@ reg IO_voltage_reg = 1'b0; // Initial state
 
 always @(posedge Clock) begin
     if ( count_value_flag )  //  Flip flag 
-        IO_voltage_reg <= ~IO_voltage_reg; // IO voltage filp
+        IO_voltage_reg <= ~IO_voltage_reg; // IO voltage flip
     else //  No flip flag
         IO_voltage_reg <= IO_voltage_reg; // IO voltage constant
 end
@@ -208,11 +208,11 @@ Since this is the first time we create it, the following dialog box will pop up.
 
 ![create_constrain_file](./../../../../zh/tang/tang-primer-20k/examples/assets/led_assets/create_constrain_file.png)
 
-![floorplanner_intreface](./../../../../zh/tang/tang-nano-20k/assets/led/nano_20k_floorplanner_interface.png)
+![floorplanner_interface](./../../../../zh/tang/tang-nano-20k/assets/led/nano_20k_floorplanner_interface.png)
 
 The ways to constraint the file can be get from this docs: [SUG935-1.3E_Gowin Design Physical Constraints User Guide.pdf](https://dl.sipeed.com/fileList/TANG/Nano%209K/6_Chip_Manual/EN/General%20Guide/SUG935-1.3E_Gowin%20Design%20Physical%20Constraints%20User%20Guide.pdf)
 
-Here we only use the IO Constranins method shown below to constrain the pins:
+Here we only use the IO Constrains method shown below to constrain the pins:
 
 ![floor_planner_ioconstrain](./../../../../zh/tang/tang-primer-20k/examples/assets/led_assets/floor_planner_ioconstrain.png)
 
@@ -224,7 +224,7 @@ Here we only blink LED0, and we can see it's connected with FPGA PIN15.
 
 ![nano_20k_led_port](./../../../../zh/tang/tang-nano-20k/assets/led/nano_20k_led_port.png)
 
-So for the IO Constranins under the FloorPlanner interactive window, we fill in the following values for PORT and Location:：
+So for the IO Constrains under the FloorPlanner interactive window, we fill in the following values for PORT and Location:：
 
 ![nano_20k_io_constrain_value](./../../../../zh/tang/tang-nano-20k/assets/led/nano_20k_io_constrain_value.png)
 
@@ -236,7 +236,7 @@ Then we see there is a .cst file in our project, and its content are easy to und
 
 ### Place & Route
 
-After finishing constrainting, we run Place & Route. The purpose is to synthesize the generated netlist and our defined constraints to calculate the optimal solution through IDE, then allocate resources reasonably on the FPGA chip.
+After finishing constraining, we run Place & Route. The purpose is to synthesize the generated netlist and our defined constraints to calculate the optimal solution through IDE, then allocate resources reasonably on the FPGA chip.
 
 Double click Place&Route marked with red box to run.
 
@@ -287,7 +287,7 @@ Here we finished downloading into SRAM。
 Burnning into sram is used for verifying biststream, but can't store program.
 If we want to run application at startup, we need to burn into flash.
 
-This steps are similar to the steps above of burnning to SRAM.
+This steps are similar to the steps above of burning to SRAM.
 
 Click the function box below Operation to open the device configuration interface, then select the External Flash Mode in the Access Mode to burn into external Flash. Finally click the three dots below to select the.fs we generated to download the firmware. Choose the three dots box below to select our generated `.fs` bitstream file. Generally speaking, bitstream firmware file is in the impl -> pnr directory. Finally, select the Generic Flash device from the following external Flash options.
 

docs/hardware/en/tang/tang-nano-20k/nano-20k.md

@@ -11,7 +11,7 @@ update:
 
 ## Introduction
 
-Tang Nano 20K is a development board, using the [GW2AR-18 QN88](http://www.gowinsemi.com.cn/prod_view.aspx?TypeId=10&FId=t3:10:3&Id=167#GW2AR) FPGA, containing 20736 LUT4 logic cells and 15552 Filp-Flops. There are 2 PLL in this FPGA chip, and many DSP units supporting 18 bit x 18 bit multiplication. Onboard [BL616](https://bouffalolab.com/product/?type=detail&id=21) is used for downloading bitstream into FPGA, and it's also used as USB to serial convertor to communicate FPGA with computer via UART. The 27MHz crystal generates the clock for HDMI display, onboard MS5351 clock generating chip also provides mutiple clocks.
+Tang Nano 20K is a development board, using the [GW2AR-18 QN88](http://www.gowinsemi.com.cn/prod_view.aspx?TypeId=10&FId=t3:10:3&Id=167#GW2AR) FPGA, containing 20736 LUT4 logic cells and 15552 Flip-Flops. There are 2 PLL in this FPGA chip, and many DSP units supporting 18 bit x 18 bit multiplication. Onboard [BL616](https://bouffalolab.com/product/?type=detail&id=21) is used for downloading bitstream into FPGA, and it's also used as USB to serial convertor to communicate FPGA with computer via UART. The 27MHz crystal generates the clock for HDMI display, onboard MS5351 clock generating chip also provides multiple clocks.
 
 ## Rendering appearance
 

docs/hardware/en/tang/tang-primer-15k/primer-15k.md

@@ -214,7 +214,7 @@ port: 10559
 
 if the ip not work, try use "gowinlic.sipeed.com" domain's IP.
 
-if you don't want to apply for a licence, you can  choose the education version IDE. The education version IDE can be used without a licence, but it usually only contains a limited number of IPs.
+if you don't want to apply for a license, you can  choose the education version IDE. The education version IDE can be used without a license, but it usually only contains a limited number of IPs.
 
 Install IDE [Click me](https://wiki.sipeed.com/hardware/zh/tang/Tang-Nano-Doc/get_started/install-the-ide.html)
 

docs/hardware/en/tang/tang-primer-20k/example.md

@@ -9,7 +9,7 @@ update:
       - Determine directory
 ---
 
-> All examples articles and github are continuing building, thanks for your unserstanding.
+> All examples articles and github are continuing building, thanks for your understanding.
 
 ## LED
 

docs/hardware/en/tang/tang-primer-20k/examples/led.md

@@ -117,7 +117,7 @@ For time counter inside module, crystal oscillator on the Primer 20K core board
 parameter count_value       = 13_499_999; // The number of times needed to time 0.5S
 
 reg [23:0]  count_value_reg ; // counter_value
-reg         count_value_flag; // IO chaneg flag
+reg         count_value_flag; // IO change flag
 
 always @(posedge Clock) begin
     if ( count_value_reg <= count_value ) begin //not count to 0.5S
@@ -138,7 +138,7 @@ reg IO_voltage_reg = 1'b0; // Initial state
 
 always @(posedge Clock) begin
     if ( count_value_flag )  //  Flip flag 
-        IO_voltage_reg <= ~IO_voltage_reg; // IO voltage filp
+        IO_voltage_reg <= ~IO_voltage_reg; // IO voltage flip
     else //  No flip flag
         IO_voltage_reg <= IO_voltage_reg; // IO voltage constant
 end
@@ -157,7 +157,7 @@ module led(
 parameter count_value       = 13_499_999; // The number of times needed to time 0.5S
 
 reg [23:0]  count_value_reg ; // counter_value
-reg         count_value_flag; // IO chaneg flag
+reg         count_value_flag; // IO change flag
 
 always @(posedge Clock) begin
     if ( count_value_reg <= count_value ) begin //not count to 0.5S
@@ -175,7 +175,7 @@ reg IO_voltage_reg = 1'b0; // Initial state
 
 always @(posedge Clock) begin
     if ( count_value_flag )  //  Flip flag 
-        IO_voltage_reg <= ~IO_voltage_reg; // IO voltage filp
+        IO_voltage_reg <= ~IO_voltage_reg; // IO voltage flip
     else //  No flip flag
         IO_voltage_reg <= IO_voltage_reg; // IO voltage constant
 end
@@ -212,7 +212,7 @@ Since this is the first time we create it, the following dialog box will pop up.
 
 The ways to constraint the file can be get from this docs: [SUG935-1.3E_Gowin Design Physical Constraints User Guide.pdf](https://dl.sipeed.com/fileList/TANG/Nano%209K/6_Chip_Manual/EN/General%20Guide/SUG935-1.3E_Gowin%20Design%20Physical%20Constraints%20User%20Guide.pdf)
 
-Here we only use the IO Constranins method shown below to constrain the pins:
+Here we only use the IO Constraints method shown below to constrain the pins:
 
 ![floor_planner_ioconstrain](./../../../../zh/tang/tang-primer-20k/examples/assets/led_assets/floor_planner_ioconstrain.png)
 
@@ -224,7 +224,7 @@ Taking into consideration the IO screen printing on the ext_board, we decide to
 
 ![led_port](./../../../../zh/tang/tang-primer-20k/examples/assets/led_assets/led_port.png)
 
-So for the IO Constranins under the FloorPlanner interactive window, we fill in the following values for PORT and Location:
+So for the IO Constraints under the FloorPlanner interactive window, we fill in the following values for PORT and Location:
 
 ![io_constrain_value](./../../../../zh/tang/tang-primer-20k/examples/assets/led_assets/io_constrain_value.png)
 
@@ -236,7 +236,7 @@ Then we see there is a .cst file in our project, and its content are easy to und
 
 ### Place & Route
 
-After finishing constrainting, we run Place & Route. The purpose is to synthesize the generated netlist and our defined constraints to calculate the optimal solution through IDE, then allocate resources reasonably on the FPGA chip.
+After finishing constraining, we run Place & Route. The purpose is to synthesize the generated netlist and our defined constraints to calculate the optimal solution through IDE, then allocate resources reasonably on the FPGA chip.
 
 Double click Place&Route marked with red box to run.
 
@@ -286,10 +286,10 @@ Here we finished downloading into SRAM。
 
 ### Burn into Flash
 
-Burnning into sram is used for verifying biststream, but can't store program.
+Burning into sram is used for verifying bitstream, but can't store program.
 If we want to run application at startup, we need to burn into flash.
 
-This steps are similar to the steps above of burnning to SRAM.
+This steps are similar to the steps above of burning to SRAM.
 
 Click the function box below Operation to open the device configuration interface, then select the External Flash Mode in the Access Mode to burn into external Flash. Finally click the three dots below to select the.fs we generated to download the firmware. Choose the three dots box below to select our generated `.fs` bitstream file. Generally speaking, bitstream firmware file is in the impl -> pnr directory. Finally, select the Generic Flash device from the following external Flash options.
 
@@ -341,7 +341,7 @@ According to the simulation results, we can see the difference between blocking
 
 And we get two results:
 - Input data is not always valid, it depends on the clock edge. If the data is maintained for less than one clock cycle, it may regard useless data.
-- Everytime Triggerring the edge clock, the `always` block runs from begin to the end, not runs from the middle.
+- Every time Triggering the edge clock, the `always` block runs from begin to the end, not runs from the middle.
 
 ## Questions
 

docs/hardware/en/tang/tang-primer-20k/examples/lite/blink.md

@@ -15,7 +15,7 @@ Let's blink a led after getting the Tang Primer 20K Lite suits.
 
 ## Preread
 
-This document is writen for guiding user start preparing GOWIN development enviroment and use the Tang Primer 20K.
+This document is writen for guiding user start preparing GOWIN development environment and use the Tang Primer 20K.
 
 The default firmware function in the Core board is as followings:
 - All IO port routed to pin 2.54mm pad toggles regularly, including spi_lcd connector ports and sd_card connector ports on Core Board
@@ -25,13 +25,13 @@ Because of the DDR test function, Core Board will be very hot. you can erase the
 
 ## Install IDE
 
-Visit [Install IDE](./../../../Tang-Nano-Doc/install-the-ide.md) to prepare the enviroment for this FPGA.
+Visit [Install IDE](./../../../Tang-Nano-Doc/install-the-ide.md) to prepare the environment for this FPGA.
 
 For Linux users, if it's difficult to run Programmer application to burn firmware into fpga, please visit [OpenFpgaloader](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-Doc/flash-in-linux.html) to see how to use it.
 
 ## New Project
 
-New Project：File-->NEW-->FPGA Dsign Project-->OK
+New Project：File-->NEW-->FPGA Design Project-->OK
 
 <img src="./../../../Tang-Nano-1K/assets/LED-1.png" width=35% alt="new_project">
 
@@ -121,7 +121,7 @@ For time counter inside module, crystal oscillator on the Primer 20K core board
 parameter count_value       = 13_499_999; // The number of times needed to time 0.5S
 
 reg [23:0]  count_value_reg ; // counter_value
-reg         count_value_flag; // IO chaneg flag
+reg         count_value_flag; // IO change flag
 
 always @(posedge Clock) begin
     if ( count_value_reg <= count_value ) begin //not count to 0.5S
@@ -142,7 +142,7 @@ reg IO_voltage_reg = 1'b0; // Initial state
 
 always @(posedge Clock) begin
     if ( count_value_flag )  //  Flip flag 
-        IO_voltage_reg <= ~IO_voltage_reg; // IO voltage filp
+        IO_voltage_reg <= ~IO_voltage_reg; // IO voltage flip
     else //  No flip flag
         IO_voltage_reg <= IO_voltage_reg; // IO voltage constant
 end
@@ -179,7 +179,7 @@ reg IO_voltage_reg = 1'b0; // Initial state
 
 always @(posedge Clock) begin
     if ( count_value_flag )  //  Flip flag 
-        IO_voltage_reg <= ~IO_voltage_reg; // IO voltage filp
+        IO_voltage_reg <= ~IO_voltage_reg; // IO voltage flip
     else //  No flip flag
         IO_voltage_reg <= IO_voltage_reg; // IO voltage constant
 end
@@ -216,7 +216,7 @@ Since this is the first time we create it, the following dialog box will pop up.
 
 The ways to constraint the file can be get from this docs: [SUG935-1.3E_Gowin Design Physical Constraints User Guide.pdf](https://dl.sipeed.com/fileList/TANG/Nano%209K/6_Chip_Manual/EN/General%20Guide/SUG935-1.3E_Gowin%20Design%20Physical%20Constraints%20User%20Guide.pdf)
 
-Here we only use the IO Constranins method shown below to constrain the pins:
+Here we only use the IO Constraints method shown below to constrain the pins:
 
 ![floor_planner_ioconstrain](./../../../../../../../news/others/20k_lite_start/assets/floor_planner_ioconstrain.png)
 
@@ -228,7 +228,7 @@ Taking into consideration the IO screen printing on the ext_board, we decide to
 
 ![l14_port](./../../../../../../../news/others/20k_lite_start/assets/l14_port.png)
 
-So for the IO Constranins under the FloorPlanner interactive window, we fill in the following values for PORT and Location:
+So for the IO Constraints under the FloorPlanner interactive window, we fill in the following values for PORT and Location:
 
 ![io_constrain_value](./../../../../../../../news/others/20k_lite_start/assets/io_constrain_value.png)
 
@@ -240,7 +240,7 @@ Then we see there is a .cst file in our project, and its content are easy to und
 
 ### Place & Route
 
-After finishing constrainting, we run Place & Route. The purpose is to synthesize the generated netlist and our defined constraints to calculate the optimal solution through IDE, then allocate resources reasonably on the FPGA chip.
+After finishing constraining, we run Place & Route. The purpose is to synthesize the generated netlist and our defined constraints to calculate the optimal solution through IDE, then allocate resources reasonably on the FPGA chip.
 
 Double click Place&Route marked with red box to run.
 
@@ -297,7 +297,7 @@ Click OK to burn fpga.
 
 ### Burn to SRAM
 
-Normally this mode is used to verify biststream.
+Normally this mode is used to verify bitstream.
 
 Because of its fast burning characteristics so the use of more, but of course the power will lose data, so if you want to power on the running program you can't choose this mode.
 
@@ -315,10 +315,10 @@ Here we finished downloading into SRAM。
 
 ### Burn into Flash
 
-Burnning into sram is used for verifying biststream, but can't store program.
+Burning into sram is used for verifying biststream, but can't store program.
 If we want to run application at startup, we need to burn into flash.
 
-This steps are similar to the steps above of burnning to SRAM.
+This steps are similar to the steps above of burning to SRAM.
 
 Click the function box below Operation to open the device configuration interface, then select the External Flash Mode in the Access Mode to burn into external Flash. Finally click the three dots below to select the.fs we generated to download the firmware. Choose the three dots box below to select our generated `.fs` bitstream file. Generally speaking, bitstream firmware file is in the impl -> pnr directory. Finally, select the Generic Flash device from the following external Flash options.
 

docs/hardware/en/tang/tang-primer-20k/primer-20k.md

@@ -103,7 +103,7 @@ Buy it: [Aliexpress](https://www.aliexpress.com/item/1005004653308809.html)
 			<td style="text-align:left"></td>
 		</tr>
 		<tr>
-			<td style="text-align:left">Avaliable IO</td>
+			<td style="text-align:left">Available IO</td>
 			<td style="text-align:left">117</td>
 			<td style="text-align:left"></td>
 		</tr>
@@ -335,7 +335,7 @@ In this case, the default reason is that the wrong Dual-Purpose pin is enabled a
 
 Besides, if you have dock ext-board, this can be solved by the enable pin of dip switch. Here art the steps
 
-Firstlt, enable the core board, put the 1 switch on the dip switch down, then do something (like burnning fpga or erasing FPGA) in Programmer application, when the progress bar shows, switch the 1 switch on the dip switch up and down, after which you will find the progress bar works and finish your operations on fpga.
+Firstlt, enable the core board, put the 1 switch on the dip switch down, then do something (like burning fpga or erasing FPGA) in Programmer application, when the progress bar shows, switch the 1 switch on the dip switch up and down, after which you will find the progress bar works and finish your operations on fpga.
 
 <table>
 	<tr>

docs/hardware/zh/tang/Tang-Nano-4K/Nano-4K.md

@@ -18,7 +18,7 @@ Tang Nano 4K开发板板载的GW1NSR-LV4C，是一款系统级封装芯片，内
 | FPGA芯片         | GW1N-1-LV           | GW1NSR-LV4C       |
 | 逻辑单元         | 1152                | 4608              |
 | 寄存器           | 864                 | 3456              |
-| 硬核处理器       | 无                  | Coetex M3         |
+| 硬核处理器       | 无                  | Cortex-M3         |
 | Block SRAM(bits) | 72K                 | 180K              |
 | 用户闪存(bits)   | 96K                 | 256K              |
 | 锁相环PLL        | 1                   | 2                 |

pages/index/en/README.md

@@ -1,7 +1,7 @@
 ---
 title: Documentation
-keywords: sipeed wiki official, documentation, open source, open source hardware, Lichee, Lichee PI, AI, AIOT, edge AI, face recognization, maixpy, logan, Tang
+keywords: sipeed wiki official, documentation, open source, open source hardware, Lichee, Lichee PI, AI, AIoT, edge AI, face recognition, maixpy, logan, Tang
-desc: Wiki of Sipeed official, include software documentation and hardware infomation, and AIOT data etc.
+desc: Wiki of Sipeed official, include software documentation and hardware information, and AIoT data etc.
 id: home
 layout: home
 ---

share_docs/en/change_doc.md

@@ -13,7 +13,7 @@ So if you find something wrong or incorrect, you can edit this page.
 ![](./../assets/3.png)
 The content may show as below, just correct what you think need to be changed. 
 ![](./../assets/4.png)
-5. Pull requset after your finishing editing and add the reason why change it.   
+5. Pull request after your finishing editing and add the reason why change it.   
 ![](./../assets/5.png)
 
 We will merge request if ok.