mirror of
https://github.com/sipeed/LicheeRV-Nano-Build.git
synced 2026-11-09 18:04:55 -06:00
dbbad1938a
Update the vendored FSBL from Sophgo sg200x-dev commit 426d1e7eccce84b34169e5f21de7d6e7da1804a1 to 5a80c127cf614dea7f534d5b5352886a1c720d37, incorporating 24 upstream commits. Keep the local plat/sg200x symlink to cv181x. Import the upstream DDR, clock, storage and boot-image changes together with their platform support, prebuilt firmware and licensing files. All 935 upstream files match the target revision. Validation on LicheeRV Nano (SG2002/C906, SD, DDR3-1866 x16): - Cross-build BL2 with the existing Xuantie GCC 10.2.0 toolchain. - Repack FIP while preserving the installed OpenSBI and U-Boot byte for byte; verify headers, payload checksums, entry addresses and LZMA. - Software reboot and power-cycle boot succeed; memtester 16M 1 passes all 18 checks. Validation covers the FSBL update with existing later boot stages. Full firmware builds, A53 and video/HID acceptance are not covered.
210 lines
6.0 KiB
C
210 lines
6.0 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __EMMC_H__
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#define __EMMC_H__
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#include <stdint.h>
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#define EMMC_IDENTIFIED_TIMEOUT (1500)
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#define EMMC_CMD_TIMEOUT (100) // Follow same setting
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#define EMMC_DATA_CMD_TIMEOUT (10000) // Follow linux kernel setting
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#define EMMC_READY_FOR_DATA_TIMEOUT (5000) // Should not be happened
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#define EMMC_BLOCK_SIZE 512
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#define EMMC_BLOCK_MASK (EMMC_BLOCK_SIZE - 1)
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#define EMMC_BOOT_CLK_RATE (400 * 1000)
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#define EMMC_CMD0 0
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#define EMMC_CMD1 1
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#define EMMC_CMD2 2
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#define EMMC_CMD3 3
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#define EMMC_CMD6 6
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#define EMMC_CMD7 7
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#define EMMC_CMD8 8
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#define EMMC_CMD9 9
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#define EMMC_CMD12 12
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#define EMMC_CMD13 13
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#define EMMC_CMD17 17
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#define EMMC_CMD18 18
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#define EMMC_CMD23 23
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#define EMMC_CMD24 24
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#define EMMC_CMD25 25
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#define EMMC_CMD35 35
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#define EMMC_CMD36 36
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#define EMMC_CMD38 38
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#define OCR_POWERUP (1 << 31)
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#define OCR_BYTE_MODE (0 << 29)
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#define OCR_SECTOR_MODE (2 << 29)
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#define OCR_ACCESS_MODE_MASK (3 << 29)
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#define OCR_VDD_MIN_2V7 (0x1ff << 15)
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#define OCR_VDD_MIN_2V0 (0x7f << 8)
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#define OCR_VDD_MIN_1V7 (1 << 7)
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#define EMMC_RESPONSE_R1 1
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#define EMMC_RESPONSE_R1B 1
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#define EMMC_RESPONSE_R2 4
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#define EMMC_RESPONSE_R3 1
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#define EMMC_RESPONSE_R4 1
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#define EMMC_RESPONSE_R5 1
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#define EMMC_FIX_RCA 6 /* > 1 */
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#define RCA_SHIFT_OFFSET 16
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#define CMD_EXTCSD_PARTITION_CONFIG 179
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#define CMD_EXTCSD_BUS_WIDTH 183
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#define CMD_EXTCSD_HS_TIMING 185
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#define PART_CFG_BOOT_PARTITION1_ENABLE (1 << 3)
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#define PART_CFG_BOOT_PARTITION2_ENABLE (2 << 3)
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#define PART_CFG_PARTITION_BOOT1_ACCESS (1 << 0)
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#define PART_CFG_PARTITION_BOOT2_ACCESS (2 << 0)
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#define PART_CFG_PARTITION_RPMB_ACCESS (3 << 0)
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#define PART_CFG_PARTITION_GP1_ACCESS (4 << 0)
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#define PART_CFG_PARTITION_GP2_ACCESS (5 << 0)
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#define PART_CFG_PARTITION_GP3_ACCESS (6 << 0)
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#define PART_CFG_PARTITION_GP4_ACCESS (7 << 0)
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/* values in EXT CSD register */
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#define EMMC_BUS_WIDTH_1 0
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#define EMMC_BUS_WIDTH_4 1
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#define EMMC_BUS_WIDTH_8 2
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#define EMMC_BOOT_MODE_BACKWARD (0 << 3)
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#define EMMC_BOOT_MODE_HS_TIMING (1 << 3)
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#define EMMC_BOOT_MODE_DDR (2 << 3)
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#define EXTCSD_SET_CMD (0 << 24)
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#define EXTCSD_SET_BITS (1 << 24)
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#define EXTCSD_CLR_BITS (2 << 24)
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#define EXTCSD_WRITE_BYTES (3 << 24)
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#define EXTCSD_CMD(x) (((x) & 0xff) << 16)
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#define EXTCSD_VALUE(x) (((x) & 0xff) << 8)
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#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9)
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#define STATUS_READY_FOR_DATA (1 << 8)
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#define STATUS_SWITCH_ERROR (1 << 7)
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#define EMMC_GET_STATE(x) (((x) >> 9) & 0xf)
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#define EMMC_STATE_IDLE 0
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#define EMMC_STATE_READY 1
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#define EMMC_STATE_IDENT 2
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#define EMMC_STATE_STBY 3
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#define EMMC_STATE_TRAN 4
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#define EMMC_STATE_DATA 5
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#define EMMC_STATE_RCV 6
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#define EMMC_STATE_PRG 7
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#define EMMC_STATE_DIS 8
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#define EMMC_STATE_BTST 9
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#define EMMC_STATE_SLP 10
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#define EMMC_FLAG_CMD23 (1 << 0)
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typedef enum {
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EMMC_PARTITION_BOOT1 = 1,
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EMMC_PARTITION_BOOT2 = 2,
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EMMC_PARTITION_RPMB = 3,
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EMMC_PARTITION_GP1 = 4,
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EMMC_PARTITION_GP2 = 5,
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EMMC_PARTITION_GP3 = 6,
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EMMC_PARTITION_GP4 = 7,
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EMMC_PARTITION_UDA = 8,
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EMMC_PARTITION_MAX = 0xFF
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} emmc_partition_type;
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typedef struct emmc_cmd {
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unsigned int cmd_idx;
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unsigned int cmd_arg;
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unsigned int resp_type;
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unsigned int resp_data[4];
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} emmc_cmd_t;
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typedef struct emmc_ops {
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void (*init)(void);
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void (*reset)(void);
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int (*send_cmd)(emmc_cmd_t *cmd);
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int (*set_ios)(int clk, int width);
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int (*prepare)(int lba, uintptr_t buf, size_t size);
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int (*read)(int lba, uintptr_t buf, size_t size);
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int (*write)(int lba, const uintptr_t buf, size_t size);
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} emmc_ops_t;
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typedef struct emmc_cid {
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unsigned int manufacturing_date : 8;
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unsigned int product_serial_low : 24;
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unsigned short product_serial_high : 8;
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unsigned short product_revision : 8;
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char product_name[6];
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unsigned int oem_application_id : 8;
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unsigned int card_bga : 2;
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unsigned int reserverd_0 : 6;
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unsigned int manufacturer_id : 8;
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unsigned int reserved_1 : 8; /*dw spec page 231 response135-104 */
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} emmc_cid_t;
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typedef struct emmc_csd {
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/*data0*/
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unsigned int ecc : 2;
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unsigned int file_format : 2;
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unsigned int tmp_write_protect : 1;
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unsigned int perm_write_protect : 1;
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unsigned int copy : 1;
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unsigned int file_format_grp : 1;
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unsigned int content_prot_app : 1;
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unsigned int reserved_1 : 4;
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unsigned int write_bl_partial : 1;
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unsigned int write_bl_len : 4;
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unsigned int r2w_factor : 3;
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unsigned int default_ecc : 2;
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unsigned int wp_grp_enable : 1;
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unsigned int wp_grp_size : 5;
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unsigned int erase_grp_mult_low : 3;
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/*data1*/
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unsigned int erase_grp_mult_high : 2;
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unsigned int erase_grp_size : 5;
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unsigned int c_size_mult : 3;
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unsigned int vdd_w_curr_max : 3;
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unsigned int vdd_w_curr_min : 3;
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unsigned int vdd_r_curr_max : 3;
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unsigned int vdd_r_curr_min : 3;
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unsigned int c_size_low : 10;
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/*data2*/
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unsigned int c_size_high : 2;
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unsigned int reserved_2 : 2;
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unsigned int dsr_imp : 1;
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unsigned int read_blk_misalign : 1;
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unsigned int write_blk_misalign : 1;
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unsigned int read_bl_partial : 1;
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unsigned int read_bl_len : 4;
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unsigned int ccc : 12;
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unsigned int tran_speed : 8;
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/*data3*/
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unsigned int nsac : 8; /*bit 104*/
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unsigned int taac : 8;
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unsigned int reserved_3 : 2;
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unsigned int spec_vers : 4;
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unsigned int csd_structure : 2;
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unsigned int reserved_4 : 8; /*dw spec page 231 response135-104 */
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} emmc_csd_t;
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size_t emmc_read_blocks(int lba, uintptr_t buf, size_t size);
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size_t emmc_write_blocks(int lba, const uintptr_t buf, size_t size);
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size_t emmc_erase_blocks(int lba, size_t size);
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size_t emmc_partition_read_blocks(emmc_partition_type type, int lba, uintptr_t buf, size_t size);
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size_t emmc_partition_write_blocks(emmc_partition_type type, int lba, const uintptr_t buf, size_t size);
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size_t emmc_partition_erase_blocks(emmc_partition_type type, int lba, size_t size);
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int emmc_init(const emmc_ops_t *ops, int clk, int bus_width, unsigned int flags);
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size_t emmc_read_block_cmd8(int lba, uintptr_t buf, size_t size);
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size_t emmc_boot1_read_blocks(int lba, uintptr_t buf, size_t size);
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size_t emmc_boot1_write_blocks(int lba, uintptr_t buf, size_t size);
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void emmc_ut(void);
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#include <cv_emmc.h>
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#endif /* __EMMC_H__ */
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