mirror of
https://github.com/sipeed/LicheeRV-Nano-Build.git
synced 2026-11-09 18:04:55 -06:00
dbbad1938a
Update the vendored FSBL from Sophgo sg200x-dev commit 426d1e7eccce84b34169e5f21de7d6e7da1804a1 to 5a80c127cf614dea7f534d5b5352886a1c720d37, incorporating 24 upstream commits. Keep the local plat/sg200x symlink to cv181x. Import the upstream DDR, clock, storage and boot-image changes together with their platform support, prebuilt firmware and licensing files. All 935 upstream files match the target revision. Validation on LicheeRV Nano (SG2002/C906, SD, DDR3-1866 x16): - Cross-build BL2 with the existing Xuantie GCC 10.2.0 toolchain. - Repack FIP while preserving the installed OpenSBI and U-Boot byte for byte; verify headers, payload checksums, entry addresses and LZMA. - Software reboot and power-cycle boot succeed; memtester 16M 1 passes all 18 checks. Validation covers the FSBL update with existing later boot stages. Full firmware builds, A53 and video/HID acceptance are not covered.
192 lines
6.6 KiB
C
192 lines
6.6 KiB
C
/*
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CV_EMMC_H__
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#define __CV_EMMC_H__
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#include <emmc.h>
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#define SDHCI_DMA_ADDRESS 0x00
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#define SDHCI_BLOCK_SIZE 0x04
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#define SDHCI_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF))
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#define SDHCI_BLOCK_COUNT 0x06
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#define SDHCI_ARGUMENT 0x08
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#define SDHCI_TRANSFER_MODE 0x0C
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#define SDHCI_TRNS_DMA BIT(0)
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#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
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#define SDHCI_TRNS_ACMD12 BIT(2)
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#define SDHCI_TRNS_READ BIT(4)
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#define SDHCI_TRNS_MULTI BIT(5)
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#define SDHCI_TRNS_RESP_INT BIT(8)
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#define SDHCI_COMMAND 0x0E
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#define SDHCI_CMD_RESP_MASK 0x03
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#define SDHCI_CMD_CRC 0x08
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#define SDHCI_CMD_INDEX 0x10
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#define SDHCI_CMD_DATA 0x20
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#define SDHCI_CMD_ABORTCMD 0xC0
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#define SDHCI_CMD_RESP_NONE 0x00
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#define SDHCI_CMD_RESP_LONG 0x01
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#define SDHCI_CMD_RESP_SHORT 0x02
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#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
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#define SDHCI_MAKE_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff))
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#define SDHCI_RESPONSE_01 0x10
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#define SDHCI_RESPONSE_23 0x14
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#define SDHCI_RESPONSE_45 0x18
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#define SDHCI_RESPONSE_67 0x1C
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#define SDHCI_PSTATE 0x24
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#define SDHCI_CMD_INHIBIT BIT(0)
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#define SDHCI_CMD_INHIBIT_DAT BIT(1)
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#define SDHCI_HOST_CONTROL 0x28
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#define SDHCI_DAT_XFER_WIDTH BIT(1)
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#define SDHCI_EXT_DAT_XFER BIT(5)
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#define SDHCI_CTRL_DMA_MASK 0x18
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#define SDHCI_CTRL_SDMA 0x00
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#define SDHCI_PWR_CONTROL 0x29
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#define SDHCI_BUS_VOL_VDD1_1_8V 0xC
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#define SDHCI_BUS_VOL_VDD1_3_0V 0xE
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#define SDHCI_BUF_DATA_R 0x20
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#define SDHCI_BLOCK_GAP_CONTROL 0x2A
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#define SDHCI_CLK_CTRL 0x2C
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#define SDHCI_TOUT_CTRL 0x2E
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#define SDHCI_SOFTWARE_RESET 0x2F
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#define SDHCI_RESET_CMD 0x02
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#define SDHCI_RESET_DATA 0x04
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#define SDHCI_INT_STATUS 0x30
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#define SDHCI_ERR_INT_STATUS 0x32
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#define SDHCI_INT_CMD_COMPLETE BIT(0)
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#define SDHCI_INT_XFER_COMPLETE BIT(1)
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#define SDHCI_INT_DMA_END BIT(3)
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#define SDHCI_INT_BUF_RD_READY BIT(5)
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#define SDHCI_INT_ERROR BIT(15)
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#define SDHCI_INT_STATUS_EN 0x34
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#define SDHCI_ERR_INT_STATUS_EN 0x36
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#define SDHCI_INT_CMD_COMPLETE_EN BIT(0)
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#define SDHCI_INT_XFER_COMPLETE_EN BIT(1)
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#define SDHCI_INT_DMA_END_EN BIT(3)
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#define SDHCI_INT_ERROR_EN BIT(15)
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#define SDHCI_SIGNAL_ENABLE 0x38
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#define SDHCI_HOST_CONTROL2 0x3E
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#define SDHCI_HOST_VER4_ENABLE BIT(12)
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#define SDHCI_CAPABILITIES1 0x40
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#define SDHCI_CAPABILITIES2 0x44
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#define SDHCI_ADMA_SA_LOW 0x58
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#define SDHCI_ADMA_SA_HIGH 0x5C
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#define P_VENDOR_SPECIFIC_AREA 0xE8
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#define P_VENDOR2_SPECIFIC_AREA 0xEA
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#define VENDOR_EMMC_CTRL 0x0
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#define SDHCI_RESET_N BIT(8)
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#define SDHCI_PHY_R_OFFSET 0x300
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#define SDHCI_P_PHY_CNFG (SDHCI_PHY_R_OFFSET + 0x00)
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#define SDHCI_P_CMDPAD_CNFG (SDHCI_PHY_R_OFFSET + 0x04)
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#define SDHCI_P_DATPAD_CNFG (SDHCI_PHY_R_OFFSET + 0x06)
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#define SDHCI_P_CLKPAD_CNFG (SDHCI_PHY_R_OFFSET + 0x08)
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#define SDHCI_P_STBPAD_CNFG (SDHCI_PHY_R_OFFSET + 0x0A)
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#define SDHCI_P_RSTNPAD_CNFG (SDHCI_PHY_R_OFFSET + 0x0C)
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#define SDHCI_P_PADTEST_CNFG (SDHCI_PHY_R_OFFSET + 0x0E)
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#define SDHCI_P_PADTEST_OUT (SDHCI_PHY_R_OFFSET + 0x10)
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#define SDHCI_P_PADTEST_IN (SDHCI_PHY_R_OFFSET + 0x12)
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#define SDHCI_P_COMMDL_CNFG (SDHCI_PHY_R_OFFSET + 0x1C)
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#define SDHCI_P_SDCLKDL_CNFG (SDHCI_PHY_R_OFFSET + 0x1D)
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#define SDHCI_P_SDCLKDL_DC (SDHCI_PHY_R_OFFSET + 0x1E)
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#define SDHCI_P_SMPLDL_CNFG (SDHCI_PHY_R_OFFSET + 0x20)
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#define SDHCI_P_ATDL_CNFG (SDHCI_PHY_R_OFFSET + 0x21)
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#define SDHCI_P_DLL_CTRL (SDHCI_PHY_R_OFFSET + 0x24)
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#define SDHCI_P_DLL_CNFG1 (SDHCI_PHY_R_OFFSET + 0x25)
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#define SDHCI_P_DLL_CNFG2 (SDHCI_PHY_R_OFFSET + 0x26)
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#define SDHCI_P_DLLDL_CNFG (SDHCI_PHY_R_OFFSET + 0x28)
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#define SDHCI_P_DLL_OFFST (SDHCI_PHY_R_OFFSET + 0x29)
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#define SDHCI_P_DLLMST_TSTDC (SDHCI_PHY_R_OFFSET + 0x2A)
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#define SDHCI_P_DLLLBT_CNFG (SDHCI_PHY_R_OFFSET + 0x2C)
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#define SDHCI_P_DLL_STATUS (SDHCI_PHY_R_OFFSET + 0x2E)
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#define SDHCI_P_DLLDBG_MLKDC (SDHCI_PHY_R_OFFSET + 0x30)
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#define SDHCI_P_DLLDBG_SLKDC (SDHCI_PHY_R_OFFSET + 0x32)
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#define SDHCI_RX_DELAY_LINE (0x200 + 0x40) // P_VERDOR_SPECIFIC_AREA + 0x40(0x240) PHY_TX_RX_DLY
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#define REG_RX_SRC_SEL_MASK (0xFCFFFFFF) // 0x240 PHY_RX_SRC [25:24]
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#define REG_RX_SRC_SEL_CLR_MASK (0x3000000) // 0x240 PHY_RX_SRC [25:24]
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#define REG_RX_SRC_SEL_CLK_TX (0) // clk_tx
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#define REG_RX_SRC_SEL_CLK_TX_INV (1) // clk_tx_inv
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#define REG_RX_SRC_SEL_RES (2) // resvd
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#define REG_RX_SRC_SEL_PAD_CLK (1) // pad_clk
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#define REG_RX_SRC_SEL_SHIFT (24) // 0x240 PHY_RX_SRC [25:24]
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#define SDHCI_TX_DELAY_LINE (0x200 + 0x40) // P_VERDOR_SPECIFIC_AREA + 0x40(0x240) PHY_TX_RX_DLY
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#define REG_TX_SRC_SEL_MASK (0xFFFFFCFF) // 0x240 PHY_TX_SRC[9:8]
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#define REG_TX_SRC_SEL_CLR_MASK (0x300) // 0x240 PHY_TX_SRC[9:8]
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#define REG_TX_SRC_SEL_CLK_TX (0) // clk_tx
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#define REG_TX_SRC_SEL_CLK_TX_INV (1) // clk_tx_inv
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#define REG_TX_SRC_SEL_RES (2) // resvd
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#define REG_TX_SRC_SEL_PAD_CLK (1) // pad_clk
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#define REG_TX_SRC_SEL_SHIFT (8) // 0x240 PHY_TX_SRC[9:8]
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#define SDHCI_PHY_CONFIG (0x200 + 0x4C) // P_VERDOR_SPECIFIC_AREA + 0x4c(0x24c) PHY_TX_BPS
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#define REG_TX_BPS_SEL_MASK (0xFFFFFFFE) // 0x24c PHY_TX_BPS[0:0]
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#define REG_TX_BPS_SEL_CLR_MASK (0x1) // 0x24c PHY_TX_BPS[0:0]
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#define REG_TX_BPS_SEL_SHIFT (0) // 0x24c PHY_TX_BPS[0:0]
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#define REG_TX_BPS_SEL_BYPASS (1) // 0x24c PHY_TX_BPS inv
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#define PHY_CNFG_PHY_RSTN 0
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#define PHY_CNFG_PHY_PWRGOOD 1
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#define PHY_CNFG_PAD_SP 16
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#define PHY_CNFG_PAD_SP_MSK 0xf
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#define PHY_CNFG_PAD_SN 20
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#define PHY_CNFG_PAD_SN_MSK 0xf
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#define PAD_CNFG_RXSEL 0
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#define PAD_CNFG_RXSEL_MSK 0x7
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#define PAD_CNFG_WEAKPULL_EN 3
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#define PAD_CNFG_WEAKPULL_EN_MSK 0x3
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#define PAD_CNFG_TXSLEW_CTRL_P 5
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#define PAD_CNFG_TXSLEW_CTRL_P_MSK 0xf
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#define PAD_CNFG_TXSLEW_CTRL_N 9
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#define PAD_CNFG_TXSLEW_CTRL_N_MSK 0xf
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#define COMMDL_CNFG_DLSTEP_SEL 0
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#define COMMDL_CNFG_DLOUT_EN 1
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#define SDCLKDL_CNFG_EXTDLY_EN 0
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#define SDCLKDL_CNFG_BYPASS_EN 1
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#define SDCLKDL_CNFG_INPSEL_CNFG 2
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#define SDCLKDL_CNFG_INPSEL_CNFG_MSK 0x3
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#define SDCLKDL_CNFG_UPDATE_DC 4
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#define SMPLDL_CNFG_EXTDLY_EN 0
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#define SMPLDL_CNFG_BYPASS_EN 1
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#define SMPLDL_CNFG_INPSEL_CNFG 2
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#define SMPLDL_CNFG_INPSEL_CNFG_MSK 0x3
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#define SMPLDL_CNFG_INPSEL_OVERRIDE 4
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#define ATDL_CNFG_EXTDLY_EN 0
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#define ATDL_CNFG_BYPASS_EN 1
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#define ATDL_CNFG_INPSEL_CNFG 2
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#define ATDL_CNFG_INPSEL_CNFG_MSK 0x3
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#define GPIO_SWPORTA_DDR 0x004
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#define GPIO_SWPORTA_DR 0x000
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#define GPIO0_BASE 0x03020000
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#define GPIO1_BASE 0x03021000
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#define GPIO2_BASE 0x03022000
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#define GPIO3_BASE 0x03023000
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typedef struct bm_emmc_params {
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uintptr_t reg_base;
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uintptr_t vendor_base;
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uintptr_t desc_base;
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size_t desc_size;
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int clk_rate;
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int bus_width;
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unsigned int flags;
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} bm_emmc_params_t;
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void bm_emmc_phy_init(void);
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void bm_emmc_init(void);
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int bm_emmc_set_clk(int clk);
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void bm_emmc_read_data(unsigned int *buf);
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int bm_emmc_send_cmd_with_data_cmd8(emmc_cmd_t *cmd);
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#endif /* __CV_EMMC_H__ */
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