mirror of
https://github.com/sipeed/LicheeRV-Nano-Build.git
synced 2026-11-09 18:04:55 -06:00
dbbad1938a
Update the vendored FSBL from Sophgo sg200x-dev commit 426d1e7eccce84b34169e5f21de7d6e7da1804a1 to 5a80c127cf614dea7f534d5b5352886a1c720d37, incorporating 24 upstream commits. Keep the local plat/sg200x symlink to cv181x. Import the upstream DDR, clock, storage and boot-image changes together with their platform support, prebuilt firmware and licensing files. All 935 upstream files match the target revision. Validation on LicheeRV Nano (SG2002/C906, SD, DDR3-1866 x16): - Cross-build BL2 with the existing Xuantie GCC 10.2.0 toolchain. - Repack FIP while preserving the installed OpenSBI and U-Boot byte for byte; verify headers, payload checksums, entry addresses and LZMA. - Software reboot and power-cycle boot succeed; memtester 16M 1 passes all 18 checks. Validation covers the FSBL update with existing later boot stages. Full firmware builds, A53 and video/HID acceptance are not covered.
37 lines
758 B
C
37 lines
758 B
C
#ifndef __REG_CFG_H__
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#define __REG_CFG_H__
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// #include <stdint.h>
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// #include "ddr_sys.h"
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// #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
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struct regconf {
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uint32_t addr;
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uint32_t val;
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};
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struct regpatch {
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uint32_t addr;
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uint32_t mask;
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uint32_t val;
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};
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// #define DDR_CFG_TYPE_DDR3 1
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// #define DDR_CFG_TYPE_DDR2 2
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// #define DDR_CFG_TYPE_DDR3_AUTO 3
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// #define DDR_CFG_TYPE_DDR2_AUTO 4
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#ifdef DDR2_3
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extern struct regpatch ddr3_1866_patch_regs[];
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extern uint32_t ddr3_1866_patch_regs_count;
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extern struct regpatch ddr2_1333_patch_regs[];
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extern uint32_t ddr2_1333_patch_regs_count;
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#else
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extern struct regpatch *ddr_patch_regs;
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extern uint32_t ddr_patch_regs_count;
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#endif
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void ddr_patch_regs_init(void);
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#endif /* __REG_CFG_H__ */
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