mirror of
https://github.com/sipeed/LicheeRV-Nano-Build.git
synced 2026-11-09 18:04:55 -06:00
dbbad1938a
Update the vendored FSBL from Sophgo sg200x-dev commit 426d1e7eccce84b34169e5f21de7d6e7da1804a1 to 5a80c127cf614dea7f534d5b5352886a1c720d37, incorporating 24 upstream commits. Keep the local plat/sg200x symlink to cv181x. Import the upstream DDR, clock, storage and boot-image changes together with their platform support, prebuilt firmware and licensing files. All 935 upstream files match the target revision. Validation on LicheeRV Nano (SG2002/C906, SD, DDR3-1866 x16): - Cross-build BL2 with the existing Xuantie GCC 10.2.0 toolchain. - Repack FIP while preserving the installed OpenSBI and U-Boot byte for byte; verify headers, payload checksums, entry addresses and LZMA. - Software reboot and power-cycle boot succeed; memtester 16M 1 passes all 18 checks. Validation covers the FSBL update with existing later boot stages. Full firmware builds, A53 and video/HID acceptance are not covered.
50 lines
1.4 KiB
C
50 lines
1.4 KiB
C
#ifndef __DDR_PKG_INFO_H__
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#define __DDR_PKG_INFO_H__
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#include <stdint.h>
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#define DDR_VENDOR_UNKNOWN 0b00000
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#define DDR_VENDOR_NY_4G 0b00001
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#define DDR_VENDOR_NY_2G 0b00010
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#define DDR_VENDOR_ESMT_1G 0b00011
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#define DDR_VENDOR_ESMT_512M_DDR2 0b00100
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#define DDR_VENDOR_ETRON_1G 0b00101
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#define DDR_VENDOR_ESMT_2G 0b00110
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#define DDR_VENDOR_PM_2G 0b00111
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#define DDR_VENDOR_ETRON_N20_2G 0b01000
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#define DDR_VENDOR_ETRON_512M_DDR2 0b01001
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#define DDR_VENDOR_ESMT_N25_1G 0b01010
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#define DDR_VENDOR_NY_N20_1G 0b01011
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#define DDR_VENDOR_ESMT_N21_2G 0b01100
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#define DDR_VENDOR_ESMT_N19_4G 0b01101
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#define DDR_VENDOR_UNILC_N25_512M_DDR2 0b01110
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#define DDR_VENDOR_UNILC_N25_1G 0b01111
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#define DDR_VENDOR_UNILC_N21_2G 0b10000
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#define DDR_VENDOR_ETRON_N25_2G 0b10001
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#define DDR_VENDOR_EXTERN_DDR2_1815J 0b11110
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#define DDR_VENDOR_EXTERN_DDR3_1815J 0b11111
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#define DDR_VENDOR_EXTERN_DDR3_1815K 0b11101
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#define DDR_CAPACITY_UNKNOWN 0b000
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#define DDR_CAPACITY_512M 0b001
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#define DDR_CAPACITY_1G 0b010
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#define DDR_CAPACITY_2G 0b011
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#define DDR_CAPACITY_4G 0b100
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#define PKG_UNKNOWN 0b000
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#define PKG_QFN 0b001
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#define PKG_BGA 0b010
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#define DDR_TYPE_UNKNOWN 0
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#define DDR_TYPE_DDR2 1
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#define DDR_TYPE_DDR3 2
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extern uint32_t ddr_data_rate;
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void read_ddr_pkg_info(void);
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uint8_t get_ddr_vendor(void);
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uint8_t get_ddr_capacity(void);
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uint8_t get_pkg(void);
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uint8_t get_ddr_type(void);
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#endif /* __DDR_PKG_INFO_H__ */
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