mirror of
https://github.com/sipeed/LicheeRV-Nano-Build.git
synced 2026-11-09 18:04:55 -06:00
dbbad1938a
Update the vendored FSBL from Sophgo sg200x-dev commit 426d1e7eccce84b34169e5f21de7d6e7da1804a1 to 5a80c127cf614dea7f534d5b5352886a1c720d37, incorporating 24 upstream commits. Keep the local plat/sg200x symlink to cv181x. Import the upstream DDR, clock, storage and boot-image changes together with their platform support, prebuilt firmware and licensing files. All 935 upstream files match the target revision. Validation on LicheeRV Nano (SG2002/C906, SD, DDR3-1866 x16): - Cross-build BL2 with the existing Xuantie GCC 10.2.0 toolchain. - Repack FIP while preserving the installed OpenSBI and U-Boot byte for byte; verify headers, payload checksums, entry addresses and LZMA. - Software reboot and power-cycle boot succeed; memtester 16M 1 passes all 18 checks. Validation covers the FSBL update with existing later boot stages. Full firmware builds, A53 and video/HID acceptance are not covered.
101 lines
2.7 KiB
C
101 lines
2.7 KiB
C
#include <debug.h>
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#include <console.h>
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#include <platform.h>
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#include <bl2.h>
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#include <string.h>
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#include <delay_timer.h>
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#include <rom_api.h>
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#include <cpu.h>
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enum CHIP_CLK_MODE chip_clk_mode = CLK_ND;
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#ifdef RTOS_ENABLE_FREERTOS
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int init_comm_info(int ret)
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{
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struct transfer_config_t *transfer_config = (struct transfer_config_t *)MAILBOX_FIELD;
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struct transfer_config_t transfer_config_s;
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unsigned char *ptr = (unsigned char *)&transfer_config_s;
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unsigned short checksum = 0;
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/* mailbox field is 4 byte write access, and can not access byte by byte.
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* so init parameters and copy all to mailbox field together.
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*/
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transfer_config_s.conf_magic = RTOS_MAGIC_HEADER;
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transfer_config_s.conf_size = ((uint64_t)&transfer_config_s.checksum - (uint64_t)&transfer_config_s.conf_magic);
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transfer_config_s.isp_buffer_addr = CVIMMAP_ISP_MEM_BASE_ADDR;
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transfer_config_s.isp_buffer_size = CVIMMAP_ISP_MEM_BASE_SIZE;
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transfer_config_s.encode_img_addr = CVIMMAP_H26X_BITSTREAM_ADDR;
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transfer_config_s.encode_img_size = CVIMMAP_H26X_BITSTREAM_SIZE;
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transfer_config_s.encode_buf_addr = CVIMMAP_H26X_ENC_BUFF_ADDR;
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transfer_config_s.encode_buf_size = CVIMMAP_H26X_ENC_BUFF_SIZE;
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transfer_config_s.dump_print_enable = RTOS_DUMP_PRINT_ENABLE;
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transfer_config_s.dump_print_size_idx = RTOS_DUMP_PRINT_SZ_IDX;
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transfer_config_s.image_type = RTOS_FAST_IMAGE_TYPE;
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transfer_config_s.mcu_status = MCU_STATUS_NONOS_DONE;
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for (int i = 0; i < transfer_config_s.conf_size; i++) {
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checksum += ptr[i];
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}
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transfer_config_s.checksum = checksum;
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memcpy(transfer_config, &transfer_config_s, sizeof(struct transfer_config_t));
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return ret;
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}
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#endif
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#if !FSBL_SECURE_BOOT_SUPPORT
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int dec_verify_image(const void *image, size_t size, size_t dec_skip, struct fip_param1 *fip_param1)
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{
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return 0;
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}
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#endif
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void bl2_main(void)
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{
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uint32_t v = p_rom_api_get_boot_src();
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if (v == BOOT_SRC_UART) {
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console_init(0, PLAT_UART_CLK_IN_HZ, UART_DL_BAUDRATE);
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}
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ATF_STATE = ATF_STATE_BL2_MAIN;
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time_records->fsbl_start = read_time_ms();
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NOTICE("\nFSBL %s:%s\n", version_string, build_message);
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INFO("sw_info=0x%x\n", get_sw_info()->value);
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INFO("fip_param1: param_cksum=0x%x param2_loadaddr=0x%x\n", fip_param1->param_cksum,
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fip_param1->param2_loadaddr);
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INFO("CP_STATE_REG=0x%x\n", mmio_read_32(0x0E000018));
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// print_sram_log();
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lock_efuse_chipsn();
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setup_dl_flag();
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#ifdef SWITCH_32K_XTAL
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switch_rtc_mode_1st_stage();
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#endif
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set_rtc_en_registers();
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#ifdef OD_CLK_SEL
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chip_clk_mode = CLK_OD;
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#else
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#ifdef VC_CLK_OVERDRIVE
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chip_clk_mode = CLK_VC_OD;
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#endif
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#endif
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#ifdef CONFIG_SUSPEND
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#ifndef NO_DDR_CFG //for fpga
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jump_to_warmboot_entry();
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#endif
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#endif
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load_ddr();
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load_rest();
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NOTICE("BL2 end.\n");
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while (1)
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;
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}
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