mirror of
https://github.com/sipeed/LicheeRV-Nano-Build.git
synced 2026-11-09 18:04:55 -06:00
dbbad1938a
Update the vendored FSBL from Sophgo sg200x-dev commit 426d1e7eccce84b34169e5f21de7d6e7da1804a1 to 5a80c127cf614dea7f534d5b5352886a1c720d37, incorporating 24 upstream commits. Keep the local plat/sg200x symlink to cv181x. Import the upstream DDR, clock, storage and boot-image changes together with their platform support, prebuilt firmware and licensing files. All 935 upstream files match the target revision. Validation on LicheeRV Nano (SG2002/C906, SD, DDR3-1866 x16): - Cross-build BL2 with the existing Xuantie GCC 10.2.0 toolchain. - Repack FIP while preserving the installed OpenSBI and U-Boot byte for byte; verify headers, payload checksums, entry addresses and LZMA. - Software reboot and power-cycle boot succeed; memtester 16M 1 passes all 18 checks. Validation covers the FSBL update with existing later boot stages. Full firmware builds, A53 and video/HID acceptance are not covered.
94 lines
2.0 KiB
Makefile
94 lines
2.0 KiB
Makefile
#
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# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# Enable workarounds for selected Cortex-A53 errata
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ERRATA_A53_835769 := 1
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ERRATA_A53_843419 := 1
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ERRATA_A53_855873 := 1
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PAGE_SIZE_64KB := 1
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TEST_FROM_SPINOR1 := 0
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DEFINES += -DLZ4_USER_MEMORY_FUNCTIONS=1
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# overdrive clock setting
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ifeq ($(OD_CLK_SEL),y)
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$(eval $(call add_define,OD_CLK_SEL))
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else ifeq ($(VC_CLK_OVERDRIVE),y)
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$(eval $(call add_define,VC_CLK_OVERDRIVE))
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endif
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# ifeq ($(FSBL_SECURE_BOOT_SUPPORT),1)
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DEFINES += \
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-DNO_ALLOCS \
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-DARGTYPE=3 \
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-DLTC_NO_FILE \
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-DLTM_NO_FILE \
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-DLTM_DESC \
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-DLTC_SOURCE
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CRYPT_INCLUDES := \
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-Ilib/libtommath \
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-Ilib/libtomcrypt/src/headers \
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-Ilib/BigDigits
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CRYPT_SOURCES := \
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lib/BigDigits/bigdigits.c \
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lib/libtomcrypt/src/hashes/sha2/sha256.c
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# endif
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INCLUDES += \
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-Iinclude \
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${CPU_INCLUDES} \
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-Iplat/ \
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-Iplat/${CHIP_ARCH}/include/uart \
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-Iplat/${CHIP_ARCH}/include/usb \
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-Iplat/${CHIP_ARCH}/include \
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-Iplat/${CHIP_ARCH}/include/${BOOT_CPU} \
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-Ilib/utils \
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-Ilib/lzma \
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-Ilib/lz4 \
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-Ilib/crc \
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${STDLIB_INCLUDES} \
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${CRYPT_INCLUDES}
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BL_COMMON_SOURCES = \
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${CPU_SOURCES} \
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lib/tf_printf/tf_printf.c \
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plat/${CHIP_ARCH}/platform.c \
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plat/${CHIP_ARCH}/security/security.c \
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${STDLIB_SRCS} \
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${CRYPT_SOURCES}
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DECOMPRESSION_SOURCES = \
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lib/lzma/LzmaDec.c \
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lib/lz4/lz4_all.c \
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lib/lz4/xxhash.c
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BL2_SRCS = \
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${BL_COMMON_SOURCES} \
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plat/${CHIP_ARCH}/platform_device.c \
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plat/${CHIP_ARCH}/bl2/bl2_opt.c \
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plat/${CHIP_ARCH}/bl2/cvi_spinand.c \
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lib/utils/decompress.c \
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plat/${CHIP_ARCH}/usb/cps_cvi.c \
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plat/${CHIP_ARCH}/usb/usb_tty.c \
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plat/${CHIP_ARCH}/usb/dwc2_udc_otg.c \
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plat/${CHIP_ARCH}/usb/dwc2_udc_otg_xfer_dma.c \
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plat/${CHIP_ARCH}/usb/cv_usb.c \
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lib/crc/crc16.c \
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${DECOMPRESSION_SOURCES}
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BL2_SOURCES = \
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${BL2_CPU_SOURCES} \
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${BL2_SRCS} \
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plat/${CHIP_ARCH}/bl2/bl2_main.c
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include plat/${CHIP_ARCH}/ddr/ddr.mk
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BL2_LINKERFILE := plat/${CHIP_ARCH}/bl2/bl2.ld.S
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#BL2_RLS_OBJS := plat/${CHIP_ARCH}/bl2_objs/${PROJECT_FULLNAME}/bl2/*.o
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