mirror of
https://github.com/sipeed/LicheeRV-Nano-Build.git
synced 2026-11-09 18:04:55 -06:00
dbbad1938a
Update the vendored FSBL from Sophgo sg200x-dev commit 426d1e7eccce84b34169e5f21de7d6e7da1804a1 to 5a80c127cf614dea7f534d5b5352886a1c720d37, incorporating 24 upstream commits. Keep the local plat/sg200x symlink to cv181x. Import the upstream DDR, clock, storage and boot-image changes together with their platform support, prebuilt firmware and licensing files. All 935 upstream files match the target revision. Validation on LicheeRV Nano (SG2002/C906, SD, DDR3-1866 x16): - Cross-build BL2 with the existing Xuantie GCC 10.2.0 toolchain. - Repack FIP while preserving the installed OpenSBI and U-Boot byte for byte; verify headers, payload checksums, entry addresses and LZMA. - Software reboot and power-cycle boot succeed; memtester 16M 1 passes all 18 checks. Validation covers the FSBL update with existing later boot stages. Full firmware builds, A53 and video/HID acceptance are not covered.
405 lines
11 KiB
C
405 lines
11 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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#include <stddef.h>
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#include <string.h>
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#include <stdint.h>
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#include <delay_timer.h>
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#include "mmio.h"
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#include "reg_soc.h"
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#include "phy_pll_init.h"
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#include "ddr_sys.h"
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#include "ddr_suspend.h"
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#include "bitwise_ops.h"
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// #include "regconfig.h"
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#include "rtc.h"
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#include "cvx16_dram_cap_check.h"
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#include <platform_def.h>
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#ifdef DDR2_3
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#include <ddr3_1866_init.h>
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#include <ddr2_1333_init.h>
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#else
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#include <ddr_init.h>
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#endif
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#define susp_read_csr(reg) ({ unsigned long __tmp; \
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asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
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__tmp; })
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SUSPEND_DATA uint32_t start, delta, total_delta;
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void susp_udelay(uint32_t delay)
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{
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start = (uint32_t)(~susp_read_csr(time));
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total_delta = (delay * 25);
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mmio_write_32(REG_GP_REG2, total_delta);
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do {
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/*
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* If the timer value wraps around, the subtraction will
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* overflow and it will still give the correct result.
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*/
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delta = start - (uint32_t)(~susp_read_csr(time)); /* Decreasing counter */
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} while (delta < total_delta);
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}
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void ddr_suspend_entry(void)
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{
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ddr_sys_suspend_sus_res();
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rtc_clr_ddr_pwrok();
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rtc_clr_rmio_pwrok();
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#ifndef SUSPEND_USE_WDG_RST
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rtc_req_suspend();
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#else
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rtc_req_wdg_rst();
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#endif
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}
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void ddr_sys_suspend_sus_res(void)
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{
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cvx16_ddrc_suspend_sus_res();
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cvx16_ddr_phyd_save_sus_res(0x05026800);
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cvx16_ddr_phya_pd_sus_res();
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}
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void cvx16_ddrc_suspend_sus_res(void)
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{
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uint32_t rddata;
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// Write 0 to PCTRL_n.port_en
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for (int i = 0; i < 4; i++)
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mmio_wr32(cfg_base + 0x490 + 0xb0 * i, 0x0);
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while (1) {
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rddata = mmio_rd32(cfg_base + 0x3fc);
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if (rddata == 0)
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break;
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}
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//Write 1 to PWRCTL.selfref_sw
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rddata = mmio_rd32(cfg_base + 0x30);
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rddata = FIELD_SET(rddata, 1, 5, 5);
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mmio_wr32(cfg_base + 0x30, rddata);
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//Poll STAT.selfref_type= 2'b10
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//Poll STAT.selfref_state = 0b10 (LPDDR4 only)
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while (1) {
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rddata = mmio_rd32(cfg_base + 0x4);
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if (FIELD_GET(rddata, 5, 4) == 0x2)
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break;
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}
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}
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void cvx16_ddr_phya_pd_sus_res(void)
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{
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uint32_t rddata;
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// ----------- PHY oen/pd reset ----------------
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//OEN
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//param_phyd_tx_ca_oenz 0
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//param_phyd_tx_ca_clk0_oenz 8
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//param_phyd_tx_ca_clk1_oenz 16
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rddata = 0x00010101;
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mmio_wr32(0x0130 + PHYD_BASE_ADDR, rddata);
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//PD
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//TOP_REG_TX_CA_PD_CA 22 0
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//TOP_REG_TX_CA_PD_CKE0 24 24
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//TOP_REG_TX_CLK_PD_CLK0 26 26
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//TOP_REG_TX_CA_PD_CSB0 28 28
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//TOP_REG_TX_CA_PD_RESETZ 30 30
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//TOP_REG_TX_ZQ_PD 31 31
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//rddata[31:0] = 0x947f_ffff;
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rddata = 0x947fffff;
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mmio_wr32(0x40 + CV_DDR_PHYD_APB, rddata);
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//TOP_REG_TX_BYTE0_PD 0
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//TOP_REG_TX_BYTE1_PD 1
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rddata = 0x00000003;
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mmio_wr32(0x00 + CV_DDR_PHYD_APB, rddata);
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//OEN
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//param_phyd_sel_cke_oenz <= `PI_SD int_regin[0];
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rddata = mmio_rd32(0x0154 + PHYD_BASE_ADDR);
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//rddata[0] = 0b1;
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rddata = FIELD_SET(rddata, 1, 0, 0);
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mmio_wr32(0x0154 + PHYD_BASE_ADDR, rddata);
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//PD
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//All PHYA PD=0
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rddata = 0xffffffff;
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mmio_wr32(0x40 + CV_DDR_PHYD_APB, rddata);
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//PLL PD
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rddata = mmio_rd32(0x0C + CV_DDR_PHYD_APB);
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//rddata[15] = 1; //TOP_REG_DDRPLL_PD
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rddata = FIELD_SET(rddata, 1, 15, 15);
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mmio_wr32(0x0C + CV_DDR_PHYD_APB, rddata);
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// ----------- PHY oen/pd reset ----------------
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//reg_ddr_ssc_syn_src_en =0
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rddata = mmio_rd32(0x40 + 0x03002900);
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rddata = FIELD_SET(rddata, 0, 1, 1); //reg_ddr_ssc_syn_src_en
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mmio_wr32(0x40 + 0x03002900, rddata);
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}
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SUSPEND_DATA struct reg save_phy_regs[] = {
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{0x0 + PHYD_BASE_ADDR, 0x0},
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{0x4 + PHYD_BASE_ADDR, 0x0},
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{0x8 + PHYD_BASE_ADDR, 0x0},
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{0xc + PHYD_BASE_ADDR, 0x0},
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{0x10 + PHYD_BASE_ADDR, 0x0},
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{0x14 + PHYD_BASE_ADDR, 0x0},
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{0x18 + PHYD_BASE_ADDR, 0x0},
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{0x1c + PHYD_BASE_ADDR, 0x0},
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{0x20 + PHYD_BASE_ADDR, 0x0},
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{0x24 + PHYD_BASE_ADDR, 0x0},
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{0x28 + PHYD_BASE_ADDR, 0x0},
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{0x2c + PHYD_BASE_ADDR, 0x0},
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{0x40 + PHYD_BASE_ADDR, 0x0},
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{0x44 + PHYD_BASE_ADDR, 0x0},
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{0x48 + PHYD_BASE_ADDR, 0x0},
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{0x4c + PHYD_BASE_ADDR, 0x0},
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{0x50 + PHYD_BASE_ADDR, 0x0},
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{0x54 + PHYD_BASE_ADDR, 0x0},
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{0x58 + PHYD_BASE_ADDR, 0x0},
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{0x5c + PHYD_BASE_ADDR, 0x0},
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{0x60 + PHYD_BASE_ADDR, 0x0},
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{0x64 + PHYD_BASE_ADDR, 0x0},
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{0x68 + PHYD_BASE_ADDR, 0x0},
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{0x70 + PHYD_BASE_ADDR, 0x0},
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{0x74 + PHYD_BASE_ADDR, 0x0},
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{0x80 + PHYD_BASE_ADDR, 0x0},
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{0x84 + PHYD_BASE_ADDR, 0x0},
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{0x88 + PHYD_BASE_ADDR, 0x0},
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{0x8c + PHYD_BASE_ADDR, 0x0},
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{0x90 + PHYD_BASE_ADDR, 0x0},
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{0x94 + PHYD_BASE_ADDR, 0x0},
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{0xa0 + PHYD_BASE_ADDR, 0x0},
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{0xa4 + PHYD_BASE_ADDR, 0x0},
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{0xa8 + PHYD_BASE_ADDR, 0x0},
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{0xac + PHYD_BASE_ADDR, 0x0},
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{0xb0 + PHYD_BASE_ADDR, 0x0},
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{0xb4 + PHYD_BASE_ADDR, 0x0},
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{0xb8 + PHYD_BASE_ADDR, 0x0},
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{0xbc + PHYD_BASE_ADDR, 0x0},
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{0xf8 + PHYD_BASE_ADDR, 0x0},
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{0xfc + PHYD_BASE_ADDR, 0x0},
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{0x100 + PHYD_BASE_ADDR, 0x0},
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{0x104 + PHYD_BASE_ADDR, 0x0},
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{0x10c + PHYD_BASE_ADDR, 0x0},
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{0x110 + PHYD_BASE_ADDR, 0x0},
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{0x114 + PHYD_BASE_ADDR, 0x0},
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{0x118 + PHYD_BASE_ADDR, 0x0},
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{0x11c + PHYD_BASE_ADDR, 0x0},
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{0x120 + PHYD_BASE_ADDR, 0x0},
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{0x124 + PHYD_BASE_ADDR, 0x0},
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{0x128 + PHYD_BASE_ADDR, 0x0},
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{0x12c + PHYD_BASE_ADDR, 0x0},
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{0x130 + PHYD_BASE_ADDR, 0x0},
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{0x134 + PHYD_BASE_ADDR, 0x0},
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{0x138 + PHYD_BASE_ADDR, 0x0},
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{0x140 + PHYD_BASE_ADDR, 0x0},
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{0x144 + PHYD_BASE_ADDR, 0x0},
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{0x148 + PHYD_BASE_ADDR, 0x0},
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{0x14c + PHYD_BASE_ADDR, 0x0},
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{0x150 + PHYD_BASE_ADDR, 0x0},
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{0x154 + PHYD_BASE_ADDR, 0x0},
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{0x158 + PHYD_BASE_ADDR, 0x0},
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{0x15c + PHYD_BASE_ADDR, 0x0},
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{0x164 + PHYD_BASE_ADDR, 0x0},
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{0x168 + PHYD_BASE_ADDR, 0x0},
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{0x16c + PHYD_BASE_ADDR, 0x0},
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{0x170 + PHYD_BASE_ADDR, 0x0},
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{0x174 + PHYD_BASE_ADDR, 0x0},
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{0x180 + PHYD_BASE_ADDR, 0x0},
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{0x184 + PHYD_BASE_ADDR, 0x0},
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{0x188 + PHYD_BASE_ADDR, 0x0},
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{0x18c + PHYD_BASE_ADDR, 0x0},
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{0x190 + PHYD_BASE_ADDR, 0x0},
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{0x200 + PHYD_BASE_ADDR, 0x0},
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{0x204 + PHYD_BASE_ADDR, 0x0},
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{0x208 + PHYD_BASE_ADDR, 0x0},
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{0x220 + PHYD_BASE_ADDR, 0x0},
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{0x224 + PHYD_BASE_ADDR, 0x0},
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{0x228 + PHYD_BASE_ADDR, 0x0},
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{0x400 + PHYD_BASE_ADDR, 0x0},
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{0x404 + PHYD_BASE_ADDR, 0x0},
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{0x408 + PHYD_BASE_ADDR, 0x0},
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{0x40c + PHYD_BASE_ADDR, 0x0},
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{0x410 + PHYD_BASE_ADDR, 0x0},
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{0x414 + PHYD_BASE_ADDR, 0x0},
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{0x418 + PHYD_BASE_ADDR, 0x0},
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{0x41c + PHYD_BASE_ADDR, 0x0},
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{0x500 + PHYD_BASE_ADDR, 0x0},
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{0x504 + PHYD_BASE_ADDR, 0x0},
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{0x508 + PHYD_BASE_ADDR, 0x0},
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{0x50c + PHYD_BASE_ADDR, 0x0},
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{0x510 + PHYD_BASE_ADDR, 0x0},
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{0x514 + PHYD_BASE_ADDR, 0x0},
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{0x518 + PHYD_BASE_ADDR, 0x0},
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{0x51c + PHYD_BASE_ADDR, 0x0},
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{0x520 + PHYD_BASE_ADDR, 0x0},
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{0x540 + PHYD_BASE_ADDR, 0x0},
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{0x544 + PHYD_BASE_ADDR, 0x0},
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{0x548 + PHYD_BASE_ADDR, 0x0},
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{0x54c + PHYD_BASE_ADDR, 0x0},
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{0x550 + PHYD_BASE_ADDR, 0x0},
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{0x554 + PHYD_BASE_ADDR, 0x0},
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{0x558 + PHYD_BASE_ADDR, 0x0},
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{0x55c + PHYD_BASE_ADDR, 0x0},
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{0x560 + PHYD_BASE_ADDR, 0x0},
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{0x900 + PHYD_BASE_ADDR, 0x0},
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{0x904 + PHYD_BASE_ADDR, 0x0},
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{0x908 + PHYD_BASE_ADDR, 0x0},
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{0x90c + PHYD_BASE_ADDR, 0x0},
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{0x910 + PHYD_BASE_ADDR, 0x0},
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{0x914 + PHYD_BASE_ADDR, 0x0},
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{0x918 + PHYD_BASE_ADDR, 0x0},
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{0x91c + PHYD_BASE_ADDR, 0x0},
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{0x920 + PHYD_BASE_ADDR, 0x0},
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{0x924 + PHYD_BASE_ADDR, 0x0},
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{0x928 + PHYD_BASE_ADDR, 0x0},
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{0x92c + PHYD_BASE_ADDR, 0x0},
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{0x930 + PHYD_BASE_ADDR, 0x0},
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{0x934 + PHYD_BASE_ADDR, 0x0},
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{0x938 + PHYD_BASE_ADDR, 0x0},
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{0x940 + PHYD_BASE_ADDR, 0x0},
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{0x944 + PHYD_BASE_ADDR, 0x0},
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{0x948 + PHYD_BASE_ADDR, 0x0},
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{0x94c + PHYD_BASE_ADDR, 0x0},
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{0x950 + PHYD_BASE_ADDR, 0x0},
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{0x954 + PHYD_BASE_ADDR, 0x0},
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{0x958 + PHYD_BASE_ADDR, 0x0},
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{0x95c + PHYD_BASE_ADDR, 0x0},
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{0x960 + PHYD_BASE_ADDR, 0x0},
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{0x964 + PHYD_BASE_ADDR, 0x0},
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{0x968 + PHYD_BASE_ADDR, 0x0},
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{0x96c + PHYD_BASE_ADDR, 0x0},
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{0x970 + PHYD_BASE_ADDR, 0x0},
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{0x974 + PHYD_BASE_ADDR, 0x0},
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{0x978 + PHYD_BASE_ADDR, 0x0},
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{0x97c + PHYD_BASE_ADDR, 0x0},
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{0x980 + PHYD_BASE_ADDR, 0x0},
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{0xa00 + PHYD_BASE_ADDR, 0x0},
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{0xa04 + PHYD_BASE_ADDR, 0x0},
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{0xa08 + PHYD_BASE_ADDR, 0x0},
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{0xa0c + PHYD_BASE_ADDR, 0x0},
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{0xa10 + PHYD_BASE_ADDR, 0x0},
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{0xa14 + PHYD_BASE_ADDR, 0x0},
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{0xa18 + PHYD_BASE_ADDR, 0x0},
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{0xa1c + PHYD_BASE_ADDR, 0x0},
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{0xa20 + PHYD_BASE_ADDR, 0x0},
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{0xa24 + PHYD_BASE_ADDR, 0x0},
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{0xa28 + PHYD_BASE_ADDR, 0x0},
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{0xa2c + PHYD_BASE_ADDR, 0x0},
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{0xa30 + PHYD_BASE_ADDR, 0x0},
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{0xa34 + PHYD_BASE_ADDR, 0x0},
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{0xa38 + PHYD_BASE_ADDR, 0x0},
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{0xa3c + PHYD_BASE_ADDR, 0x0},
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{0xa40 + PHYD_BASE_ADDR, 0x0},
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{0xa44 + PHYD_BASE_ADDR, 0x0},
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{0xa48 + PHYD_BASE_ADDR, 0x0},
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{0xa4c + PHYD_BASE_ADDR, 0x0},
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{0xa50 + PHYD_BASE_ADDR, 0x0},
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{0xa54 + PHYD_BASE_ADDR, 0x0},
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{0xa58 + PHYD_BASE_ADDR, 0x0},
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{0xa5c + PHYD_BASE_ADDR, 0x0},
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{0xa60 + PHYD_BASE_ADDR, 0x0},
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{0xa64 + PHYD_BASE_ADDR, 0x0},
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{0xa68 + PHYD_BASE_ADDR, 0x0},
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{0xa6c + PHYD_BASE_ADDR, 0x0},
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{0xa70 + PHYD_BASE_ADDR, 0x0},
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{0xa74 + PHYD_BASE_ADDR, 0x0},
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{0xa78 + PHYD_BASE_ADDR, 0x0},
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{0xa7c + PHYD_BASE_ADDR, 0x0},
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{0xb00 + PHYD_BASE_ADDR, 0x0},
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{0xb04 + PHYD_BASE_ADDR, 0x0},
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{0xb08 + PHYD_BASE_ADDR, 0x0},
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{0xb0c + PHYD_BASE_ADDR, 0x0},
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{0xb10 + PHYD_BASE_ADDR, 0x0},
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{0xb14 + PHYD_BASE_ADDR, 0x0},
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{0xb18 + PHYD_BASE_ADDR, 0x0},
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{0xb1c + PHYD_BASE_ADDR, 0x0},
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{0xb20 + PHYD_BASE_ADDR, 0x0},
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{0xb24 + PHYD_BASE_ADDR, 0x0},
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{0xb30 + PHYD_BASE_ADDR, 0x0},
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{0xb34 + PHYD_BASE_ADDR, 0x0},
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{0xb38 + PHYD_BASE_ADDR, 0x0},
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{0xb3c + PHYD_BASE_ADDR, 0x0},
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{0xb40 + PHYD_BASE_ADDR, 0x0},
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{0xb44 + PHYD_BASE_ADDR, 0x0},
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{0xb48 + PHYD_BASE_ADDR, 0x0},
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{0xb4c + PHYD_BASE_ADDR, 0x0},
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{0xb50 + PHYD_BASE_ADDR, 0x0},
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{0xb54 + PHYD_BASE_ADDR, 0x0},
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{REG_GP_REG3, 0x0}, //reserve for chipid suspend resume
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{0xDEADBEEF, 0xDEADBEEF},
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};
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void cvx16_ddr_phyd_save_sus_res(uint32_t rtc_sram_base)
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{
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// struct reg *psave_phy_regs = (struct reg *)rtc_sram_base;
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uintptr_t temp = rtc_sram_base;
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struct reg *psave_phy_regs = (struct reg *)temp;
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int i;
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for (i = 0; i < ARRAY_SIZE(save_phy_regs) - 1; i++) {
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psave_phy_regs[i].addr = save_phy_regs[i].addr;
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psave_phy_regs[i].val = mmio_rd32(save_phy_regs[i].addr);
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}
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}
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void rtc_clr_ddr_pwrok(void)
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{
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mmio_clrbits_32(REG_RTC_BASE + RTC_PG_REG, 0x00000001);
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}
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void rtc_clr_rmio_pwrok(void)
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{
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mmio_clrbits_32(REG_RTC_BASE + RTC_PG_REG, 0x00000002);
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}
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#ifndef SUSPEND_USE_WDG_RST
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void rtc_req_suspend(void)
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{
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//info("Send suspend request\n");
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/* Enable power suspend wakeup source mask */
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mmio_write_32(REG_RTC_BASE + 0x3C, 0x1); // 1 = select prdata from 32K domain
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mmio_write_32(REG_RTC_CTRL_BASE + RTC_CTRL0_UNLOCKKEY, 0xAB18);
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mmio_write_32(REG_RTC_BASE + RTC_EN_SUSPEND_REQ, 0x01);
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while (mmio_read_32(REG_RTC_BASE + RTC_EN_SUSPEND_REQ) != 0x01)
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;
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while (1) {
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/* Send suspend request to RTC*/
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susp_udelay(1000);
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mmio_write_32(REG_RTC_CTRL_BASE + RTC_CTRL0, 0x00800080);
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}
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}
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#else
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void rtc_req_wdg_rst(void)
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{
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uint32_t write_data = 0;
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write_data = mmio_rd32(REG_RTC_CTRL_BASE + 0x18); //rtcsys_rst_ctrl
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write_data = write_data | (0x01 << 24); //reg_rtcsys_reset_en
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mmio_wr32(REG_RTC_CTRL_BASE + 0x18, write_data); //
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mmio_wr32(REG_RTC_BASE + 0xE8, 0x04); // RTC_DB_REQ_WARM_RST
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mmio_wr32(REG_RTC_BASE + 0xE0, 0x01); // RTC_EN_WDG_RST_REQ
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mmio_wr32(REG_RTC_CTRL_BASE + 0x60, 0xA5); // write dummy register
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mmio_wr32(REG_RTC_CTRL_BASE + 0x04, 0xAB18); // rtc_ctrl0_unlockkey
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write_data = mmio_rd32(REG_RTC_CTRL_BASE + 0x08); // rtc_ctrl0
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//req_shdn = rtc_ctrl0[0];
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//req_sw_thm_shdn = rtc_ctrl0[1];
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//hw_thm_shdn_en = rtc_ctrl0[2];
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//req_pwr_cyc = rtc_ctrl0[3];
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//req_warm_rst = rtc_ctrl0[4];
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//req_sw_wdg_rst = rtc_ctrl0[5];
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//hw_wdg_rst_en = rtc_ctrl0[6];
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//req_suspend = rtc_ctrl0[7];
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write_data = 0xffff0000 | write_data | (0x01 << 5);
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// printf("[RTC] ----> Set req_sw_wdg_rst to 1 by register setting\n");
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mmio_wr32(REG_RTC_CTRL_BASE + 0x08, write_data); //rtc_ctrl0
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}
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#endif
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