mirror of
https://github.com/sipeed/LicheeRV-Nano-Build.git
synced 2026-11-09 18:04:55 -06:00
dbbad1938a
Update the vendored FSBL from Sophgo sg200x-dev commit 426d1e7eccce84b34169e5f21de7d6e7da1804a1 to 5a80c127cf614dea7f534d5b5352886a1c720d37, incorporating 24 upstream commits. Keep the local plat/sg200x symlink to cv181x. Import the upstream DDR, clock, storage and boot-image changes together with their platform support, prebuilt firmware and licensing files. All 935 upstream files match the target revision. Validation on LicheeRV Nano (SG2002/C906, SD, DDR3-1866 x16): - Cross-build BL2 with the existing Xuantie GCC 10.2.0 toolchain. - Repack FIP while preserving the installed OpenSBI and U-Boot byte for byte; verify headers, payload checksums, entry addresses and LZMA. - Software reboot and power-cycle boot succeed; memtester 16M 1 passes all 18 checks. Validation covers the FSBL update with existing later boot stages. Full firmware builds, A53 and video/HID acceptance are not covered.
687 lines
26 KiB
C
687 lines
26 KiB
C
#include <mmio.h>
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#include <reg_soc.h>
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#include <ddr_sys.h>
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#include <ddr_pkg_info.h>
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void cvx16_pinmux(void)
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{
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uartlog("%s\n", __func__);
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// ddr_debug_wr32(0x4E);
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// ddr_debug_num_write();
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#ifndef DDR_SIM
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switch (get_ddr_vendor()) {
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case DDR_VENDOR_NY_4G:
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// DDR3_4G
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mmio_write_32(0x0000 + PHYD_BASE_ADDR, 0x12141013);
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mmio_write_32(0x0004 + PHYD_BASE_ADDR, 0x0C041503);
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mmio_write_32(0x0008 + PHYD_BASE_ADDR, 0x06050001);
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mmio_write_32(0x000C + PHYD_BASE_ADDR, 0x08070B02);
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mmio_write_32(0x0010 + PHYD_BASE_ADDR, 0x0A0F0E09);
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mmio_write_32(0x0014 + PHYD_BASE_ADDR, 0x0016110D);
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mmio_write_32(0x0018 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x001C + PHYD_BASE_ADDR, 0x00000100);
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mmio_write_32(0x0020 + PHYD_BASE_ADDR, 0x02136574);
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mmio_write_32(0x0024 + PHYD_BASE_ADDR, 0x00000008);
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mmio_write_32(0x0028 + PHYD_BASE_ADDR, 0x76512308);
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mmio_write_32(0x002C + PHYD_BASE_ADDR, 0x00000004);
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break;
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case DDR_VENDOR_NY_2G:
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// DDR3_2G
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mmio_write_32(0x0000 + PHYD_BASE_ADDR, 0x08070D09);
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mmio_write_32(0x0004 + PHYD_BASE_ADDR, 0x0605020B);
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mmio_write_32(0x0008 + PHYD_BASE_ADDR, 0x14040100);
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mmio_write_32(0x000C + PHYD_BASE_ADDR, 0x15030E0C);
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mmio_write_32(0x0010 + PHYD_BASE_ADDR, 0x0A0F1213);
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mmio_write_32(0x0014 + PHYD_BASE_ADDR, 0x00111016);
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mmio_write_32(0x0018 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x001C + PHYD_BASE_ADDR, 0x00000100);
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mmio_write_32(0x0020 + PHYD_BASE_ADDR, 0x82135764);
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mmio_write_32(0x0024 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x0028 + PHYD_BASE_ADDR, 0x67513028);
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mmio_write_32(0x002C + PHYD_BASE_ADDR, 0x00000004);
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break;
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case DDR_VENDOR_ESMT_1G:
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// DDR3_1G
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KC_MSG("pin mux X16 mode DDR_VENDOR_ESMT_1G setting\n");
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mmio_write_32(0x0000 + PHYD_BASE_ADDR, 0x08070B09);
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mmio_write_32(0x0004 + PHYD_BASE_ADDR, 0x05000206);
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mmio_write_32(0x0008 + PHYD_BASE_ADDR, 0x0C04010D);
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mmio_write_32(0x000C + PHYD_BASE_ADDR, 0x15030A14);
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mmio_write_32(0x0010 + PHYD_BASE_ADDR, 0x10111213);
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mmio_write_32(0x0014 + PHYD_BASE_ADDR, 0x000F160E);
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mmio_write_32(0x0018 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x001C + PHYD_BASE_ADDR, 0x00000100);
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mmio_write_32(0x0020 + PHYD_BASE_ADDR, 0x31756024);
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mmio_write_32(0x0024 + PHYD_BASE_ADDR, 0x00000008);
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mmio_write_32(0x0028 + PHYD_BASE_ADDR, 0x26473518);
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mmio_write_32(0x002C + PHYD_BASE_ADDR, 0x00000000);
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break;
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case DDR_VENDOR_ESMT_512M_DDR2:
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// N25_DDR2_512
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KC_MSG("pin mux X16 mode DDR_VENDOR_ESMT_512M_DDR2 setting\n");
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mmio_write_32(0x0000 + PHYD_BASE_ADDR, 0x0C06080B);
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mmio_write_32(0x0004 + PHYD_BASE_ADDR, 0x070D0904);
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mmio_write_32(0x0008 + PHYD_BASE_ADDR, 0x00010502);
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mmio_write_32(0x000C + PHYD_BASE_ADDR, 0x110A0E03);
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mmio_write_32(0x0010 + PHYD_BASE_ADDR, 0x0F141610);
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mmio_write_32(0x0014 + PHYD_BASE_ADDR, 0x00151312);
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mmio_write_32(0x0018 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x001C + PHYD_BASE_ADDR, 0x00000100);
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mmio_write_32(0x0020 + PHYD_BASE_ADDR, 0x71840532);
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mmio_write_32(0x0024 + PHYD_BASE_ADDR, 0x00000006);
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mmio_write_32(0x0028 + PHYD_BASE_ADDR, 0x76103425);
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mmio_write_32(0x002C + PHYD_BASE_ADDR, 0x00000008);
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break;
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case DDR_VENDOR_ESMT_2G:
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// DDR3_2G
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mmio_write_32(0x0000 + PHYD_BASE_ADDR, 0x080B0D06);
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mmio_write_32(0x0004 + PHYD_BASE_ADDR, 0x09010407);
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mmio_write_32(0x0008 + PHYD_BASE_ADDR, 0x1405020C);
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mmio_write_32(0x000C + PHYD_BASE_ADDR, 0x15000E03);
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mmio_write_32(0x0010 + PHYD_BASE_ADDR, 0x0A0F1213);
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mmio_write_32(0x0014 + PHYD_BASE_ADDR, 0x00111016);
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mmio_write_32(0x0018 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x001C + PHYD_BASE_ADDR, 0x00000100);
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mmio_write_32(0x0020 + PHYD_BASE_ADDR, 0x82135764);
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mmio_write_32(0x0024 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x0028 + PHYD_BASE_ADDR, 0x67513208);
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mmio_write_32(0x002C + PHYD_BASE_ADDR, 0x00000004);
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break;
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case DDR_VENDOR_ETRON_1G:
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// ETRON_DDR3_1G
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mmio_write_32(0x0000 + PHYD_BASE_ADDR, 0x0B060908);
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mmio_write_32(0x0004 + PHYD_BASE_ADDR, 0x02000107);
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mmio_write_32(0x0008 + PHYD_BASE_ADDR, 0x0C05040D);
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mmio_write_32(0x000C + PHYD_BASE_ADDR, 0x13141503);
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mmio_write_32(0x0010 + PHYD_BASE_ADDR, 0x160A1112);
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mmio_write_32(0x0014 + PHYD_BASE_ADDR, 0x000F100E);
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mmio_write_32(0x0018 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x001C + PHYD_BASE_ADDR, 0x00000100);
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mmio_write_32(0x0020 + PHYD_BASE_ADDR, 0x28137564);
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mmio_write_32(0x0024 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x0028 + PHYD_BASE_ADDR, 0x76158320);
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mmio_write_32(0x002C + PHYD_BASE_ADDR, 0x00000004);
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break;
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case DDR_VENDOR_ESMT_N25_1G:
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// ESMT_N25_DDR3_1G
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mmio_write_32(0x0000 + PHYD_BASE_ADDR, 0x08060B09);
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mmio_write_32(0x0004 + PHYD_BASE_ADDR, 0x02040701);
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mmio_write_32(0x0008 + PHYD_BASE_ADDR, 0x0C00050D);
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mmio_write_32(0x000C + PHYD_BASE_ADDR, 0x13150314);
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mmio_write_32(0x0010 + PHYD_BASE_ADDR, 0x10111216);
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mmio_write_32(0x0014 + PHYD_BASE_ADDR, 0x000F0A0E);
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mmio_write_32(0x0018 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x001C + PHYD_BASE_ADDR, 0x00000100);
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mmio_write_32(0x0020 + PHYD_BASE_ADDR, 0x82135674);
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mmio_write_32(0x0024 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x0028 + PHYD_BASE_ADDR, 0x76153280);
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mmio_write_32(0x002C + PHYD_BASE_ADDR, 0x00000004);
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break;
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case DDR_VENDOR_ETRON_512M_DDR2:
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// ETRON_DDR2_512
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mmio_write_32(0x0000 + PHYD_BASE_ADDR, 0x070B090C);
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mmio_write_32(0x0004 + PHYD_BASE_ADDR, 0x04050608);
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mmio_write_32(0x0008 + PHYD_BASE_ADDR, 0x0E02030D);
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mmio_write_32(0x000C + PHYD_BASE_ADDR, 0x110A0100);
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mmio_write_32(0x0010 + PHYD_BASE_ADDR, 0x0F131614);
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mmio_write_32(0x0014 + PHYD_BASE_ADDR, 0x00151012);
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mmio_write_32(0x0018 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x001C + PHYD_BASE_ADDR, 0x00000100);
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mmio_write_32(0x0020 + PHYD_BASE_ADDR, 0x86014532);
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mmio_write_32(0x0024 + PHYD_BASE_ADDR, 0x00000007);
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mmio_write_32(0x0028 + PHYD_BASE_ADDR, 0x76012345);
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mmio_write_32(0x002C + PHYD_BASE_ADDR, 0x00000008);
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break;
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case DDR_VENDOR_NY_N20_1G:
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// NY_N20_DDR3_1G
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mmio_write_32(0x0000 + PHYD_BASE_ADDR, 0x08060F0B);
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mmio_write_32(0x0004 + PHYD_BASE_ADDR, 0x07040109);
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mmio_write_32(0x0008 + PHYD_BASE_ADDR, 0x1405020C);
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mmio_write_32(0x000C + PHYD_BASE_ADDR, 0x15030F00);
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mmio_write_32(0x0010 + PHYD_BASE_ADDR, 0x0A0F1213);
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mmio_write_32(0x0014 + PHYD_BASE_ADDR, 0x00111016);
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mmio_write_32(0x0018 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x001C + PHYD_BASE_ADDR, 0x00000100);
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mmio_write_32(0x0020 + PHYD_BASE_ADDR, 0x82315764);
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mmio_write_32(0x0024 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x0028 + PHYD_BASE_ADDR, 0x67513208);
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mmio_write_32(0x002C + PHYD_BASE_ADDR, 0x00000004);
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break;
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case DDR_VENDOR_UNILC_N25_1G:
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// UnilC_DDR3_1G
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mmio_write_32(0x0000 + PHYD_BASE_ADDR, 0x08020B07);
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mmio_write_32(0x0004 + PHYD_BASE_ADDR, 0x00030905);
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mmio_write_32(0x0008 + PHYD_BASE_ADDR, 0x04010006);
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mmio_write_32(0x000C + PHYD_BASE_ADDR, 0x1300150C);
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mmio_write_32(0x0010 + PHYD_BASE_ADDR, 0x16111214);
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mmio_write_32(0x0014 + PHYD_BASE_ADDR, 0x00000A10);
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mmio_write_32(0x0018 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x001C + PHYD_BASE_ADDR, 0x00000100);
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mmio_write_32(0x0020 + PHYD_BASE_ADDR, 0x08137564);
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mmio_write_32(0x0024 + PHYD_BASE_ADDR, 0x00000002);
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mmio_write_32(0x0028 + PHYD_BASE_ADDR, 0x76513820);
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mmio_write_32(0x002C + PHYD_BASE_ADDR, 0x00000004);
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break;
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case DDR_VENDOR_UNILC_N21_2G:
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// UnilC_DDR3_2G
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mmio_write_32(0x0000 + PHYD_BASE_ADDR, 0x08070D09);
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mmio_write_32(0x0004 + PHYD_BASE_ADDR, 0x0605020B);
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mmio_write_32(0x0008 + PHYD_BASE_ADDR, 0x14040100);
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mmio_write_32(0x000C + PHYD_BASE_ADDR, 0x1503000C);
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mmio_write_32(0x0010 + PHYD_BASE_ADDR, 0x0A120013);
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mmio_write_32(0x0014 + PHYD_BASE_ADDR, 0x00111016);
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mmio_write_32(0x0018 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x001C + PHYD_BASE_ADDR, 0x00000100);
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mmio_write_32(0x0020 + PHYD_BASE_ADDR, 0x82135764);
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mmio_write_32(0x0024 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x0028 + PHYD_BASE_ADDR, 0x76513208);
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mmio_write_32(0x002C + PHYD_BASE_ADDR, 0x00000004);
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break;
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case DDR_VENDOR_ESMT_N21_2G:
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// ESMT_N21_DDR3_2G
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mmio_write_32(0x0000 + PHYD_BASE_ADDR, 0x08070D09);
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mmio_write_32(0x0004 + PHYD_BASE_ADDR, 0x0605020B);
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mmio_write_32(0x0008 + PHYD_BASE_ADDR, 0x14040100);
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mmio_write_32(0x000C + PHYD_BASE_ADDR, 0x1503000C);
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mmio_write_32(0x0010 + PHYD_BASE_ADDR, 0x16001213);
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mmio_write_32(0x0014 + PHYD_BASE_ADDR, 0x0011100A);
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mmio_write_32(0x0018 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x001C + PHYD_BASE_ADDR, 0x00000100);
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mmio_write_32(0x0020 + PHYD_BASE_ADDR, 0x82315746);
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mmio_write_32(0x0024 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x0028 + PHYD_BASE_ADDR, 0x67513208);
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mmio_write_32(0x002C + PHYD_BASE_ADDR, 0x00000004);
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break;
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case DDR_VENDOR_ESMT_N19_4G:
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// ESMT_DDR3_4G_19nm
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mmio_write_32(0x0000 + PHYD_BASE_ADDR, 0x09050D07);
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mmio_write_32(0x0004 + PHYD_BASE_ADDR, 0x00080E02);
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mmio_write_32(0x0008 + PHYD_BASE_ADDR, 0x0C060B01);
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mmio_write_32(0x000C + PHYD_BASE_ADDR, 0x12031104);
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mmio_write_32(0x0010 + PHYD_BASE_ADDR, 0x15001310);
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mmio_write_32(0x0014 + PHYD_BASE_ADDR, 0x000A1614);
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mmio_write_32(0x0018 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x001C + PHYD_BASE_ADDR, 0x00000100);
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mmio_write_32(0x0020 + PHYD_BASE_ADDR, 0x31756024);
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mmio_write_32(0x0024 + PHYD_BASE_ADDR, 0x00000008);
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mmio_write_32(0x0028 + PHYD_BASE_ADDR, 0x45172380);
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mmio_write_32(0x002C + PHYD_BASE_ADDR, 0x00000006);
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break;
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case DDR_VENDOR_UNILC_N25_512M_DDR2:
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// UniIC_DDR2_512M
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mmio_write_32(0x0000 + PHYD_BASE_ADDR, 0x00040608);
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mmio_write_32(0x0004 + PHYD_BASE_ADDR, 0x02090B0C);
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mmio_write_32(0x0008 + PHYD_BASE_ADDR, 0x0E01070D);
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mmio_write_32(0x000C + PHYD_BASE_ADDR, 0x0A031605);
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mmio_write_32(0x0010 + PHYD_BASE_ADDR, 0x10110F14);
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mmio_write_32(0x0014 + PHYD_BASE_ADDR, 0x00121513);
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mmio_write_32(0x0018 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x001C + PHYD_BASE_ADDR, 0x00000100);
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mmio_write_32(0x0020 + PHYD_BASE_ADDR, 0x61437025);
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mmio_write_32(0x0024 + PHYD_BASE_ADDR, 0x00000008);
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mmio_write_32(0x0028 + PHYD_BASE_ADDR, 0x63410725);
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mmio_write_32(0x002C + PHYD_BASE_ADDR, 0x00000008);
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break;
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case DDR_VENDOR_ETRON_N20_2G:
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// Etron_N20_DDR3_2G (ERD3CBA20-HA2133, GELMV QFN88 SIP)
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mmio_write_32(0x0000 + PHYD_BASE_ADDR, 0x08070D09);
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mmio_write_32(0x0004 + PHYD_BASE_ADDR, 0x06010B02);
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mmio_write_32(0x0008 + PHYD_BASE_ADDR, 0x0C000405);
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mmio_write_32(0x000C + PHYD_BASE_ADDR, 0x13151403);
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mmio_write_32(0x0010 + PHYD_BASE_ADDR, 0x0A001612);
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mmio_write_32(0x0014 + PHYD_BASE_ADDR, 0x00110010);
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mmio_write_32(0x0018 + PHYD_BASE_ADDR, 0x00000000);
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mmio_write_32(0x001C + PHYD_BASE_ADDR, 0x00000100);
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mmio_write_32(0x0020 + PHYD_BASE_ADDR, 0x20317546);
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mmio_write_32(0x0024 + PHYD_BASE_ADDR, 0x00000008);
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mmio_write_32(0x0028 + PHYD_BASE_ADDR, 0x67512308);
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mmio_write_32(0x002C + PHYD_BASE_ADDR, 0x00000004);
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break;
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}
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#endif //ndef DDR_SIM
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#ifdef ETRON_DDR2_512
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KC_MSG("pin mux X16 mode ETRON_DDR2_512 setting\n");
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//------------------------------
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// pin mux base on PHYA
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//------------------------------
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//param_phyd_data_byte_swap_slice0 [1: 0]
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//param_phyd_data_byte_swap_slice1 [9: 8]
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rddata = 0x00000100;
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mmio_write_32(0x001C + PHYD_BASE_ADDR, rddata);
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//param_phyd_swap_byte0_dq0_mux [3: 0]
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//param_phyd_swap_byte0_dq1_mux [7: 4]
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//param_phyd_swap_byte0_dq2_mux [11: 8]
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//param_phyd_swap_byte0_dq3_mux [15: 12]
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//param_phyd_swap_byte0_dq4_mux [19: 16]
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//param_phyd_swap_byte0_dq5_mux [23: 20]
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//param_phyd_swap_byte0_dq6_mux [27: 24]
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//param_phyd_swap_byte0_dq7_mux [31: 28]
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rddata = 0x86014532;
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mmio_write_32(0x0020 + PHYD_BASE_ADDR, rddata);
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//param_phyd_swap_byte0_dm_mux [3: 0]
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rddata = 0x00000007;
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mmio_write_32(0x0024 + PHYD_BASE_ADDR, rddata);
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//param_phyd_swap_byte1_dq0_mux [3: 0]
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//param_phyd_swap_byte1_dq1_mux [7: 4]
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//param_phyd_swap_byte1_dq2_mux [11: 8]
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//param_phyd_swap_byte1_dq3_mux [15: 12]
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//param_phyd_swap_byte1_dq4_mux [19: 16]
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//param_phyd_swap_byte1_dq5_mux [23: 20]
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//param_phyd_swap_byte1_dq6_mux [27: 24]
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//param_phyd_swap_byte1_dq7_mux [31: 28]
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rddata = 0x76012345;
|
|
mmio_write_32(0x0028 + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_byte1_dm_mux [3: 0]
|
|
rddata = 0x00000008;
|
|
mmio_write_32(0x002C + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_ca0 [4: 0]
|
|
//param_phyd_swap_ca1 [12: 8]
|
|
//param_phyd_swap_ca2 [20: 16]
|
|
//param_phyd_swap_ca3 [28: 24]
|
|
rddata = 0x070B090C;
|
|
mmio_write_32(0x0000 + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_ca4 [4: 0]
|
|
//param_phyd_swap_ca5 [12: 8]
|
|
//param_phyd_swap_ca6 [20: 16]
|
|
//param_phyd_swap_ca7 [28: 24]
|
|
rddata = 0x04050608;
|
|
mmio_write_32(0x0004 + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_ca8 [4: 0]
|
|
//param_phyd_swap_ca9 [12: 8]
|
|
//param_phyd_swap_ca10 [20: 16]
|
|
//param_phyd_swap_ca11 [28: 24]
|
|
rddata = 0x0E02030D;
|
|
mmio_write_32(0x0008 + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_ca12 [4: 0]
|
|
//param_phyd_swap_ca13 [12: 8]
|
|
//param_phyd_swap_ca14 [20: 16]
|
|
//param_phyd_swap_ca15 [28: 24]
|
|
rddata = 0x110A0100;
|
|
mmio_write_32(0x000C + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_ca16 [4: 0]
|
|
//param_phyd_swap_ca17 [12: 8]
|
|
//param_phyd_swap_ca18 [20: 16]
|
|
//param_phyd_swap_ca19 [28: 24]
|
|
rddata = 0x0F131614;
|
|
mmio_write_32(0x0010 + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_ca20 [4: 0]
|
|
//param_phyd_swap_ca21 [12: 8]
|
|
//param_phyd_swap_ca22 [20: 16]
|
|
rddata = 0x00151012;
|
|
mmio_write_32(0x0014 + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_cke0 [0:0]
|
|
//param_phyd_swap_cs0 [4:4]
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x0018 + PHYD_BASE_ADDR, rddata);
|
|
KC_MSG("pin mux setting }\n");
|
|
#endif
|
|
|
|
//pinmux
|
|
#ifdef ESMT_N25_DDR3_1G
|
|
KC_MSG("pin mux X16 mode ESMT_N25_DDR3_1G setting\n");
|
|
//------------------------------
|
|
// pin mux base on PHYA
|
|
//------------------------------
|
|
//param_phyd_data_byte_swap_slice0 [1: 0]
|
|
//param_phyd_data_byte_swap_slice1 [9: 8]
|
|
rddata = 0x00000100;
|
|
mmio_write_32(0x001C + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_byte0_dq0_mux [3: 0]
|
|
//param_phyd_swap_byte0_dq1_mux [7: 4]
|
|
//param_phyd_swap_byte0_dq2_mux [11: 8]
|
|
//param_phyd_swap_byte0_dq3_mux [15: 12]
|
|
//param_phyd_swap_byte0_dq4_mux [19: 16]
|
|
//param_phyd_swap_byte0_dq5_mux [23: 20]
|
|
//param_phyd_swap_byte0_dq6_mux [27: 24]
|
|
//param_phyd_swap_byte0_dq7_mux [31: 28]
|
|
rddata = 0x82135674;
|
|
mmio_write_32(0x0020 + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_byte0_dm_mux [3: 0]
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x0024 + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_byte1_dq0_mux [3: 0]
|
|
//param_phyd_swap_byte1_dq1_mux [7: 4]
|
|
//param_phyd_swap_byte1_dq2_mux [11: 8]
|
|
//param_phyd_swap_byte1_dq3_mux [15: 12]
|
|
//param_phyd_swap_byte1_dq4_mux [19: 16]
|
|
//param_phyd_swap_byte1_dq5_mux [23: 20]
|
|
//param_phyd_swap_byte1_dq6_mux [27: 24]
|
|
//param_phyd_swap_byte1_dq7_mux [31: 28]
|
|
rddata = 0x76153280;
|
|
mmio_write_32(0x0028 + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_byte1_dm_mux [3: 0]
|
|
rddata = 0x00000004;
|
|
mmio_write_32(0x002C + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_ca0 [4: 0]
|
|
//param_phyd_swap_ca1 [12: 8]
|
|
//param_phyd_swap_ca2 [20: 16]
|
|
//param_phyd_swap_ca3 [28: 24]
|
|
rddata = 0x08060B09;
|
|
mmio_write_32(0x0000 + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_ca4 [4: 0]
|
|
//param_phyd_swap_ca5 [12: 8]
|
|
//param_phyd_swap_ca6 [20: 16]
|
|
//param_phyd_swap_ca7 [28: 24]
|
|
rddata = 0x02040701;
|
|
mmio_write_32(0x0004 + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_ca8 [4: 0]
|
|
//param_phyd_swap_ca9 [12: 8]
|
|
//param_phyd_swap_ca10 [20: 16]
|
|
//param_phyd_swap_ca11 [28: 24]
|
|
rddata = 0x0C00050D;
|
|
mmio_write_32(0x0008 + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_ca12 [4: 0]
|
|
//param_phyd_swap_ca13 [12: 8]
|
|
//param_phyd_swap_ca14 [20: 16]
|
|
//param_phyd_swap_ca15 [28: 24]
|
|
rddata = 0x13150314;
|
|
mmio_write_32(0x000C + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_ca16 [4: 0]
|
|
//param_phyd_swap_ca17 [12: 8]
|
|
//param_phyd_swap_ca18 [20: 16]
|
|
//param_phyd_swap_ca19 [28: 24]
|
|
rddata = 0x10111216;
|
|
mmio_write_32(0x0010 + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_ca20 [4: 0]
|
|
//param_phyd_swap_ca21 [12: 8]
|
|
//param_phyd_swap_ca22 [20: 16]
|
|
rddata = 0x000F0A0E;
|
|
mmio_write_32(0x0014 + PHYD_BASE_ADDR, rddata);
|
|
//param_phyd_swap_cke0 [0: 0]
|
|
//param_phyd_swap_cs0 [4: 4]
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x0018 + PHYD_BASE_ADDR, rddata);
|
|
KC_MSG("pin mux setting }\n");
|
|
#endif
|
|
|
|
#ifdef ESMT_DDR3_2G
|
|
KC_MSG("pin mux X16 mode ESMT_DDR3_2G setting\n");
|
|
rddata = 0x00000100;
|
|
mmio_write_32(0x001C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x82135764;
|
|
mmio_write_32(0x0020 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x0024 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x67513208;
|
|
mmio_write_32(0x0028 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000004;
|
|
mmio_write_32(0x002C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x080B0D06;
|
|
mmio_write_32(0x0000 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x09010407;
|
|
mmio_write_32(0x0004 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x1405020C;
|
|
mmio_write_32(0x0008 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x15000E03;
|
|
mmio_write_32(0x000C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0A0F1213;
|
|
mmio_write_32(0x0010 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00111016;
|
|
mmio_write_32(0x0014 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x0018 + PHYD_BASE_ADDR, rddata);
|
|
KC_MSG("pin mux setting }\n");
|
|
#endif
|
|
|
|
#ifdef ETRON_DDR3_1G
|
|
KC_MSG("pin mux X16 mode ETRON_DDR3_1G setting\n");
|
|
rddata = 0x00000100;
|
|
mmio_write_32(0x001C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x28137564;
|
|
mmio_write_32(0x0020 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x0024 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x76158320;
|
|
mmio_write_32(0x0028 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000004;
|
|
mmio_write_32(0x002C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0B060908;
|
|
mmio_write_32(0x0000 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x02000107;
|
|
mmio_write_32(0x0004 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0C05040D;
|
|
mmio_write_32(0x0008 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x13141503;
|
|
mmio_write_32(0x000C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x160A1112;
|
|
mmio_write_32(0x0010 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x000F100E;
|
|
mmio_write_32(0x0014 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x0018 + PHYD_BASE_ADDR, rddata);
|
|
KC_MSG("pin mux setting }\n");
|
|
#endif
|
|
|
|
#ifdef DDR3_1G
|
|
KC_MSG("pin mux X16 mode DDR3_1G setting\n");
|
|
rddata = 0x00000100;
|
|
mmio_write_32(0x001C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x31756024;
|
|
mmio_write_32(0x0020 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000008;
|
|
mmio_write_32(0x0024 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x26473518;
|
|
mmio_write_32(0x0028 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x002C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x08070B09;
|
|
mmio_write_32(0x0000 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x05000206;
|
|
mmio_write_32(0x0004 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0C04010D;
|
|
mmio_write_32(0x0008 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x15030A14;
|
|
mmio_write_32(0x000C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x10111213;
|
|
mmio_write_32(0x0010 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x000F160E;
|
|
mmio_write_32(0x0014 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x0018 + PHYD_BASE_ADDR, rddata);
|
|
KC_MSG("pin mux setting }\n");
|
|
#endif
|
|
|
|
#ifdef DDR3_2G
|
|
KC_MSG("pin mux X16 mode DDR3_2G setting\n");
|
|
rddata = 0x00000100;
|
|
mmio_write_32(0x001C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x82135764;
|
|
mmio_write_32(0x0020 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x0024 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x67513028;
|
|
mmio_write_32(0x0028 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000004;
|
|
mmio_write_32(0x002C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x08070D09;
|
|
mmio_write_32(0x0000 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0605020B;
|
|
mmio_write_32(0x0004 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x14040100;
|
|
mmio_write_32(0x0008 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x15030E0C;
|
|
mmio_write_32(0x000C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0A0F1213;
|
|
mmio_write_32(0x0010 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00111016;
|
|
mmio_write_32(0x0014 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x0018 + PHYD_BASE_ADDR, rddata);
|
|
KC_MSG("pin mux setting }\n");
|
|
#endif
|
|
|
|
#ifdef DDR3_4G
|
|
KC_MSG("pin mux X16 mode DDR3_4G setting\n");
|
|
rddata = 0x00000100;
|
|
mmio_write_32(0x001C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x02136574;
|
|
mmio_write_32(0x0020 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000008;
|
|
mmio_write_32(0x0024 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x76512308;
|
|
mmio_write_32(0x0028 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000004;
|
|
mmio_write_32(0x002C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x12141013;
|
|
mmio_write_32(0x0000 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0C041503;
|
|
mmio_write_32(0x0004 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x06050001;
|
|
mmio_write_32(0x0008 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x08070B02;
|
|
mmio_write_32(0x000C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0A0F0E09;
|
|
mmio_write_32(0x0010 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0016110D;
|
|
mmio_write_32(0x0014 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x0018 + PHYD_BASE_ADDR, rddata);
|
|
KC_MSG("pin mux setting }\n");
|
|
#endif
|
|
|
|
#ifdef DDR3_DBG
|
|
KC_MSG("pin mux X16 mode DDR3_DBG setting\n");
|
|
rddata = 0x00000100;
|
|
mmio_write_32(0x001C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x30587246;
|
|
mmio_write_32(0x0020 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000001;
|
|
mmio_write_32(0x0024 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x26417538;
|
|
mmio_write_32(0x0028 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x002C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0002080E;
|
|
mmio_write_32(0x0000 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x04060D01;
|
|
mmio_write_32(0x0004 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x090C030B;
|
|
mmio_write_32(0x0008 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x05071412;
|
|
mmio_write_32(0x000C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0A151013;
|
|
mmio_write_32(0x0010 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0016110F;
|
|
mmio_write_32(0x0014 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x0018 + PHYD_BASE_ADDR, rddata);
|
|
KC_MSG("pin mux setting }\n");
|
|
#endif
|
|
#ifdef DDR3_PINMUX
|
|
KC_MSG("pin mux X16 mode DDR3_6mil setting\n");
|
|
rddata = 0x00000001;
|
|
mmio_write_32(0x001C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x40613578;
|
|
mmio_write_32(0x0020 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000002;
|
|
mmio_write_32(0x0024 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x03582467;
|
|
mmio_write_32(0x0028 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000001;
|
|
mmio_write_32(0x002C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x020E0D00;
|
|
mmio_write_32(0x0000 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x07090806;
|
|
mmio_write_32(0x0004 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0C05010B;
|
|
mmio_write_32(0x0008 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x12141503;
|
|
mmio_write_32(0x000C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x100A0413;
|
|
mmio_write_32(0x0010 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00160F11;
|
|
mmio_write_32(0x0014 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x0018 + PHYD_BASE_ADDR, rddata);
|
|
KC_MSG("pin mux setting }\n");
|
|
#endif
|
|
|
|
#ifdef DDR2_512
|
|
KC_MSG("pin mux X16 mode DDR2_512 setting\n");
|
|
rddata = 0x00000100;
|
|
mmio_write_32(0x001C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x60851243;
|
|
mmio_write_32(0x0020 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000007;
|
|
mmio_write_32(0x0024 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x67012354;
|
|
mmio_write_32(0x0028 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000008;
|
|
mmio_write_32(0x002C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0C06080B;
|
|
mmio_write_32(0x0000 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x090D0204;
|
|
mmio_write_32(0x0004 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x01050700;
|
|
mmio_write_32(0x0008 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x160A0E03;
|
|
mmio_write_32(0x000C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0F141110;
|
|
mmio_write_32(0x0010 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00151312;
|
|
mmio_write_32(0x0014 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x0018 + PHYD_BASE_ADDR, rddata);
|
|
KC_MSG("pin mux setting }\n");
|
|
#endif
|
|
|
|
#ifdef N25_DDR2_512
|
|
KC_MSG("pin mux X16 mode N25_DDR2_512 setting\n");
|
|
rddata = 0x00000100;
|
|
mmio_write_32(0x001C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x71840532;
|
|
mmio_write_32(0x0020 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000006;
|
|
mmio_write_32(0x0024 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x76103425;
|
|
mmio_write_32(0x0028 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000008;
|
|
mmio_write_32(0x002C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0C06080B;
|
|
mmio_write_32(0x0000 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x070D0904;
|
|
mmio_write_32(0x0004 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00010502;
|
|
mmio_write_32(0x0008 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x110A0E03;
|
|
mmio_write_32(0x000C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0F141610;
|
|
mmio_write_32(0x0010 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00151312;
|
|
mmio_write_32(0x0014 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x0018 + PHYD_BASE_ADDR, rddata);
|
|
KC_MSG("pin mux setting }\n");
|
|
#endif
|
|
#ifdef DDR2_PINMUX
|
|
KC_MSG("pin mux X16 mode DDR2 setting\n");
|
|
rddata = 0x00000001;
|
|
mmio_write_32(0x001C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x40613578;
|
|
mmio_write_32(0x0020 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000002;
|
|
mmio_write_32(0x0024 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x03582467;
|
|
mmio_write_32(0x0028 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000001;
|
|
mmio_write_32(0x002C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x020E0D00;
|
|
mmio_write_32(0x0000 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x07090806;
|
|
mmio_write_32(0x0004 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x0C05010B;
|
|
mmio_write_32(0x0008 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x12141503;
|
|
mmio_write_32(0x000C + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x100A0413;
|
|
mmio_write_32(0x0010 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00160F11;
|
|
mmio_write_32(0x0014 + PHYD_BASE_ADDR, rddata);
|
|
rddata = 0x00000000;
|
|
mmio_write_32(0x0018 + PHYD_BASE_ADDR, rddata);
|
|
KC_MSG("pin mux setting }\n");
|
|
#endif
|
|
}
|