mirror of
https://github.com/sipeed/LicheeRV-Nano-Build.git
synced 2026-11-09 18:04:55 -06:00
dbbad1938a
Update the vendored FSBL from Sophgo sg200x-dev commit 426d1e7eccce84b34169e5f21de7d6e7da1804a1 to 5a80c127cf614dea7f534d5b5352886a1c720d37, incorporating 24 upstream commits. Keep the local plat/sg200x symlink to cv181x. Import the upstream DDR, clock, storage and boot-image changes together with their platform support, prebuilt firmware and licensing files. All 935 upstream files match the target revision. Validation on LicheeRV Nano (SG2002/C906, SD, DDR3-1866 x16): - Cross-build BL2 with the existing Xuantie GCC 10.2.0 toolchain. - Repack FIP while preserving the installed OpenSBI and U-Boot byte for byte; verify headers, payload checksums, entry addresses and LZMA. - Software reboot and power-cycle boot succeed; memtester 16M 1 passes all 18 checks. Validation covers the FSBL update with existing later boot stages. Full firmware builds, A53 and video/HID acceptance are not covered.
99 lines
2.1 KiB
ArmAsm
99 lines
2.1 KiB
ArmAsm
/*
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform.h>
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#ifdef __riscv
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OUTPUT_FORMAT("elf64-littleriscv")
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OUTPUT_ARCH(riscv)
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#else
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OUTPUT_FORMAT("elf64-littleaarch64")
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OUTPUT_ARCH(aarch64)
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#endif
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ENTRY(bl2_entrypoint)
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MEMORY {
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RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_SIZE
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SRAM (rwx): ORIGIN = TPU_SRAM_BASE, LENGTH = TPU_SRAM_SIZE
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}
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SECTIONS
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{
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. = BL2_BASE;
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ASSERT(. == ALIGN(4096),
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"BL2_BASE address is not aligned on a page boundary.")
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ro . : {
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__RO_START__ = .;
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*bl2_entrypoint.o(.text*)
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*(.vectors)
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*(.text*)
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*(.rodata*)
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__RO_END__ = .;
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} >RAM
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/*
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* .data must be placed at a lower address than the stacks if the stack
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* protector is enabled. Alternatively, the .data.stack_protector_canary
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* section can be placed independently of the main .data section.
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*/
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.data . : {
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. = ALIGN(16);
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__DATA_START__ = .;
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*(.data*)
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. = ALIGN(16);
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__DATA_END__ = .;
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} >RAM
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stacks (NOLOAD) : {
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. = ALIGN(64);
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__STACKS_START__ = .;
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. += PLATFORM_STACK_SIZE;
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. = ALIGN(64);
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__STACKS_END__ = .;
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} >RAM
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/*
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* The .bss section gets initialised to 0 at runtime.
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* Its base address should be 16-byte aligned for better performance of the
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* zero-initialization code.
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*/
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.bss : ALIGN(16) {
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. = ALIGN(16);
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__BSS_START__ = .;
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*(SORT_BY_ALIGNMENT(.bss*))
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*(COMMON)
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. = ALIGN(16);
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__BSS_END__ = .;
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} >RAM
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/*
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* Define a linker symbol to mark end of the RW memory area for this
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* image.
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*/
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__BL2_END__ = .;
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__BSS_SIZE__ = SIZEOF(.bss);
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ASSERT(. <= (BL2_BASE + BL2_SIZE), "BL2 image has exceeded its limit.")
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.suspend_sect :
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{
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. = ALIGN(8);
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__suspend_sect_start = .;
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KEEP(*(.suspend_entry))
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KEEP(*(.suspend_func))
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. = ALIGN(8);
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__suspend_data_start = .;
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KEEP(*(.suspend_data))
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. = ALIGN(8);
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__suspend_sect_end = .;
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} > SRAM
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#include <rom_api_refer.h>
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}
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