mirror of
https://github.com/sipeed/LicheeRV-Nano-Build.git
synced 2026-11-09 18:04:55 -06:00
dbbad1938a
Update the vendored FSBL from Sophgo sg200x-dev commit 426d1e7eccce84b34169e5f21de7d6e7da1804a1 to 5a80c127cf614dea7f534d5b5352886a1c720d37, incorporating 24 upstream commits. Keep the local plat/sg200x symlink to cv181x. Import the upstream DDR, clock, storage and boot-image changes together with their platform support, prebuilt firmware and licensing files. All 935 upstream files match the target revision. Validation on LicheeRV Nano (SG2002/C906, SD, DDR3-1866 x16): - Cross-build BL2 with the existing Xuantie GCC 10.2.0 toolchain. - Repack FIP while preserving the installed OpenSBI and U-Boot byte for byte; verify headers, payload checksums, entry addresses and LZMA. - Software reboot and power-cycle boot succeed; memtester 16M 1 passes all 18 checks. Validation covers the FSBL update with existing later boot stages. Full firmware builds, A53 and video/HID acceptance are not covered.
138 lines
2.9 KiB
ArmAsm
138 lines
2.9 KiB
ArmAsm
/*
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <cpu.h>
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#include <aarch64/asm_macros.S>
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#include <bl_common.h>
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#include <debug.h>
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.globl bl2_entrypoint
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.globl bl2_entrypoint_real
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func bl2_entrypoint
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b bl2_entrypoint_real
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.word 0 // resvered
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.word 0 // BL2 MSID
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.word 0 // BL2 version
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.word 0 //
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.word 0
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.word 0
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.word 0
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bl2_entrypoint_real:
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atf_state_set w14, x15, ATF_STATE_BL2_ENTRY_POINT
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/* ---------------------------------------------
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* Sync instruction cache
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* ---------------------------------------------
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*/
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ic iallu
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isb
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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* ---------------------------------------------
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*/
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adr x0, bl2_exceptions
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msr vbar_el3, x0
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isb
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/* ---------------------------------------------
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* Enable the SError interrupt now that the
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* exception vectors have been setup.
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* ---------------------------------------------
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*/
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msr daifclr, #DAIF_ABT_BIT
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/* ---------------------------------------------
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* Zero out NOBITS sections. There are 2 of them:
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* - the .bss section;
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* - the coherent memory section.
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* ---------------------------------------------
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*/
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ldr x0, =__BSS_START__
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ldr x1, =__BSS_SIZE__
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bl zeromem
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/* --------------------------------------------
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* Allocate a stack whose memory will be marked
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* as Normal-IS-WBWA when the MMU is enabled.
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* There is no risk of reading stale stack
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* memory after enabling the MMU as only the
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* primary cpu is running at the moment.
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* --------------------------------------------
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*/
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ldr x0, =__STACKS_END__
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mov sp, x0
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/* ---------------------------------------------
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* Jump to main function.
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* ---------------------------------------------
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*/
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bl bl2_main
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/* ---------------------------------------------
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* Should never reach this point.
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* ---------------------------------------------
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*/
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no_ret panic_handler
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endfunc bl2_entrypoint
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.global call_with_eret_to_next
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.type call_with_eret_to_next, %function
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.global call_with_eret
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.type call_with_eret, %function
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call_with_eret_to_next:
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mov x9, x30
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b 1f
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call_with_eret:
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mov x9, x0
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1:
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msr elr_el3, x9
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/* Same exception vector */
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mrs x9, vbar_el3
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msr vbar_el2, x9
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eret
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b .
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.global disable_mmu_el3
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func disable_mmu_el3
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mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT)
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do_disable_mmu:
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mrs x0, sctlr_el3
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bic x0, x0, x1
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msr sctlr_el3, x0
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isb // ensure MMU is off
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dsb sy
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ret
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endfunc disable_mmu_el3
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.global disable_mmu_icache_el3
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func disable_mmu_icache_el3
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mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
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b do_disable_mmu
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endfunc disable_mmu_icache_el3
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.global jump_bl31
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func jump_bl31
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mov x20, x0 // bl31_entry
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mov x21, x1 // bl31_params
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bl disable_mmu_icache_el3
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tlbi alle3
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mov x0, x21 // bl31_params
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mov x1, xzr
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blr x20
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endfunc jump_bl31
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